From 24dd44b43dcac60dc534a0ce93f56a8104d05c82 Mon Sep 17 00:00:00 2001 From: mahi Date: Thu, 9 Aug 2012 14:15:10 +0200 Subject: [PATCH] Dbg: Added pls configs --- .../freescale_mpc5567evb_debug_jtag.cfg | 273 ++++++++++++++++++ .../Targets/isystem_mpc5516_debug_jtag_z1.cfg | 183 ++++++++++++ 2 files changed, 456 insertions(+) create mode 100644 tools/pls/UDE 3.2/Targets/freescale_mpc5567evb_debug_jtag.cfg create mode 100644 tools/pls/UDE 3.2/Targets/isystem_mpc5516_debug_jtag_z1.cfg diff --git a/tools/pls/UDE 3.2/Targets/freescale_mpc5567evb_debug_jtag.cfg b/tools/pls/UDE 3.2/Targets/freescale_mpc5567evb_debug_jtag.cfg new file mode 100644 index 00000000..d5c96ffc --- /dev/null +++ b/tools/pls/UDE 3.2/Targets/freescale_mpc5567evb_debug_jtag.cfg @@ -0,0 +1,273 @@ +[Main] +Signature=UDE_TARGINFO_2.0 +Description=Freescale MPC5567EVB Evalboard with MPC5567 (Jtag) +Description1=MMU preinitialized, memory mapping 1:1 +Description2=512k 16Bit synchronous SRAM at CS0 mapped at 0x3FF80000 +Description3=FLASH programming prepared but not enabled +Description4=Write Filter for BAM Module +MCUs=Controller0 +Architecture=PowerPC +Vendor=Freescale +Board=MPC5567 Evaluation Board + +[Controller0] +Family=PowerPC +Type=MPC5567 +Enabled=1 +IntClock=20000 +MemDevs=BAMWriteFilter +ExtClock=20000 + +[Controller0.Core] +Protocol=PPCJTAG +Enabled=1 + +[Controller0.Core.LoadedAddOn] +UDEMemtool=1 + +[Controller0.Core.PpcJtagTargIntf] +PortType=Default +ResetWaitTime=50 +MaxJtagClk=5000 +DoSramInit=1 +UseNexus=1 +AdaptiveJtagPhaseShift=1 +ConnOption=Default +ChangeJtagClk=-1 +HaltAfterReset=1 +SimioAddr=g_JtagSimioAccess +FreezeTimers=1 +InvalidTlbOnReset=1 +InvalidateCache=0 +ForceCacheFlush=1 +IgnoreLockedLines=1 +ExecInitCmds=1 +JtagTapNumber=0 +JtagNumOfTaps=1 +JtagNumIrBefore=0 +JtagNumIrAfter=0 +AllowMmuSetup=1 +JtagViaPod=0 +TargetPort=Default +UseExtReset=0 +ChangeMsr=0 +ChangeMsrValue=0x0 +ExecOnStartCmds=0 +ExecOnHaltCmds=0 +ExecOnHaltCmdsWhileHalted=0 +EnableProgramTimeMeasurement=0 +HandleWdtBug=0 +ForceEndOfReset=0 +UseHwResetMode=0 +HandleNexusAccessBug=0 +DoNotEnableTrapSwBrp=0 +AllowResetOnCheck=0 +BootPasswd0=0xFEEDFACE +BootPasswd1=0xCAFEBEEF +BootPasswd2=0xFFFFFFFF +BootPasswd3=0xFFFFFFFF +BootPasswd4=0xFFFFFFFF +BootPasswd5=0xFFFFFFFF +BootPasswd6=0xFFFFFFFF +BootPasswd7=0xFFFFFFFF + +[Controller0.BAMWriteFilter] +Description=BAM WriteAccess Filter +Range0Start=0xFFFFC000 +Range0Size=0x4000 +Enabled=1 +Handler=AccessFilter +Mode=ReadOnly + +[Controller0.PFLASH] +Enabled=1 +EnableMemtoolByDefault=1 + +[Controller0.Core.PpcJtagTargIntf.InitScript] +// TLB invalidate +SETSPR 0x3F4 0x2 0xFFFFFFFF +// select TLB 1 +SETSPR 0x274 0x10000108 0xFFFFFFFF + + +// programm peripheral B modules + +// TLB 1, entry 0 +SETSPR 0x270 0x10000000 0xFFFFFFFF +// Valid, protect against invalidation, global entry, size=1MB +SETSPR 0x271 0xC0000500 0xFFFFFFFF +// effective page number FFF00000, I,G +SETSPR 0x272 0xFFF0000A 0xFFFFFFFF +// real page FFF00000, UX,SX,UW,SW,UR,SR +SETSPR 0x273 0xFFF0003F 0xFFFFFFFF +// execute TLB write instruction +EXECOPCODE 0x7C0007A4 + +// programm internal Flash, no cache because of flash +// TLB 1, entry 1 +SETSPR 0x270 0x10010000 0xFFFFFFFF +// Valid, protect against invalidation, global entry, size=16MB +SETSPR 0x271 0xC0000700 0xFFFFFFFF +// effective page number 00000000 +SETSPR 0x272 0x8 0xFFFFFFFF +// real page 00000000, UX,SX,UW,SW,UR,SR +SETSPR 0x273 0x3F 0xFFFFFFFF +// execute TLB write instruction +EXECOPCODE 0x7C0007A4 + +// programm external memory +// TLB 1, entry 2 +SETSPR 0x270 0x10020000 0xFFFFFFFF +// Valid, protect against invalidation, global entry, size=16MB +SETSPR 0x271 0xC0000700 0xFFFFFFFF +// effective page number 20000000 +SETSPR 0x272 0x20000008 0xFFFFFFFF +// real page 20000000, UX,SX,UW,SW,UR,SR +SETSPR 0x273 0x2000003F 0xFFFFFFFF +// execute TLB write instruction +EXECOPCODE 0x7C0007A4 + +// programm internal SRAM +// TLB 1, entry 3 +SETSPR 0x270 0x10030000 0xFFFFFFFF +// Valid, protect against invalidation, global entry, size=256k +SETSPR 0x271 0xC0000400 0xFFFFFFFF +// effective page number 40000000, I +SETSPR 0x272 0x40000008 0xFFFFFFFF +// real page 0x40000008, UX,SX,UW,SW,UR,SR +SETSPR 0x273 0x4000003F 0xFFFFFFFF +// execute TLB write instruction +EXECOPCODE 0x7C0007A4 + +// programm peripheral A modules +// TLB 1, entry 4 +SETSPR 0x270 0x10040000 0xFFFFFFFF +// Valid, protect against invalidation, global entry, size=1MB +SETSPR 0x271 0xC0000500 0xFFFFFFFF +// effective page number C3F00000, I +SETSPR 0x272 0xC3F0000A 0xFFFFFFFF +// real page C3F00000, UX,SX,UW,SW,UR,SR +SETSPR 0x273 0xC3F0003F 0xFFFFFFFF +// execute TLB write instruction +EXECOPCODE 0x7C0007A4 + +// programm external memory +// TLB 1, entry 5 +SETSPR 0x270 0x10050000 0xFFFFFFFF +// Valid, protect against invalidation, global entry, size=4MB +SETSPR 0x271 0xC0000600 0xFFFFFFFF +// effective page number 3FC00000, I +SETSPR 0x272 0x3FC0000A 0xFFFFFFFF +// real page 3FC00000, UX,SX,UW,SW,UR,SR +SETSPR 0x273 0x3FC0003F 0xFFFFFFFF +// execute TLB write instruction +EXECOPCODE 0x7C0007A4 + +// cache invalidate +SETSPR 0x3F2 0x3 0x3 + +// setup IVOPR +// points to internal memory at 0x40000000 +SETSPR 0x3F 0x40000000 0xFFFFFFFF +// MMU data error vector offset +SETSPR 0x19D 0x0 0xFFFFFFFF +// MMU instruction error vector offset +SETSPR 0x19E 0x0 0xFFFFFFFF + +// setup clock to 128MHz +SET 0xC3F80000 0x46046000 0xFFFFFFFF +WAIT 0x5 + +// setup pins +// setup address bus pins, alternate function 1, strengh 20pF +// ADDR8/9 Pad Configuration Register (PCR) +SET 0xC3F90048 0x4400440 0xFFFFFFFF +// ADDR10/11 Pad Configuration Register (PCR) +SET 0xC3F9004C 0x4400440 0xFFFFFFFF +// ADDR12/13 Pad Configuration Register (PCR) +SET 0xC3F90050 0x4400440 0xFFFFFFFF +// ADDR14/15 Pad Configuration Register (PCR) +SET 0xC3F90054 0x4400440 0xFFFFFFFF +// ADDR16/17 Pad Configuration Register (PCR) +SET 0xC3F90058 0x4400440 0xFFFFFFFF +// ADDR18/19 Pad Configuration Register (PCR) +SET 0xC3F9005C 0x4400440 0xFFFFFFFF +// ADDR20/21 Pad Configuration Register (PCR) +SET 0xC3F90060 0x4400440 0xFFFFFFFF +// ADDR22/23 Pad Configuration Register (PCR) +SET 0xC3F90064 0x4400440 0xFFFFFFFF +// ADDR24/25 Pad Configuration Register (PCR) +SET 0xC3F90068 0x4400440 0xFFFFFFFF +// ADDR26/27 Pad Configuration Register (PCR) +SET 0xC3F9006C 0x4400440 0xFFFFFFFF +// ADDR28/29 Pad Configuration Register (PCR) +SET 0xC3F90070 0x4400440 0xFFFFFFFF +// ADDR30/31 Pad Configuration Register (PCR) +SET 0xC3F90074 0x4400440 0xFFFFFFFF + +// setup data bus pins, alternate function 1, strengh 20pF +// DATA0/1 Configuration Register (PCR) +SET 0xC3F90078 0x4400440 0xFFFFFFFF +// DATA2/3 Pad Configuration Register (PCR) +SET 0xC3F9007C 0x4400440 0xFFFFFFFF +// DATA4/5 Pad Configuration Register (PCR) +SET 0xC3F90080 0x4400440 0xFFFFFFFF +// DATA6/7 Pad Configuration Register (PCR) +SET 0xC3F90084 0x4400440 0xFFFFFFFF +// DATA8/9 Pad Configuration Register (PCR) +SET 0xC3F90088 0x4400440 0xFFFFFFFF +// DATA10/11 Pad Configuration Register (PCR) +SET 0xC3F9008C 0x4400440 0xFFFFFFFF +// DATA12/13 Pad Configuration Register (PCR) +SET 0xC3F90090 0x4400440 0xFFFFFFFF +// DATA14/15 Pad Configuration Register (PCR) +SET 0xC3F90094 0x4400440 0xFFFFFFFF +// DATA16/17 Pad Configuration Register (PCR) +SET 0xC3F90098 0x4400440 0xFFFFFFFF +// DATA18/19 Pad Configuration Register (PCR) +SET 0xC3F9009C 0x4400440 0xFFFFFFFF +// DATA20/21 Pad Configuration Register (PCR) +SET 0xC3F900A0 0x4400440 0xFFFFFFFF +// DATA22/23 Pad Configuration Register (PCR) +SET 0xC3F900A4 0x4400440 0xFFFFFFFF +// DATA24/25 Pad Configuration Register (PCR) +SET 0xC3F900A8 0x4400440 0xFFFFFFFF +// DATA26/27 Pad Configuration Register (PCR) +SET 0xC3F900AC 0x4400440 0xFFFFFFFF +// DATA28/29 Pad Configuration Register (PCR) +SET 0xC3F900B0 0x4400440 0xFFFFFFFF +// DATA30/31 Pad Configuration Register (PCR) +SET 0xC3F900B4 0x4400440 0xFFFFFFFF + +// setup control pins, alternate function 1, strengh 20pF +// RD / /WR / /BPIDPad Configuration Register (PCR) +SET 0xC3F900BC 0x4400440 0xFFFFFFFF + +// setup WE pins, alternate function 1, strengh 20pF, enable weak PullUp +// /WE0 / /WE1Pad Configuration Register (PCR) +SET 0xC3F900C0 0x4430443 0xFFFFFFFF +// /WE2 / /WE3 Pad Configuration Register (PCR) +SET 0xC3F900C4 0x4430443 0xFFFFFFFF +//// setup OE, TS pins, alternate function 1, strengh 20pF, enable weak PullUp +// /OE / /TS Pad Configuration Register (PCR) +SET 0xC3F900C8 0x4430443 0xFFFFFFFF +//// setup CS pins, alternate function 1, strengh 20pF, enable weak PullUp +// /CS0 / /CS1 Pad Configuration Register (PCR) +SET 0xC3F90040 0x4430443 0xFFFFFFFF +// /CS2 / /CS3 Pad Configuration Register (PCR) +SET 0xC3F90044 0x4430443 0xFFFFFFFF + +// setup EBI +// CS0 at 0x3FF80000, Valid, burst enable, 16bit +// EBI_BR0 +SET 0xC3F84010 0x3FF80841 0xFFFFFFFF +// 17 waitstates +// EBI_OR0 +SET 0xC3F84014 0xFFF80000 0xFFFFFFFF + +// set clockout, GPIO, OBE, strengh 10pF +// CLKOUT Pad Configuration Register (PCR) +SET16 0xC3F9020A 0x200 0xFFFF + +[Controller0.Core.PpcJtagTargIntf.OnStartScript] +[Controller0.Core.PpcJtagTargIntf.OnHaltScript] diff --git a/tools/pls/UDE 3.2/Targets/isystem_mpc5516_debug_jtag_z1.cfg b/tools/pls/UDE 3.2/Targets/isystem_mpc5516_debug_jtag_z1.cfg new file mode 100644 index 00000000..7cbd9c29 --- /dev/null +++ b/tools/pls/UDE 3.2/Targets/isystem_mpc5516_debug_jtag_z1.cfg @@ -0,0 +1,183 @@ +[Main] +Signature=UDE_TARGINFO_2.0 +Description=iSystem MPC5516 Evalboard with MPC5516 (Jtag/Single Core debug z1) +Description1=MMU preinitialized, memory mapping 1:1 +Description2=FLASH programming prepared but not enabled +Description3=Write Filter for BAM Module +MCUs=Controller0 +Architecture=PowerPC +Vendor=iSystem +Board=MPC5516 Evaluation Board + +[Controller0] +Family=PowerPC +Type=MPC5516G +Enabled=1 +IntClock=64000 +MemDevs=BAMWriteFilter +ExtClock=8000 + +[Controller0.z1] +Protocol=PPCJTAG +Enabled=1 + +[Controller0.z1.LoadedAddOn] +UDEMemtool=1 + +[Controller0.z1.PpcJtagTargIntf] +PortType=Default +ResetWaitTime=50 +MaxJtagClk=2000 +DoSramInit=1 +UseNexus=0 +AdaptiveJtagPhaseShift=1 +ConnOption=Reset +ChangeJtagClk=12500 +HaltAfterReset=1 +SimioAddr=g_JtagSimioAccess +FreezeTimers=1 +InvalidTlbOnReset=1 +InvalidateCache=0 +ForceCacheFlush=0 +IgnoreLockedLines=0 +ExecInitCmds=1 +JtagTapNumber=0 +JtagNumOfTaps=1 +JtagNumIrBefore=0 +JtagNumIrAfter=0 + +AllowMmuSetup=1 +FlushCache=0 +UseExtReset=1 +HandleWdtBug=1 +ForceEndOfReset=0 +JtagViaPod=0 +TargetPort=Default +ChangeMsr=0 +ChangeMsrValue=0x0 +ExecOnStartCmds=0 +ExecOnHaltCmds=0 +EnableProgramTimeMeasurement=0 +UseHwResetMode=0 +HandleNexusAccessBug=0 +DoNotEnableTrapSwBrp=0 +AllowResetOnCheck=0 +BootPasswd0=0xFEEDFACE +BootPasswd1=0xCAFEBEEF +BootPasswd2=0xFFFFFFFF +BootPasswd3=0xFFFFFFFF +BootPasswd4=0xFFFFFFFF +BootPasswd5=0xFFFFFFFF +BootPasswd6=0xFFFFFFFF +BootPasswd7=0xFFFFFFFF +ExecOnHaltCmdsWhileHalted=0 + + + +[Controller0.BAMWriteFilter] +Description=BAM WriteAccess Filter +Range0Start=0xFFFFC000 +Range0Size=0x4000 +Enabled=1 +Handler=AccessFilter +Mode=ReadOnly + +[Controller0.z0] +Protocol=PPCJTAG +Enabled=0 + +[Controller0.PFLASH] +Enabled=1 +EnableMemtoolByDefault=1 + +[Controller0.z1.PpcJtagTargIntf.InitScript] +// TLB invalidate +SETSPR 0x3F4 0x2 0xFFFFFFFF +// select TLB 1 +SETSPR 0x274 0x10000108 0xFFFFFFFF + +// programm peripheral B modules +// TLB 1, entry 0 +SETSPR 0x270 0x10000000 0xFFFFFFFF +// Valid, protect against invalidation, global entry, size=1MB +SETSPR 0x271 0xC0000500 0xFFFFFFFF +// effective page number FFF00000, I,G +SETSPR 0x272 0xFFF0000A 0xFFFFFFFF +// real page FFF00000, UX,SX,UW,SW,UR,SR +SETSPR 0x273 0xFFF0003F 0xFFFFFFFF +// execute TLB write instruction +EXECOPCODE 0x7C0007A4 + +// programm internal Flash, no cache because of flash +// TLB 1, entry 1 +SETSPR 0x270 0x10010000 0xFFFFFFFF +// Valid, protect against invalidation, global entry, size=256MB +SETSPR 0x271 0xC0000900 0xFFFFFFFF +// effective page number 00000000 +SETSPR 0x272 0x08 0xFFFFFFFF +// real page 00000000, UX,SX,UW,SW,UR,SR +SETSPR 0x273 0x3F 0xFFFFFFFF +// execute TLB write instruction +EXECOPCODE 0x7C0007A4 + +// programm external memory +// TLB 1, entry 2 +SETSPR 0x270 0x10020000 0xFFFFFFFF +// Valid, protect against invalidation, global entry, size=256MB +SETSPR 0x271 0xC0000900 0xFFFFFFFF +// effective page number 20000000 +SETSPR 0x272 0x20000008 0xFFFFFFFF +// real page 20000000, UX,SX,UW,SW,UR,SR +SETSPR 0x273 0x2000003F 0xFFFFFFFF +// execute TLB write instruction +EXECOPCODE 0x7C0007A4 + +// programm internal SRAM +// TLB 1, entry 3 +SETSPR 0x270 0x10030000 0xFFFFFFFF +// Valid, protect against invalidation, global entry, size=256k +SETSPR 0x271 0xC0000400 0xFFFFFFFF +// effective page number 40000000, I +SETSPR 0x272 0x40000008 0xFFFFFFFF +// real page 0x40000008, UX,SX,UW,SW,UR,SR +SETSPR 0x273 0x4000003F 0xFFFFFFFF +// execute TLB write instruction +EXECOPCODE 0x7C0007A4 + +// setup IVOPR +// points to internal memory at 0x40000000 +SETSPR 0x3F 0x40000000 0xFFFFFFFF + +// enable external osscillator, CRP CLKSRC +SET 0xFFFEC000 0x00040000 0x00040000 + +// SIU_ECCR 1/4 clock +SET 0xFFFE8984 0x3 0xFFFFFFFF + +// setup clock to 64MHz +// FMPLL_ESYNSCR2 Set ERFD to initial value of 8 +SET 0xFFFF000C 0x6 0xFFFFFFFF +// FMPLL_ESYNSCR1 +SET 0xFFFF0008 0xF0000020 0xFFFFFFFF +WAIT 0x10 +// Set ERFD to final value for 64 MHz sysclk +SET 0xFFFF000C 0x5 0xFFFFFFFF +// Select PLL for sysclk, SIU_SYSCLK +SET 0xFFFE89A0 0x80000000 0xC0000000 + +// set Z0 core to reset +SET 0xFFFEC054 0xFFFFFFFE + +// disable checkstop reset, SIU_SRCR +SET 0xFFFE8010 0x0 0x0000C000 + +// disable LVI reset +SET 0xFFFEC070 0x0 0x4000000 + +// set EBI clockout pin +SET16 0xFFFE80CC 0x604 0xFFFF + + +[Controller0.z1.PpcJtagTargIntf.OnStartScript] + +[Controller0.z1.PpcJtagTargIntf.OnHaltScript] -- 2.39.2