#include "Det.h"\r
#include "CanIf_Cbk.h"\r
#include "Os.h"\r
-#include "irq.h"\r
+#include "isr.h"\r
#include "Mcu.h"\r
+#include "arc.h"\r
\r
#define DCAN1_MAX_MESSAGEBOXES 64\r
#define DCAN2_MAX_MESSAGEBOXES 64\r
#define Dem_ReportErrorStatus(...)\r
#endif\r
\r
+//static sint8 IfRegId = 0;\r
+\r
/* Macro for waiting until busy flag is 0 */\r
#define DCAN_WAIT_UNTIL_NOT_BUSY(ControllerId, IfRegId) \\r
{ \\r
/* Used to switch between IF1 and IF2 of DCAN */\r
static uint8 IfRegId = 0;\r
\r
+\r
/* Used to order Data Bytes according to hardware registers in DCAN */\r
static const uint8 ElementIndex[] = {3, 2, 1, 0, 7, 6, 5, 4};\r
\r
return 0;\r
}\r
\r
-uint32 usedBoxes[64] = {0};\r
+#define DCAN_MC_NEWDAT 15\r
+#define DCAN_MC_EOB 7\r
+\r
+uint32 usedRxBoxes[64] = {0};\r
+uint32 usedTxBoxes[64] = {0};\r
+\r
+static inline Can_ReturnType handleRxMsgObject(uint8 MsgNr, const Can_HardwareObjectType *hoh, CanControllerIdType controller) {\r
+ uint32 MsgId;\r
+ uint8 MsgDlc;\r
+ uint8 DataByteIndex;\r
+ uint8 *SduPtr;\r
+\r
+ /* Wait until Busy Flag is 0 */\r
+ DCAN_WAIT_UNTIL_NOT_BUSY(controller, IfRegId);\r
+\r
+ // Read message control\r
+ uint32 mc = CanRegs[controller]->IFx[IfRegId].MC;\r
+ uint32 arb = CanRegs[controller]->IFx[IfRegId].ARB;\r
+\r
+ // Is there a new message waiting?\r
+ if (!(mc & (1 << DCAN_MC_NEWDAT))) {\r
+ return CAN_NOT_OK; // Nothing more to be done.\r
+ }\r
+\r
+ // For debug\r
+ if (MsgNr == 0) {\r
+ usedRxBoxes[MsgNr]++;\r
+ } else {\r
+ usedRxBoxes[MsgNr]++;\r
+ }\r
+\r
+\r
+ /* Extended Id */\r
+ if(arb & 0x40000000) {\r
+ /* Bring Id to standardized format (MSB marks extended Id) */\r
+ MsgId = (arb & 0x1FFFFFFF) | 0x80000000;\r
+\r
+ } else { /* Standard Id */\r
+ /* Bring Id to standardized format (MSB marks extended Id) */\r
+ MsgId = (arb & 0x1FFC0000) >> 18;\r
+ }\r
+\r
+ /* DLC (Max 8) */\r
+ MsgDlc = mc & 0x000F;\r
+ if(MsgDlc > 8) {\r
+ MsgDlc = 8;\r
+ }\r
+\r
+ /* Let SduPtr point to Shadow Buffer */\r
+ SduPtr = RxShadowBuf[controller];\r
+\r
+ /* Copy Message Data to Shadow Buffer */\r
+ for(DataByteIndex = 0; DataByteIndex < MsgDlc; DataByteIndex++)\r
+ {\r
+ SduPtr[DataByteIndex] = CanRegs[controller]->IFx[IfRegId].DATx[ElementIndex[DataByteIndex]];\r
+ }\r
+\r
+ /* Indicate successful Reception */\r
+ CanIf_RxIndication(hoh->CanObjectId, MsgId, MsgDlc, SduPtr);\r
+\r
+ // Is this the last message object of the FIFO?\r
+ if (mc & (1 << DCAN_MC_EOB)) {\r
+ return CAN_NOT_OK;\r
+ }\r
+\r
+ return CAN_OK;\r
+}\r
+\r
\r
void Can_InterruptHandler(CanControllerIdType controller)\r
{\r
uint32 MsgNr;\r
- uint32 MsgId;\r
- uint8 MsgDlc;\r
- uint8 DataByteIndex;\r
- uint8 *SduPtr;\r
-\r
- Can_DisableControllerInterrupts(controller);\r
\r
uint32 ir = CanRegs[controller]->IR;\r
\r
- if(ir == 0x8000)\r
- {\r
+\r
+ if(ir == 0x8000) { // This is an error interrupt\r
+\r
uint32 sr = CanRegs[controller]->SR;\r
- /* WakeUp Pending */\r
- if(sr & 0x00000200) {\r
+\r
+ if(sr & 0x00000200) { /* WakeUp Pending */\r
/* Set Init Bit, so that Controller is in Stop state */\r
CanRegs[controller]->CTL |= 0x1;\r
// EcuM_CheckWakeUp(ControllerConfig[0].WakeupSrc);\r
\r
}\r
- /* Bus Off */\r
- if(sr & 0x00000080) {\r
+\r
+ if(sr & 0x00000080) { /* Bus Off */\r
Can_SetControllerMode(controller, CAN_T_STOP); // CANIF272\r
//CanIf_ControllerBusOff(0); // Not implemented in Arctic Core\r
\r
}\r
- }\r
- else\r
- {\r
- MsgNr = ir;\r
-\r
\r
- if (MsgNr == 0) {\r
- usedBoxes[MsgNr]++;\r
- } else {\r
- usedBoxes[MsgNr]++;\r
- }\r
- \r
+ } else if (ir > 0 && ir < 0x8000){ // This interrupt is from a message object.\r
+ MsgNr = ir;\r
\r
- /* Read Arbitration, Control and Data Bits and clear IntPnd and NewDat*/\r
- CanRegs[controller]->IFx[IfRegId].COM = 0x003F0000 | MsgNr;\r
+ /* Read Arbitration and control */\r
+ CanRegs[controller]->IFx[IfRegId].COM = 0x003F0000 | MsgNr;\r
\r
- /* Wait until Busy Flag is 0 */\r
- DCAN_WAIT_UNTIL_NOT_BUSY_NO_RV(controller, IfRegId);\r
+ /* Wait until Busy Flag is 0 */\r
+ DCAN_WAIT_UNTIL_NOT_BUSY_NO_RV(controller, IfRegId);\r
\r
/* Transmit Object */\r
if(CanRegs[controller]->IFx[IfRegId].ARB & 0x20000000)\r
{\r
+ // For debug\r
+ if (MsgNr == 0) {\r
+ usedTxBoxes[MsgNr]++;\r
+ } else {\r
+ usedTxBoxes[MsgNr]++;\r
+ }\r
+\r
/* Reset TxRqst-Array Element */\r
ControllerConfig[controller].TxPtr[MsgNr - 1] = 0;\r
/* A Message was successfully transmitted */\r
CanIf_TxConfirmation(ControllerConfig[controller].PduPtr[MsgNr - 1].swPduHandle);\r
- }\r
+\r
/* Receive Object */\r
- else\r
- {\r
- /* Extended Id */\r
- if(CanRegs[controller]->IFx[IfRegId].ARB & 0x40000000)\r
- {\r
- /* Bring Id to standardized format (MSB marks extended Id) */\r
- MsgId = (CanRegs[controller]->IFx[IfRegId].ARB & 0x1FFFFFFF) | 0x80000000;\r
- }\r
- /* Standard Id */\r
- else\r
- {\r
- /* Bring Id to standardized format (MSB marks extended Id) */\r
- MsgId = (CanRegs[controller]->IFx[IfRegId].ARB & 0x1FFC0000) >> 18;\r
- }\r
- /* DLC (Max 8) */\r
- MsgDlc = CanRegs[controller]->IFx[IfRegId].MC & 0x000F;\r
- if(MsgDlc > 8)\r
- {\r
- MsgDlc = 8;\r
- }\r
- /* Let SduPtr point to Shadow Buffer */\r
- SduPtr = RxShadowBuf[controller];\r
+ } else {\r
\r
- /* Copy Message Data to Shadow Buffer */\r
- for(DataByteIndex = 0; DataByteIndex < MsgDlc; DataByteIndex++)\r
- {\r
- SduPtr[DataByteIndex] = CanRegs[controller]->IFx[IfRegId].DATx[ElementIndex[DataByteIndex]];\r
- }\r
- /* Indicate successful Reception */\r
- const Can_HardwareObjectType *hoh = Can_FindRxHoh(controller, MsgNr);\r
- CanIf_RxIndication(hoh->CanObjectId, MsgId, MsgDlc, SduPtr);\r
+ // Handle all of the message objects in this FIFO buffer.\r
+ const Can_HardwareObjectType *hoh = Can_FindRxHoh(controller, MsgNr);\r
+ for(; MsgNr < ControllerConfig[controller].MaxBoxes; MsgNr++) {\r
+ if (!(hoh->Can_Arc_MbMask & (1 << (MsgNr - 1)))) {\r
+ continue;\r
+ }\r
+\r
+ /* Read setup hardware to read arbitration, control and data Bits of the message object.\r
+ * Clear IntPnd and Tx */\r
+ if (MsgNr != ir) { // Don't do this the first time.\r
+ CanRegs[controller]->IFx[IfRegId].COM = 0x003F0000 | MsgNr;\r
+ }\r
+\r
+ if (handleRxMsgObject(MsgNr, hoh, controller) == CAN_NOT_OK) {\r
+ break; // We have parsed the last object of this FIFO.\r
+ }\r
+ }\r
\r
}\r
}\r
- Can_EnableControllerInterrupts(controller);\r
}\r
\r
void Can1_InterruptHandler() {\r
uint8 MsgNr;\r
uint32 ErrCounter;\r
uint32 Eob;\r
+ imask_t state;\r
\r
/* DET Error Check */\r
#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
return;\r
}\r
#endif \r
- \r
+\r
+ Irq_Save(state);\r
+\r
// TODO This should be used instead of other variables in the Can_Lcfg file.\r
CurConfig = Config;\r
\r
CanRegs[Controller]->CTL = 0x02001641 | DCAN_IRQ_MASK | (CanControllerConfigData[Controller].Can_Arc_Loopback << 7);// | (CanControllerConfigData[Controller].CanWakeupProcessing >> 8) | (CanControllerConfigData[Controller].CanBusOffProcessing >> 7);\r
#else\r
CanRegs[Controller]->CTL = 0x00001641 | DCAN_IRQ_MASK | (CanControllerConfigData[Controller].Can_Arc_Loopback << 7);// | (CanControllerConfigData[Controller].CanWakeupProcessing >> 8) | (CanControllerConfigData[Controller].CanBusOffProcessing >> 7);\r
+\r
+ /* Parity Off */\r
+ CanRegs[Controller]->CTL = 0x00020043 | DCAN_IRQ_MASK | (CanControllerConfigData[Controller].Can_Arc_Loopback << 7);// | (CanControllerConfigData[Controller].CanWakeupProcessing >> 8);\r
#endif \r
/* LEC 7, TxOk, RxOk, PER */\r
CanRegs[Controller]->SR = 0x0000011F;\r
+ //CanRegs[Controller]->SR = 0x0000031F; // according to HalCoGen\r
\r
/* Test Mode only for Development time: Silent Loopback */\r
if (CanControllerConfigData[Controller].Can_Arc_Loopback) {\r
*(ControllerConfig[Controller].CancelPtr + MsgNr) = 0;\r
*(ControllerConfig[Controller].TxPtr + MsgNr) = 0;\r
\r
+ CanRegs[Controller]->ABOT = 0; // added manually according to HalCoGen, maybe delete???\r
+\r
DCAN_WAIT_UNTIL_NOT_BUSY_NO_RV(Controller, IfRegId);\r
\r
// Initialize all message objects for this controller to invalid state.\r
CanRegs[Controller]->IFx[IfRegId].ARB = 0x00000000;\r
/* Start writing Arbitration Bits */\r
CanRegs[Controller]->IFx[IfRegId].COM = 0x00A80000 | (MsgNr + 1);\r
+ // CanRegs[Controller]->IFx[IfRegId].COM = 0x00F80000 | (MsgNr + 1); maybe right, later it's used again??\r
\r
/* Use IFx[0] and IFx[1] alternating */\r
IfRegId ^= 1;\r
| (CanControllerConfigData[Controller].CanTxProcessing << 1) // Tx confirmation interrupt enabled\r
| (Eob & ~(hoh->CanObjectType >> 22)); // Eob, only for Rx.\r
\r
+ //CanRegs[Controller]->IFx[IfRegId].MC = 0x00001008;\r
+\r
//CanRegs[Controller]->IFx[IfRegId].MC = 0x00001008 | CanControllerConfigData[Controller].CanRxProcessing | (CanControllerConfigData[Controller].CanTxProcessing) | Eob & ~(hoh->CanObjectType >> 17);\r
\r
if(hoh->CanIdType == CAN_ID_TYPE_STANDARD) /* Standard Identifiers */\r
{\r
/* Only Standard-Ids are accepted, Set Mask */\r
+ // HalCoGen\r
CanRegs[Controller]->IFx[IfRegId].MASK = 0x80000000 | ((*(hoh->CanFilterMaskRef)) & 0x1FFFFFFF);\r
/* Message valid, Id, Direction */\r
CanRegs[Controller]->IFx[IfRegId].ARB = 0x80000000 | ((hoh->CanIdValue & 0x7FF) << 18) | hoh->CanObjectType;\r
else if(hoh->CanIdType == CAN_ID_TYPE_EXTENDED) /* Extended Identifiers */\r
{\r
/* Only Extended-Ids are accepted, Set Mask */\r
- CanRegs[Controller]->IFx[IfRegId].MASK = 0x80000000 | ((*(hoh->CanFilterMaskRef)) & 0x1FFFFFFF);\r
+ CanRegs[Controller]->IFx[IfRegId].MASK = 0xC0000000 | ((*(hoh->CanFilterMaskRef)) & 0x1FFFFFFF); // HalCoGen\r
+ // C = bit 30: The message direction bit (Dir) is used for acceptance filtering.\r
+ // CanRegs[Controller]->IFx[IfRegId].MASK = 0x80000000 | ((*(hoh->CanFilterMaskRef)) & 0x1FFFFFFF);\r
/* Message valid, Id, Direction */\r
CanRegs[Controller]->IFx[IfRegId].ARB = 0xC0000000 | (hoh->CanIdValue & 0x1FFFFFFF) | hoh->CanObjectType;\r
}\r
/* Set Bit Timing Register */\r
CanRegs[Controller]->BTR = Can_CalculateBTR(Controller);\r
\r
- /* Reset CCE Bit */\r
+ /* Reset CCE Bit, i.e. disable configuration change */\r
CanRegs[Controller]->CTL &= ~0x00000040;\r
\r
#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
#endif\r
\r
// Install interrupt handlers\r
- TaskType tid;\r
if (CanControllerConfigData[Controller].CanControllerId == DCAN1) {\r
- tid = Os_Arc_CreateIsr(Can1_InterruptHandler, 2 ,"DCAN1Level0");\r
- Irq_AttachIsr2(tid, NULL, 16);\r
-\r
- tid = Os_Arc_CreateIsr(Can1_InterruptHandler, 2, "DCAN1Level1");\r
- Irq_AttachIsr2(tid, NULL, 29);\r
+ ISR_INSTALL_ISR2("DCAN1Level0",Can1_InterruptHandler,CAN1_LEVEL_0,2,0);\r
+ ISR_INSTALL_ISR2("DCAN1Level1",Can1_InterruptHandler,CAN1_LEVEL_1,2,0);\r
\r
} else if (CanControllerConfigData[Controller].CanControllerId == DCAN2) {\r
- tid = Os_Arc_CreateIsr(Can2_InterruptHandler, 2 ,"DCAN2Level0");\r
- Irq_AttachIsr2(tid, NULL, 35);\r
-\r
- tid = Os_Arc_CreateIsr(Can2_InterruptHandler, 2, "DCAN2Level1");\r
- Irq_AttachIsr2(tid, NULL, 42);\r
+ ISR_INSTALL_ISR2("DCAN2Level0",Can2_InterruptHandler,CAN2_LEVEL_0,2,0);\r
+ ISR_INSTALL_ISR2("DCAN2Level1",Can2_InterruptHandler,CAN2_LEVEL_1,2,0);\r
\r
} else if (CanControllerConfigData[Controller].CanControllerId == DCAN3) {\r
- tid = Os_Arc_CreateIsr(Can3_InterruptHandler, 2 ,"DCAN3Level0");\r
- Irq_AttachIsr2(tid, NULL, 45);\r
-\r
- tid = Os_Arc_CreateIsr(Can3_InterruptHandler, 2, "DCAN3Level1");\r
- Irq_AttachIsr2(tid, NULL, 55);\r
+ ISR_INSTALL_ISR2("DCAN3Level0",Can3_InterruptHandler,CAN3_LEVEL_0,2,0);\r
+ ISR_INSTALL_ISR2("DCAN3Level1",Can3_InterruptHandler,CAN3_LEVEL_1,2,0);\r
\r
}\r
\r
ModuleState = CAN_READY;\r
#endif\r
\r
+ Irq_Restore(state);\r
\r
+}\r
+\r
+// Unitialize the module\r
+void Can_DeInit()\r
+{\r
\r
+ return;\r
}\r
\r
\r
{\r
uint8 MsgNr;\r
uint32 ErrCounter;\r
+ imask_t state;\r
\r
#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
if(Config == NULL)\r
}\r
#endif \r
\r
+ Irq_Save(state);\r
+\r
ErrCounter = CAN_TIMEOUT_DURATION;\r
\r
//for(MsgNr = 0; MsgNr < ControllerConfig[Controller].MessageBoxCount; MsgNr++)\r
\r
DCAN_WAIT_UNTIL_NOT_BUSY_NO_RV(Controller, IfRegId);\r
\r
- /* Read actual MaskRegister value of MessageObject */\r
+ /* Read actual MaskRegister value of MessageObject; TxRqst/NewDat */\r
CanRegs[Controller]->IFx[IfRegId].COM = 0x004C0000 | (MsgNr);\r
\r
DCAN_WAIT_UNTIL_NOT_BUSY_NO_RV(Controller, IfRegId);\r
/* Set new Mask */\r
CanRegs[Controller]->IFx[IfRegId].MASK |= (*(hoh->CanFilterMaskRef)) & 0x1FFFFFFF;\r
/* Write new Mask to MaskRegister */\r
- CanRegs[Controller]->IFx[IfRegId].COM = 0x00C80000 | (MsgNr);\r
+ CanRegs[Controller]->IFx[IfRegId].COM = 0x00C80000 | (MsgNr); // E8??\r
\r
IfRegId ^= 1;\r
}\r
/* Clear CCE Bit */\r
CanRegs[Controller]->CTL &= ~0x00000040;\r
\r
+ Irq_Restore(state);\r
}\r
\r
\r
break;\r
\r
case CAN_T_SLEEP:\r
- /* Set PDR Bit */\r
+ /* Set PDR Bit - Local Power Down Mode requested */\r
CanRegs[Controller]->CTL |= 0x01000000;\r
/* Save actual Register status */\r
RegBuf = CanRegs[Controller]->CTL;\r
Can_PduType *CurPduArrayPtr;\r
uint8 *CurCancelRqstPtr;\r
uint8 *CurTxRqstPtr;\r
+ imask_t state;\r
\r
- CurSduPtr = PduInfo->sdu;\r
+ CurSduPtr = PduInfo->sdu; // e.g. ComArcIPduBuffer_TX_PDU\r
\r
\r
/* DET Error Check */\r
if (!(mbMask & 1)) {\r
continue; // This message object is not part of this hoh.\r
}\r
+ /* Check if TxRqst Bit of MsgObject is set */\r
+ if(CanRegs[ControllerId]->TRx[MsgNr >> 5] & (1 << (MsgNr & 0x1F))) // (1 << (MsgNr & 0x1F)) - bitIndex\r
+ {\r
+ continue;\r
+ }\r
+ break;\r
}\r
\r
+ /* Check if TxRqst Bit of MsgObject is set */\r
+ if(CanRegs[ControllerId]->TRx[MsgNr >> 5] & (1 << (MsgNr & 0x1F)))\r
+ {\r
+ return CAN_BUSY;\r
+ }\r
+\r
CurPduArrayPtr = ControllerConfig[ControllerId].PduPtr + (MsgNr - 1);\r
CurCancelRqstPtr = ControllerConfig[ControllerId].CancelPtr + (MsgNr - 1);\r
CurTxRqstPtr = ControllerConfig[ControllerId].TxPtr + (MsgNr - 1);\r
\r
/* Bring Id Value to appropriate format and set ArbRegValue */\r
- if(PduInfo->id & 0x80000000)\r
- {\r
+ if( hoh->CanIdType == CAN_ID_TYPE_EXTENDED ) {\r
/* MsgVal, Ext, Transmit, Extended Id */ \r
- ArbRegValue = 0xD0000000 | (PduInfo->id & 0x1FFFFFFF);\r
- }\r
- else\r
- {\r
+ ArbRegValue = 0xE0000000 | (PduInfo->id & 0x1FFFFFFF);\r
+ } else {\r
/* MsgVal, Std, Transmit, Standard Id */ \r
ArbRegValue = 0xA0000000 | ((PduInfo->id & 0x7FF) << 18);\r
}\r
\r
- /* Check if TxRqst Bit of MsgObject is set */\r
- if(CanRegs[ControllerId]->TRx[MsgNr >> 5] & (1 << (MsgNr & 0x1F)))\r
- {\r
- return CAN_BUSY;\r
- }\r
\r
DCAN_WAIT_UNTIL_NOT_BUSY(ControllerId, IfRegId);\r
\r
+ // We cannot allow an interrupt or other task to play with the COM, MC and ARB registers here.\r
+ Irq_Save(state);\r
+\r
\r
/* Set NewDat, TxIE (dep on ControllerConfig), TxRqst, EoB and DLC */\r
CanRegs[ControllerId]->IFx[IfRegId].MC = 0x00000100 // Tx request\r
| 0x00000080 // Eob should be set to one for tx\r
| (0x000F & PduInfo->length) // Set DLC\r
- | CanControllerConfigData[ControllerId].CanRxProcessing\r
| (CanControllerConfigData[ControllerId].CanTxProcessing << 1); // Tx confirmation interrupt enabled\r
\r
-\r
/* Set ArbitrationRegister */\r
CanRegs[ControllerId]->IFx[IfRegId].ARB = ArbRegValue;\r
\r
+\r
/* Set Databytes */\r
for(DataByteIndex = 0; DataByteIndex < PduInfo->length; DataByteIndex++)\r
{\r
\r
IfRegId ^= 1;\r
\r
+ Irq_Restore(state);\r
return CAN_OK;\r
}\r
\r
projects / arc.git / blobdiff