Isr almost done

[arc.git] / arch / ppc / mpc55xx / kernel / irq.c

diff --git a/arch/ppc/mpc55xx/kernel/irq.c b/arch/ppc/mpc55xx/kernel/irq.c
index d95ad9c8f3795ea9b8b6ade8003f63b0491f421f..75300c105ae97b1f282e6b162dec3f7b35840f45 100644 (file)
--- a/arch/ppc/mpc55xx/kernel/irq.c
+++ b/arch/ppc/mpc55xx/kernel/irq.c
@@ -1,3 +1,4 @@
+\r
 /* -------------------------------- Arctic Core ------------------------------\r
  * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
  *\r
@@ -13,48 +14,47 @@
  * for more details.\r
  * -------------------------------- Arctic Core ------------------------------*/\r
 \r
+/* ----------------------------[includes]------------------------------------*/\r
+/* ----------------------------[private define]------------------------------*/\r
+/* ----------------------------[private macro]-------------------------------*/\r
+/* ----------------------------[private typedef]-----------------------------*/\r
+/* ----------------------------[private function prototypes]-----------------*/\r
+/* ----------------------------[private variables]---------------------------*/\r
+/* ----------------------------[private functions]---------------------------*/\r
+/* ----------------------------[public functions]----------------------------*/\r
+\r
+\r
+/* ----------------------------[includes]------------------------------------*/\r
+\r
 #include "internal.h"\r
-#include "asm_book_e.h"\r
 #include "irq_types.h"\r
 #include "mpc55xx.h"\r
-#if !defined(USE_KERNEL)\r
-#include "Mcu.h"\r
-#endif\r
-\r
-#if defined(USE_KERNEL)\r
 #include "pcb.h"\r
 #include "sys.h"\r
 #include "internal.h"\r
 #include "task_i.h"\r
 #include "hooks.h"\r
-\r
-#if 0\r
-#define INTC_SSCIR0_CLR7                                       7\r
-#define MLB_SERVICE_REQUEST                                    293\r
-#define CRITICAL_INPUT_EXCEPTION                       320\r
-#define DEBUG_EXCEPTION                                                335\r
-#define NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS    336\r
-#endif\r
-\r
 #include "debug.h"\r
-#endif\r
-#include "irq.h"\r
-\r
-static void dump_exception_regs( uint32_t *regs );\r
+#include "isr.h"\r
+#include <stdint.h>\r
 \r
+/* ----------------------------[private define]------------------------------*/\r
+/* ----------------------------[private macro]-------------------------------*/\r
+/* ----------------------------[private typedef]-----------------------------*/\r
 typedef void (*f_t)( uint32_t *);\r
-//typedef void (*func_t)();\r
-//extern vfunc_t Irq_VectorTable[];\r
-extern void exception_tbl(void);\r
 \r
+/* ----------------------------[private function prototypes]-----------------*/\r
+//extern uintptr_t Irq_VectorTable[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];\r
+//extern uint8 Irq_IsrTypeTable[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];\r
+//extern const OsIsrConstType *Irq_Map[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];\r
 \r
+static void dumpExceptionRegs( uint32_t *regs );\r
 \r
-#if defined(USE_KERNEL)\r
-extern void * Irq_VectorTable[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];\r
-extern uint8 Irq_IsrTypeTable[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];\r
-#else\r
-extern func_t Irq_VectorTable[];\r
-#endif\r
+/* ----------------------------[private variables]---------------------------*/\r
+extern void exception_tbl(void);\r
+\r
+/* ----------------------------[private functions]---------------------------*/\r
+/* ----------------------------[public functions]----------------------------*/\r
 \r
 // write 0 to pop INTC stack\r
 void Irq_Init( void ) {\r
@@ -113,17 +113,6 @@ void Irq_Init( void ) {
          INTC.MCR.B.VTES = 0; // 4 byte offset between entries\r
        #endif\r
 \r
-\r
-         // Pointless in software vector more???\r
-#if 0\r
-         // Check alignment requirements for the INTC table\r
-         assert( (((uint32_t)&Irq_VectorTable[0]) & 0x7ff) == 0 );\r
-       #if defined(CFG_MPC5516)\r
-         INTC.IACKR_PRC0.R = (uint32_t) & Irq_VectorTable[0]; // Set INTC ISR vector table\r
-       #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)\r
-         INTC.IACKR.R = (uint32_t) & Irq_VectorTable[0]; // Set INTC ISR vector table\r
-       #endif\r
-#endif\r
          // Pop the FIFO queue\r
          for (int i = 0; i < 15; i++)\r
          {\r
@@ -140,12 +129,11 @@ void Irq_Init( void ) {
        #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)\r
          INTC.CPR.B.PRI = 0;\r
        #endif\r
-\r
 }\r
 \r
 void Irq_EOI( void ) {\r
 #if defined(CFG_MPC5516)\r
-       struct INTC_tag *intc = &INTC;\r
+       volatile struct INTC_tag *intc = &INTC;\r
        intc->EOIR_PRC0.R = 0;\r
 #elif defined(CFG_MPC5554)||defined(CFG_MPC5567)\r
        volatile struct INTC_tag *intc = &INTC;\r
@@ -153,7 +141,7 @@ void Irq_EOI( void ) {
 #endif\r
 }\r
 \r
-\r
+#if 0\r
 /**\r
  *\r
  * @param stack_p Ptr to the current stack.\r
@@ -166,6 +154,7 @@ void *Irq_Entry( void *stack_p )
        uint32_t vector;\r
        uint32_t *stack = (uint32_t *)stack_p;\r
        uint32_t exc_vector = (EXC_OFF_FROM_BOTTOM+EXC_VECTOR_OFF)  / sizeof(uint32_t);\r
+       const OsIsrConstType *isr;\r
 \r
        // Check for exception\r
        if( stack[exc_vector]>=CRITICAL_INPUT_EXCEPTION )\r
@@ -193,47 +182,15 @@ void *Irq_Entry( void *stack_p )
                }\r
        }\r
 \r
-#if defined(USE_KERNEL)\r
-\r
-       if( Irq_GetIsrType(vector) == ISR_TYPE_1 ) {\r
-               // It's a function, just call it.\r
-               ((func_t)Irq_VectorTable[vector])();\r
+       isr = Os_IsrGet(exc_vector);\r
+       if( isr->type == ISR_TYPE_1 ) {\r
+               isr->entry();\r
                return stack;\r
        } else {\r
-               // It's a PCB\r
-               // Let the kernel handle the rest,\r
-               return Os_Isr(stack, (void *)Irq_VectorTable[vector]);\r
-       }\r
-\r
-\r
-#else\r
-               //read address\r
-       t = (func_t)Irq_VectorTable[vector];\r
-\r
-       if( t == ((void *)0) )\r
-       {\r
-               while(1);\r
+               return Os_Isr(stack, vector);\r
        }\r
-\r
-       // Enable nestling interrupts\r
-       Irq_Enable();\r
-       t();\r
-       Irq_Disable();\r
-\r
-       if( vector < INTC_NUMBER_OF_INTERRUPTS )\r
-       {\r
-               // write 0 to pop INTC stack\r
-               intc->EOIR_PRC0.R = 0;\r
-       }\r
-       return NULL;\r
-\r
-#endif\r
 }\r
-\r
-\r
-\r
-#if defined(USE_KERNEL)\r
-\r
+#endif\r
 \r
 \r
 static inline int osPrioToCpuPio( uint8_t prio ) {\r
@@ -250,6 +207,7 @@ void Irq_SetPriority( Cpu_t cpu,  IrqType vector, uint8_t prio ) {
 \r
 \r
 \r
+#if 0\r
 /**\r
  * Attach an ISR type 1 to the interrupt controller.\r
  *\r
@@ -272,7 +230,55 @@ void Irq_AttachIsr1( void (*entry)(void), void *int_ctrl, uint32_t vector,uint8_
        }\r
 \r
 }\r
+#endif\r
+\r
+\r
+void Irq_EnableVector( int16_t vector, int priority, int core ) {\r
+\r
+       if (vector < INTC_NUMBER_OF_INTERRUPTS) {\r
+               Irq_SetPriority(core,vector + IRQ_INTERRUPT_OFFSET, osPrioToCpuPio(priority));\r
+       } else if ((vector >= CRITICAL_INPUT_EXCEPTION)\r
+                       && (vector<= DEBUG_EXCEPTION)) {\r
+       } else {\r
+               /* Invalid vector! */\r
+               assert(0);\r
+       }\r
+}\r
+\r
+\r
+\r
+#if 0\r
+\r
+/**\r
+ *\r
+ * @param isrPtr\r
+ * @param type\r
+ * @param int_ctrl\r
+ */\r
+ISRType Irq_Attach( int vector ) {\r
+//     Os_Sys.isrCnt\r
+//     uint32_t vector = isrPtr->vector;\r
+\r
+       //Irq_VectorTable[vector] = (uintptr_t)isrPtr;\r
+//     Irq_IsrTypeTable[vector] = type;\r
+//     Irq_VectorTable[vector] = isrPtr;\r
+\r
+\r
+       if (vector < INTC_NUMBER_OF_INTERRUPTS) {\r
+               Irq_SetPriority(Irq_Map[vector]->core ,vector + IRQ_INTERRUPT_OFFSET, osPrioToCpuPio(Irq_Map[vector]->priority));\r
+       } else if ((vector >= CRITICAL_INPUT_EXCEPTION)\r
+                       && (vector<= DEBUG_EXCEPTION)) {\r
+       } else {\r
+               /* Invalid vector! */\r
+               assert(0);\r
+       }\r
+\r
+\r
+       return;\r
+}\r
+#endif\r
 \r
+#if 0\r
 /**\r
  * Attach a ISR type 2 to the interrupt controller.\r
  *\r
@@ -281,9 +287,9 @@ void Irq_AttachIsr1( void (*entry)(void), void *int_ctrl, uint32_t vector,uint8_
  * @param vector\r
  */\r
 void Irq_AttachIsr2(TaskType tid,void *int_ctrl,IrqType vector ) {\r
-       OsPcbType *pcb;\r
+       OsTaskVarType *pcb;\r
 \r
-       pcb = os_find_task(tid);\r
+       pcb = Os_TaskGet(tid);\r
        Irq_VectorTable[vector] = (void *)pcb;\r
        Irq_IsrTypeTable[vector] = PROC_ISR2;\r
 \r
@@ -296,49 +302,9 @@ void Irq_AttachIsr2(TaskType tid,void *int_ctrl,IrqType vector ) {
                assert(0);\r
        }\r
 }\r
-\r
-#endif /* defined(USE_KERNEL) */\r
-\r
-#if !defined(USE_KERNEL)\r
-/**\r
- * Installs a vector in intc vector table. It also sets the priority in the INTC\r
- * internal registers.\r
- *\r
- * This does NOT use the kernel\r
- *\r
- * @param func   The function to install\r
- * @param vector INTC vector to install it to\r
- * @param priority INTC priority. 0 - Low prio. 15- Highest( NMI )\r
- * @param cpu\r
- */\r
-\r
-void Irq_InstallVector(void(*func)(), IrqType vector,\r
-    uint8_t priority, Cpu_t cpu)\r
-{\r
-  VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_INTCVECTORINSTALL_SERVICE_ID, MCU_E_UNINIT );\r
-  DEBUG(DEBUG_LOW,"Installing INTC vector:%d,prio:%d,cpu,%d\n",vector,priority,cpu);\r
-  Irq_VectorTable[vector] = func;\r
-\r
-  if (vector <= MLB_SERVICE_REQUEST)\r
-  {\r
-    INTC.PSR[vector].B.PRC_SEL = cpu;\r
-    INTC.PSR[vector].B.PRI = priority;\r
-\r
-    Irq_VectorTable[vector] = func;\r
-  } else if ((vector >= CRITICAL_INPUT_EXCEPTION)\r
-      && (vector <= DEBUG_EXCEPTION))\r
-  {\r
-    Irq_VectorTable[vector] = func;\r
-  } else\r
-  {\r
-    /* Invalid vector! */\r
-    assert(0);\r
-  }\r
-}\r
 #endif\r
 \r
 \r
-\r
 /**\r
  * Generates a soft interrupt\r
  * @param vector\r
@@ -385,7 +351,7 @@ void IVOR0Exception (uint32_t *regs)
 //     ExceptionSave(srr0,srr1,esr,mcsr,dear;)\r
        // CSRR0, CSSR1\r
        // Nothing more\r
-       dump_exception_regs(regs);\r
+       dumpExceptionRegs(regs);\r
        while (1);\r
 }\r
 \r
@@ -394,7 +360,7 @@ void IVOR1Exception (uint32_t *regs)
 {\r
        // CSRR0, CSSR1\r
        // MCSR - Source of machine check\r
-       dump_exception_regs(regs);\r
+       dumpExceptionRegs(regs);\r
    while (1);\r
 }\r
 // Data Storage Interrupt\r
@@ -402,7 +368,7 @@ void IVOR2Exception (uint32_t *regs)
 {\r
        // SRR0, SRR1\r
        // ESR - lots of stuff\r
-       dump_exception_regs(regs);\r
+       dumpExceptionRegs(regs);\r
    while (1);\r
 }\r
 \r
@@ -411,7 +377,7 @@ void IVOR3Exception (uint32_t *regs)
 {\r
        // SRR0, SRR1\r
        // ESR - lots of stuff\r
-       dump_exception_regs(regs);\r
+       dumpExceptionRegs(regs);\r
    while (1);\r
 }\r
 \r
@@ -421,7 +387,7 @@ void IVOR5Exception (uint32_t *regs)
        // SRR0, SRR1\r
        // ESR - lots of stuff\r
        // DEAR - Address of load store that caused the exception\r
-       dump_exception_regs(regs);\r
+       dumpExceptionRegs(regs);\r
    while (1);\r
 }\r
 \r
@@ -430,7 +396,7 @@ void IVOR6Exception (uint32_t *regs)
 {\r
        // SRR0, SRR1\r
        // ESR - lots of stuff\r
-       dump_exception_regs(regs);\r
+       dumpExceptionRegs(regs);\r
        while (1);\r
 }\r
 \r
@@ -438,7 +404,7 @@ void IVOR6Exception (uint32_t *regs)
 void IVOR7Exception (uint32_t *regs)\r
 {\r
        // SRR0, SRR1\r
-       dump_exception_regs(regs);\r
+       dumpExceptionRegs(regs);\r
    while (1);\r
 }\r
 \r
@@ -447,7 +413,7 @@ void IVOR8Exception (uint32_t *regs)
 {\r
        // SRR0, SRR1\r
        // ESR\r
-       dump_exception_regs(regs);\r
+       dumpExceptionRegs(regs);\r
        while (1);\r
 }\r
 \r
@@ -455,7 +421,7 @@ void IVOR8Exception (uint32_t *regs)
 void IVOR9Exception (uint32_t *regs)\r
 {\r
        // Does not happen on e200\r
-       dump_exception_regs(regs);\r
+       dumpExceptionRegs(regs);\r
        while (1);\r
 }\r
 #if 0\r
@@ -471,7 +437,7 @@ void IVOR10Exception (uint32_t *regs)
 void IVOR11Exception (uint32_t *regs)\r
 {\r
        // SRR0, SRR1\r
-       dump_exception_regs(regs);\r
+       dumpExceptionRegs(regs);\r
        while (1);\r
 }\r
 \r
@@ -479,7 +445,7 @@ void IVOR11Exception (uint32_t *regs)
 void IVOR12Exception (uint32_t *regs)\r
 {\r
        // SRR0, SRR1\r
-       dump_exception_regs(regs);\r
+       dumpExceptionRegs(regs);\r
        while (1);\r
 }\r
 \r
@@ -498,14 +464,14 @@ void IVOR14Exception (uint32_t *regs)
 {\r
        // SRR0, SRR1\r
        // ESR - MIF set, All others cleared\r
-       dump_exception_regs(regs);\r
+       dumpExceptionRegs(regs);\r
        while (1);\r
 }\r
 \r
 void IVOR15Exception (uint32_t *regs)\r
 {\r
        // Debug\r
-       dump_exception_regs(regs);\r
+       dumpExceptionRegs(regs);\r
        while (1);\r
 }\r
 \r
@@ -531,7 +497,7 @@ typedef struct {
 \r
 \r
 \r
-static void dump_exception_regs( uint32_t *regs ) {\r
+static void dumpExceptionRegs( uint32_t *regs ) {\r
        exc_stack_t *r = (exc_stack_t *)regs;\r
 \r
        LDEBUG_PRINTF("sp   %08x  srr0 %08x  srr1 %08x\n",r->sp,r->srr0,r->srr1);\r
@@ -542,107 +508,7 @@ static void dump_exception_regs( uint32_t *regs ) {
 }\r
 \r
 #else\r
-static void dump_exception_regs( uint32_t *regs ) {\r
+static void dumpExceptionRegs( uint32_t *regs ) {\r
 }\r
 #endif\r
 \r
-#if !defined(USE_KERNEL)\r
-func_t Irq_VectorTable[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS] __attribute__ ((aligned (0x800))) = {\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 00 - 04 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 05 - 09 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 10 - 14 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 15 - 19 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 20 - 24 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 25 - 29 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 30 - 34 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 35 - 39 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 40 - 44 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 45 - 49 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 50 - 54 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 55 - 59 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 60 - 64 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 55 - 69 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 70 - 74 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 75 - 79 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 80 - 84 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 85 - 89 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 90 - 94 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 95 - 99 */\r
-\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 100 - 104 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 105 - 109 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 110 - 114 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 115 - 119 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 120 - 124 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 125 - 129 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 130 - 134 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 135 - 139 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 140 - 144 */\r
- dummy, dummy, dummy, dummy, dummy /* PIT1 */, /* ISRs 145 - 149 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 150 - 154 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 155 - 159 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 160 - 164 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 155 - 169 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 170 - 174 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 175 - 179 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 180 - 184 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 185 - 189 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 190 - 194 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 195 - 199 */\r
-\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 200 - 204 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 205 - 209 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 210 - 214 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 215 - 219 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 220 - 224 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 225 - 229 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 230 - 234 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 235 - 239 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 240 - 244 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 245 - 249 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 250 - 254 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 255 - 259 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 260 - 264 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 255 - 269 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 270 - 274 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 275 - 279 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 280 - 284 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 285 - 289 */\r
- dummy, dummy, dummy, dummy,        /* ISRs 290 - 293 */\r
-\r
- /* Some reserved vectors between INC interrupts and exceptions. */\r
- dummy,                             /* INTC_NUMBER_OF_INTERRUPTS */\r
-\r
- dummy, dummy, dummy, dummy, dummy,\r
- dummy, dummy, dummy, dummy, dummy,\r
- dummy, dummy, dummy, dummy, dummy,\r
- dummy, dummy, dummy, dummy, dummy,\r
- dummy, dummy, dummy, dummy, dummy,\r
-\r
- IVOR0Exception,                    /* CRITICAL_INPUT_EXCEPTION, */\r
- IVOR1Exception,                    /* MACHINE_CHECK_EXCEPTION */\r
- IVOR2Exception,                    /* DATA_STORAGE_EXCEPTION */\r
- IVOR3Exception,                    /* INSTRUCTION_STORAGE_EXCEPTION */\r
- dummy,                             /* EXTERNAL_INTERRUPT */\r
-                                    /* This is the place where the "normal" interrupts will hit the CPU... */\r
- IVOR5Exception,                    /* ALIGNMENT_EXCEPTION */\r
- IVOR6Exception,                    /* PROGRAM_EXCEPTION */\r
- IVOR7Exception,                    /* FLOATING_POINT_EXCEPTION */\r
- IVOR8Exception,                    /* SYSTEM_CALL_EXCEPTION */\r
- dummy,                             /* AUX_EXCEPTION Not implemented in MPC5516. */\r
- dummy,                             /* DECREMENTER_EXCEPTION */\r
- IVOR11Exception,                   /* FIXED_INTERVAL_TIMER_EXCEPTION */\r
- IVOR12Exception,                   /* WATCHDOG_TIMER_EXCEPTION */\r
- IVOR13Exception,                   /* DATA_TLB_EXCEPTION */\r
- IVOR14Exception,                   /* INSTRUCTION_TLB_EXCEPTION */\r
- IVOR15Exception,                   /* DEBUG_EXCEPTION */\r
-};\r
-\r
-void dummy (void) {\r
-   while (1){\r
-          /* TODO: Rename and check for what spurious interrupt have happend */\r
-   };\r
- }\r
-\r
-#endif\r
-\r