-/* -------------------------------- Arctic Core ------------------------------
- * Arctic Core - the open source AUTOSAR platform http://arccore.com
- *
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
- *
- * This source code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- * -------------------------------- Arctic Core ------------------------------*/
-
-
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
#include "Std_Types.h"\r
#include "Mcu.h"\r
-#include "Det.h"
-#if defined(USE_DEM)
+#include "Det.h"\r
+#if defined(USE_DEM)\r
#include "Dem.h"\r
-#endif
+#endif\r
#include <assert.h>\r
-#include "cpu.h"\r
+#include "Cpu.h"\r
#include <string.h>\r
#include "Ramlog.h"\r
-#include "system_stm32f10x.h"
\r
-//#define USE_TRACE 1\r
//#define USE_LDEBUG_PRINTF 1\r
#include "debug.h"\r
-
-
-#ifndef ARRAY_SIZE
-#define ARRAY_SIZE(_x) (sizeof(_x)/sizeof((_x)[0]))
-#endif
-
-/* Development error macros. */
-#if ( MCU_DEV_ERROR_DETECT == STD_ON )
-#define VALIDATE(_exp,_api,_err ) \
- if( !(_exp) ) { \
- Det_ReportError(MODULE_ID_MCU,0,_api,_err); \
- return; \
- }
-
-#define VALIDATE_W_RV(_exp,_api,_err,_rv ) \
- if( !(_exp) ) { \
- Det_ReportError(MODULE_ID_MCU,0,_api,_err); \
- return (_rv); \
- }
-#else
-#define VALIDATE(_exp,_api,_err )
-#define VALIDATE_W_RV(_exp,_api,_err,_rv )
-#endif
-
-
-#define CORE_CPUID_CORTEX_M3 0x411FC231UL
-
-
+\r
+\r
+#ifndef ARRAY_SIZE\r
+#define ARRAY_SIZE(_x) (sizeof(_x)/sizeof((_x)[0]))\r
+#endif\r
+\r
+/* Development error macros. */\r
+#if ( MCU_DEV_ERROR_DETECT == STD_ON )\r
+#define VALIDATE(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_MCU,0,_api,_err); \\r
+ return; \\r
+ }\r
+\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_MCU,0,_api,_err); \\r
+ return (_rv); \\r
+ }\r
+#else\r
+#define VALIDATE(_exp,_api,_err )\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv )\r
+#endif\r
+\r
+\r
+#define CORE_CPUID_CORTEX_M3 0x411FC231UL\r
+\r
+\r
\r
typedef struct {\r
uint32 lossOfLockCnt;\r
char *name;\r
uint32 pvr;\r
} cpu_info_t;\r
-
-
-void Mcu_ConfigureFlash(void);
-
-
-
-/* Haven't found any ID accessable from memory.
- * There is the DBGMCU_IDCODE (0xe0042000) found in RM0041 but it
- * you can't read from that address..
- */
+\r
+\r
+void Mcu_ConfigureFlash(void);\r
+\r
+\r
+\r
+/* Haven't found any ID accessable from memory.\r
+ * There is the DBGMCU_IDCODE (0xe0042000) found in RM0041 but it\r
+ * you can't read from that address..\r
+ */\r
#if 0\r
cpu_info_t cpu_info_list[] = {\r
{\r
.pvr = 0,\r
},\r
};\r
-#endif
-
-/* The supported cores
+#endif\r
+\r
+/* The supported cores\r
*/\r
core_info_t core_info_list[] = {\r
{\r
\r
return NULL;\r
}\r
-#endif
-
+#endif\r
+\r
\r
static core_info_t *Mcu_IdentifyCore(uint32 pvr)\r
{\r
return NULL;\r
}\r
\r
-
-
-/**
- * Identify the core, just to check that we have support for it.
- *
- * @return
+/**\r
+ * Identify the core, just to check that we have support for it.\r
+ *\r
+ * @return\r
*/\r
static uint32 Mcu_CheckCpu( void ) {\r
\r
- uint32 pvr;\r
+ uint32 pvr = SCB->CPUID;\r
//uint32 pir;\r
//cpu_info_t *cpuType;\r
core_info_t *coreType;\r
\r
if( (coreType == NULL) ) {\r
// Just hang\r
- while(1);\r
- }
+ while(1) ;\r
+ }\r
\r
return 0;\r
}\r
\r
+static uint32_t GetPllValueFromMult(uint8_t pll)\r
+{\r
+ return (((uint32_t)pll - 2) << 18);\r
+}\r
+\r
+#ifdef STM32F10X_CL\r
+static uint32_t GetPll2ValueFromMult(uint8_t pll)\r
+{\r
+ return (((uint32_t)pll - 2) << 8);\r
+}\r
+#endif\r
+\r
+/**\r
+ * Set bus clocks. SysClk,AHBClk,APB1Clk,APB2Clk\r
+ */\r
+static void SetClocks(Mcu_ClockSettingConfigType *clockSettingsPtr)\r
+{\r
+ volatile uint32 StartUpCounter = 0, HSEStatus = 0;\r
+\r
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/\r
+ /* Enable HSE */\r
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+\r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+ StartUpCounter++;\r
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
+\r
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+ {\r
+ HSEStatus = (uint32_t)0x01;\r
+ }\r
+ else\r
+ {\r
+ HSEStatus = (uint32_t)0x00;\r
+ }\r
+\r
+ if (HSEStatus == (uint32_t)0x01)\r
+ {\r
+ /* Enable Prefetch Buffer */\r
+ FLASH->ACR |= FLASH_ACR_PRFTBE;\r
+\r
+ /* Flash 2 wait state */\r
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;\r
+\r
+\r
+ /* HCLK = SYSCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+\r
+ /* PCLK2 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+\r
+ /* PCLK1 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;\r
+\r
+#ifdef STM32F10X_CL\r
+ /* Configure PLLs ------------------------------------------------------*/\r
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */\r
+\r
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | GetPll2ValueFromMult(clockSettingsPtr->Pll2) |\r
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);\r
+\r
+ /* Enable PLL2 */\r
+ RCC->CR |= RCC_CR_PLL2ON;\r
+ /* Wait till PLL2 is ready */\r
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
+ {\r
+ }\r
+\r
+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */\r
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |\r
+ GetPllValueFromMult(clockSettingsPtr->Pll1));\r
+#else\r
+ /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |\r
+ RCC_CFGR_PLLMULL));\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | GetPllValueFromMult(clockSettingsPtr->Pll1));\r
+#endif /* STM32F10X_CL */\r
+\r
+ /* Enable PLL */\r
+ RCC->CR |= RCC_CR_PLLON;\r
+\r
+ /* Wait till PLL is ready */\r
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+ {\r
+ }\r
+\r
+ /* Select PLL as system clock source */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;\r
+\r
+ /* Wait till PLL is used as system clock source */\r
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+ {\r
+ }\r
+ }\r
+ else\r
+ { /* HSE fails to start-up, the application will have wrong clock */\r
+ NVIC_SystemReset();\r
+ }\r
+}\r
+\r
+/**\r
+ * Initialize Peripherals clocks\r
+ */\r
+static void InitPerClocks()\r
+{\r
+ RCC->AHBENR |= McuPerClockConfigData.AHBClocksEnable;\r
+ RCC->APB1ENR |= McuPerClockConfigData.APB1ClocksEnable;\r
+ RCC->APB2ENR |= McuPerClockConfigData.APB2ClocksEnable;\r
+}\r
+\r
+/**\r
+ * Initialize Flash, PLL and clocks.\r
+ */\r
+static void InitMcuClocks(Mcu_ClockSettingConfigType *clockSettingsPtr)\r
+{\r
+ /* Reset the RCC clock configuration to the default reset state(for debug purpose) */\r
+ /* Set HSION bit */\r
+ RCC->CR |= (uint32_t)0x00000001;\r
+\r
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */\r
+#ifndef STM32F10X_CL\r
+ RCC->CFGR &= (uint32_t)0xF8FF0000;\r
+#else\r
+ RCC->CFGR &= (uint32_t)0xF0FF0000;\r
+#endif /* STM32F10X_CL */\r
+\r
+ /* Reset HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xFEF6FFFF;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */\r
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;\r
+\r
+#ifndef STM32F10X_CL\r
+ /* Disable all interrupts and clear pending bits */\r
+ RCC->CIR = 0x009F0000;\r
+#else\r
+ /* Reset PLL2ON and PLL3ON bits */\r
+ RCC->CR &= (uint32_t)0xEBFFFFFF;\r
+\r
+ /* Disable all interrupts and clear pending bits */\r
+ RCC->CIR = 0x00FF0000;\r
+\r
+ /* Reset CFGR2 register */\r
+ RCC->CFGR2 = 0x00000000;\r
+#endif /* STM32F10X_CL */\r
+\r
+ /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */\r
+ /* Configure the Flash Latency cycles and enable prefetch buffer */\r
+ SetClocks(clockSettingsPtr);\r
+}\r
\r
//-------------------------------------------------------------------\r
\r
{\r
VALIDATE( ( NULL != configPtr ), MCU_INIT_SERVICE_ID, MCU_E_PARAM_CONFIG );\r
\r
- if( !SIMULATOR() ) {\r
- Mcu_CheckCpu();\r
- }\r
+#if !defined(USE_SIMULATOR)\r
+ Mcu_CheckCpu();\r
+#endif\r
\r
memset(&Mcu_Global.stats,0,sizeof(Mcu_Global.stats));\r
-
-
- SystemInit();\r
-
+\r
Irq_Enable();\r
\r
Mcu_Global.config = configPtr;\r
Mcu_Global.clockSetting = ClockSetting;\r
clockSettingsPtr = &Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting];\r
\r
+ InitMcuClocks(clockSettingsPtr);\r
+\r
+ InitPerClocks(clockSettingsPtr);\r
\r
return E_OK;\r
}\r
\r
//-------------------------------------------------------------------\r
\r
-
-Mcu_PllStatusType Mcu_GetPllStatus(void) {
- VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETPLLSTATUS_SERVICE_ID, MCU_E_UNINIT, MCU_PLL_STATUS_UNDEFINED );
- Mcu_PllStatusType rv;
-
- if (!SIMULATOR()) {
- if (RCC->CR & RCC_CR_PLLRDY) {
- rv = MCU_PLL_LOCKED;
- } else {
- rv = MCU_PLL_UNLOCKED;
- }
- } else {
- /* We are running on instruction set simulator. PLL is then always in sync... */
- rv = MCU_PLL_LOCKED;
- }
-
- return rv;
+\r
+Mcu_PllStatusType Mcu_GetPllStatus(void) {\r
+ VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETPLLSTATUS_SERVICE_ID, MCU_E_UNINIT, MCU_PLL_STATUS_UNDEFINED );\r
+ Mcu_PllStatusType rv;\r
+\r
+#if !defined(USE_SIMULATOR)\r
+ if (RCC->CR & RCC_CR_PLLRDY) {\r
+ rv = MCU_PLL_LOCKED;\r
+ } else {\r
+ rv = MCU_PLL_UNLOCKED;\r
+ }\r
+#else\r
+ /* We are running on instruction set simulator. PLL is then always in sync... */\r
+ rv = MCU_PLL_LOCKED;\r
+#endif\r
+ return rv;\r
}\r
\r
//-------------------------------------------------------------------\r
-
-/**
- *
- * @return
+\r
+/**\r
+ *\r
+ * @return\r
*/\r
-Mcu_ResetType Mcu_GetResetReason(void) {
- Mcu_ResetType rv;
- uint32_t csr;
-
- VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETRESETREASON_SERVICE_ID, MCU_E_UNINIT, MCU_RESET_UNDEFINED );
-
- csr = RCC->CSR;
-
- if (csr & RCC_CSR_SFTRSTF) {
- rv = MCU_SW_RESET;
- } else if (csr & (RCC_CSR_IWDGRSTF|RCC_CSR_WWDGRSTF) ) {
- rv = MCU_WATCHDOG_RESET;
- } else if ( csr & RCC_CSR_PORRSTF ) {
- rv = MCU_POWER_ON_RESET;
- } else {
- rv = MCU_RESET_UNDEFINED;
- }
-
- return rv;
+Mcu_ResetType Mcu_GetResetReason(void) {\r
+ Mcu_ResetType rv;\r
+ uint32_t csr;\r
+\r
+ VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETRESETREASON_SERVICE_ID, MCU_E_UNINIT, MCU_RESET_UNDEFINED );\r
+\r
+ csr = RCC->CSR;\r
+\r
+ if (csr & RCC_CSR_SFTRSTF) {\r
+ rv = MCU_SW_RESET;\r
+ } else if (csr & (RCC_CSR_IWDGRSTF|RCC_CSR_WWDGRSTF) ) {\r
+ rv = MCU_WATCHDOG_RESET;\r
+ } else if ( csr & RCC_CSR_PORRSTF ) {\r
+ rv = MCU_POWER_ON_RESET;\r
+ } else {\r
+ rv = MCU_RESET_UNDEFINED;\r
+ }\r
+\r
+ return rv;\r
}\r
\r
-//-------------------------------------------------------------------
+//-------------------------------------------------------------------\r
\r
-/**
- * Shall read the raw reset value from hardware register if the hardware
- * supports this.
- *
- * @return
+/**\r
+ * Shall read the raw reset value from hardware register if the hardware\r
+ * supports this.\r
+ *\r
+ * @return\r
*/\r
-
-Mcu_RawResetType Mcu_GetResetRawValue(void) {
- VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETRESETREASON_SERVICE_ID, MCU_E_UNINIT, MCU_GETRESETRAWVALUE_UNINIT_RV );
-
- if (!Mcu_Global.initRun) {
- return MCU_GETRESETRAWVALUE_UNINIT_RV;
- } else {
- return (RCC->CSR) & (RCC_CSR_RMVF | RCC_CSR_PINRSTF | RCC_CSR_PORRSTF
- | RCC_CSR_SFTRSTF | RCC_CSR_IWDGRSTF | RCC_CSR_WWDGRSTF
- | RCC_CSR_LPWRRSTF);
- }
- return 0;
+\r
+Mcu_RawResetType Mcu_GetResetRawValue(void) {\r
+ VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETRESETREASON_SERVICE_ID, MCU_E_UNINIT, MCU_GETRESETRAWVALUE_UNINIT_RV );\r
+\r
+ if (!Mcu_Global.initRun) {\r
+ return MCU_GETRESETRAWVALUE_UNINIT_RV;\r
+ } else {\r
+ return (RCC->CSR) & (RCC_CSR_RMVF | RCC_CSR_PINRSTF | RCC_CSR_PORRSTF\r
+ | RCC_CSR_SFTRSTF | RCC_CSR_IWDGRSTF | RCC_CSR_WWDGRSTF\r
+ | RCC_CSR_LPWRRSTF);\r
+ }\r
+ return 0;\r
}\r
\r
//-------------------------------------------------------------------\r
\r
-#if ( MCU_PERFORM_RESET_API == STD_ON )
-/**
- * Shell perform a microcontroller reset by using the hardware feature
- * of the micro controller.
+#if ( MCU_PERFORM_RESET_API == STD_ON )\r
+/**\r
+ * Shell perform a microcontroller reset by using the hardware feature\r
+ * of the micro controller.\r
*/\r
void Mcu_PerformReset(void)\r
{\r
\r
void Mcu_SetMode(const Mcu_ModeType McuMode)\r
{\r
- VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_SETMODE_SERVICE_ID, MCU_E_UNINIT );
+ VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_SETMODE_SERVICE_ID, MCU_E_UNINIT );\r
VALIDATE( (0), MCU_SETMODE_SERVICE_ID, MCU_E_PARAM_MODE );\r
//VALIDATE( ( McuMode <= Mcu_Global.config->McuNumberOfMcuModes ), MCU_SETMODE_SERVICE_ID, MCU_E_PARAM_MODE );\r
(void) McuMode;\r
\r
- /* NOT SUPPORTED */\r
}\r
\r
//-------------------------------------------------------------------\r
*/\r
uint32_t McuE_GetSystemClock(void)\r
{\r
- /*\r
- * System clock calculation\r
- *\r
- */
-
- // TODO: This of course wrong....\r
- uint32_t f_sys = 72000000UL;\r
-#if 0\r
- uint32 extal = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePointFrequency;\r
+ uint32_t f_sys;\r
\r
- f_sys = CALC_SYSTEM_CLOCK(extal,emfd,eprediv,erfd);\r
+ uint32 extal = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePointFrequency;\r
+ uint32 pll1 = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].Pll1;\r
+\r
+#ifdef STM32F10X_CL\r
+ uint32 pll2 = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].Pll2;\r
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * PLL2 */\r
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 */\r
+ /* PLL configuration: PLLCLK = PREDIV1 * PLL1 */\r
+ f_sys = (extal / 5 * pll2) / 5 * pll1;\r
+#else\r
+ /* PLL configuration: PLLCLK = HSE * PLL1 */\r
+ f_sys = extal * pll1;\r
#endif\r
\r
-// f_sys = extal * (emfd+16) / ( (eprediv+1) * ( erfd+1 ));\r
return f_sys;\r
}\r
\r
-imask_t McuE_EnterCriticalSection()\r
-{\r
-#if 0\r
- uint32_t msr = get_msr();\r
- Irq_Disable();\r
- return msr;\r
-#endif\r
- return 0;\r
-}\r
-\r
-void McuE_ExitCriticalSection(uint32_t old_state)\r
-{\r
-#if 0\r
- set_msr(old_state);\r
-#endif\r
-}\r
-\r
/**\r
* Get the peripheral clock in Hz for a specific device\r
*/\r
-\r
-#if 0\r
uint32_t McuE_GetPeripheralClock(McuE_PeriperalClock_t type)\r
{\r
-\r
- return 0;\r
+ uint32_t res = 0;\r
+\r
+ switch(type)\r
+ {\r
+ case PERIPHERAL_CLOCK_AHB:\r
+ res = McuE_GetSystemClock();\r
+ break;\r
+ case PERIPHERAL_CLOCK_APB1:\r
+ res = McuE_GetSystemClock() / 2;\r
+ break;\r
+ case PERIPHERAL_CLOCK_APB2:\r
+ res = McuE_GetSystemClock();\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return res;\r
}\r
-#endif\r
\r
\r
/**\r
{\r
\r
}\r
-\r
-void McuE_EnableInterrupts(void)\r
-{\r
- Irq_Enable();\r
-}\r
-\r
-void McuE_DisableInterrupts(void)\r
-{\r
- Irq_Disable();\r
-}\r
projects / arc.git / blobdiff