#define SCHM_MAINFUNCTION_CYCLE_PDUR SCHM_CYCLE_MAIN\r
#define SCHM_MAINFUNCTION_CYCLE_SPI SCHM_CYCLE_MAIN\r
#define SCHM_MAINFUNCTION_CYCLE_WDGM SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_WDGM_TRIGGER SCHM_CYCLE_MAIN\r
+#define SCHM_MAINFUNCTION_CYCLE_WDGM_ALIVESUPERVISION SCHM_CYCLE_MAIN\r
\r
/*\r
* Schedule BSW memory\r