arch/ppc/mpc55xx/kernel/irq_types.h

   1 /* -------------------------------- Arctic Core ------------------------------\r
   2  * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
   3  *\r
   4  * Copyright (C) 2009  ArcCore AB <contact@arccore.com>\r
   5  *\r
   6  * This source code is free software; you can redistribute it and/or modify it\r
   7  * under the terms of the GNU General Public License version 2 as published by the\r
   8  * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
   9  *\r
  10  * This program is distributed in the hope that it will be useful, but\r
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License\r
  13  * for more details.\r
  14  * -------------------------------- Arctic Core ------------------------------*/\r
  15 \r
  16 \r
  17 #ifndef IRQ_TYPES_H\r
  18 #define IRQ_TYPES_H\r
  19 \r
  20 \r
  21 #define Irq_SOI()\r
  22 \r
  23 /**\r
  24  * End-Of-Interrupt. Called by the OS it wants to clear the interrupt.\r
  25  */\r
  26 void Irq_EOI( void );\r
  27 \r
  28 \r
  29 typedef enum\r
  30 {\r
  31     /* Software interrupts. */\r
  32     INTC_SSCIR0_CLR0,           // 0\r
  33     INTC_SSCIR0_CLR1,           // 1\r
  34     INTC_SSCIR0_CLR2,           // 2\r
  35     INTC_SSCIR0_CLR3,           // 3\r
  36     INTC_SSCIR0_CLR4,           // 4\r
  37     INTC_SSCIR0_CLR5,           // 5\r
  38     INTC_SSCIR0_CLR6,           // 6\r
  39     INTC_SSCIR0_CLR7,           // 7\r
  40 #if defined(CFG_MPC560X)\r
  41     RESERVED0,              // 5606-8\r
  42 \r
  43     ECSM_INT,               // 5606-9\r
  44 \r
  45     DMA_COMBINED_ERROR_INT, // 5606-10\r
  46     DMA_CH0_INT,            // 5606-11\r
  47     DMA_CH1_INT,            // 5606-12\r
  48     DMA_CH2_INT,            // 5606-13\r
  49     DMA_CH3_INT,            // 5606-14\r
  50     DMA_CH4_INT,            // 5606-15\r
  51     DMA_CH5_INT,            // 5606-16\r
  52     DMA_CH6_INT,            // 5606-17\r
  53     DMA_CH7_INT,            // 5606-18\r
  54     DMA_CH8_INT,            // 5606-19\r
  55     DMA_CH9_INT,            // 5606-20\r
  56     DMA_CH10_INT,           // 5606-21\r
  57     DMA_CH11_INT,           // 5606-22\r
  58     DMA_CH12_INT,           // 5606-23\r
  59     DMA_CH13_INT,           // 5606-24\r
  60     DMA_CH14_INT,           // 5606-25\r
  61     DMA_CH15_INT,           // 5606-26\r
  62 \r
  63     RESERVED1,              // 5606-27\r
  64 \r
  65     SWT_TIMEOUT,            // 5606-28\r
  66 \r
  67     RESERVED2,              // 5606-29\r
  68 \r
  69     STM_CH0_INT,            // 5606-30\r
  70     STM_CH1_INT,            // 5606-31\r
  71     STM_CH2_INT,            // 5606-32\r
  72     STM_CH3_INT,            // 5606-33\r
  73 \r
  74     RESERVED3,              // 5606-34\r
  75 \r
  76     ECC_DBD_INT,            // 5606-35\r
  77     ECC_SBC_INT,            // 5606-36\r
  78 \r
  79     RESERVED4,              // 5606-37\r
  80 \r
  81     RTC_INT,                // 5606-38\r
  82     API_INT,                // 5606-39\r
  83 \r
  84     RESERVED5,              // 5606-40\r
  85 \r
  86     SIU_EXT_IRQ0,           // 5606-41\r
  87     SIU_EXT_IRQ1,           // 5606-42\r
  88 \r
  89     RESERVED6,              // 5606-43\r
  90     RESERVED7,              // 5606-44\r
  91     RESERVED8,              // 5606-45\r
  92 \r
  93     WAKEUP_IRQ0,            // 5606-46\r
  94     WAKEUP_IRQ1,            // 5606-47\r
  95     WAKEUP_IRQ2,            // 5606-48\r
  96 \r
  97     RESERVED9,              // 5606-49\r
  98     RESERVED10,             // 5606-50\r
  99 \r
 100     SAFE_MODE_INT,          // 5606-51\r
 101     MODE_TRAS_INT,          // 5606-52\r
 102     INV_MODE_INT,           // 5606-53\r
 103     INV_MODE_CONF_INT,      // 5606-54\r
 104 \r
 105     RESERVED11,             // 5606-55\r
 106 \r
 107     RESET_ALT_EVENT_INT,    // 5606-56\r
 108 \r
 109     FXOSC_COUNTER_EXPIRED,  // 5606-57\r
 110 \r
 111     RESERVED12,             // 5606-58\r
 112 \r
 113     PIT_INT0,               // 5606-59\r
 114     PIT_INT1,               // 5606-60\r
 115     PIT_INT2,               // 5606-61\r
 116 \r
 117     ADC_EOC_INT,            // 5606-62\r
 118     ADC_ER_INT,             // 5606-63\r
 119     ADC_WD_INT,             // 5606-64\r
 120 \r
 121     FLEXCAN_0_ESR_ERR_INT,  // 5606-65\r
 122     FLEXCAN_0_ESR_BOFF_INT, // 5606-66\r
 123 \r
 124     RESERVED13,             // 5606-67\r
 125 \r
 126     FLEXCAN_0_BUF_00_03,    // 5606-68\r
 127     FLEXCAN_0_BUF_04_07,    // 5606-69\r
 128     FLEXCAN_0_BUF_08_11,    // 5606-70\r
 129     FLEXCAN_0_BUF_12_15,    // 5606-71\r
 130     FLEXCAN_0_BUF_16_31,    // 5606-72\r
 131     FLEXCAN_0_BUF_32_63,    // 5606-73\r
 132 \r
 133     DSPI_0_ISR_TFUF_RFOF,   // 5606-74\r
 134     DSPI_0_ISR_EOQF,        // 5606-75\r
 135     DSPI_0_ISR_TFFF,        // 5606-76\r
 136     DSPI_0_ISR_TCF,         // 5606-77\r
 137     DSPI_0_ISR_RFDF,        // 5606-78\r
 138 \r
 139     LINFLEX_0_RXI,          // 5606-79\r
 140     LINFLEX_0_TXI,          // 5606-80\r
 141     LINFLEX_0_ERR,          // 5606-81\r
 142 \r
 143     RESERVED14,             // 5606-82\r
 144     RESERVED15,             // 5606-83\r
 145     RESERVED16,             // 5606-84\r
 146 \r
 147     FLEXCAN_1_ESR_ERR_INT,  // 5606-85\r
 148     FLEXCAN_1_ESR_BOFF_INT, // 5606-86\r
 149 \r
 150         RESERVED17,             // 5606-87\r
 151 \r
 152         FLEXCAN_1_BUF_00_03,    // 5606-88\r
 153         FLEXCAN_1_BUF_04_07,    // 5606-89\r
 154         FLEXCAN_1_BUF_08_11,    // 5606-90\r
 155         FLEXCAN_1_BUF_12_15,    // 5606-91\r
 156         FLEXCAN_1_BUF_16_31,    // 5606-92\r
 157         FLEXCAN_1_BUF_32_63,    // 5606-93\r
 158 \r
 159     DSPI_1_ISR_TFUF_RFOF,   // 5606-94\r
 160     DSPI_1_ISR_EOQF,        // 5606-95\r
 161     DSPI_1_ISR_TFFF,        // 5606-96\r
 162     DSPI_1_ISR_TCF,         // 5606-97\r
 163     DSPI_1_ISR_RFDF,        // 5606-98\r
 164 \r
 165     LINFLEX_1_RXI,          // 5606-99\r
 166     LINFLEX_1_TXI,          // 5606-100\r
 167     LINFLEX_1_ERR,          // 5606-101\r
 168 \r
 169     RESERVED18,             // 5606-102\r
 170     RESERVED19,             // 5606-103\r
 171     RESERVED20,             // 5606-104\r
 172     RESERVED21,             // 5606-105\r
 173     RESERVED22,             // 5606-106\r
 174         RESERVED23,             // 5606-107\r
 175         RESERVED24,             // 5606-108\r
 176         RESERVED25,             // 5606-109\r
 177         RESERVED26,             // 5606-110\r
 178         RESERVED27,             // 5606-111\r
 179         RESERVED28,             // 5606-112\r
 180         RESERVED29,             // 5606-113\r
 181         RESERVED30,             // 5606-114\r
 182         RESERVED31,             // 5606-115\r
 183         RESERVED32,             // 5606-116\r
 184         RESERVED33,             // 5606-117\r
 185         RESERVED34,             // 5606-118\r
 186         RESERVED35,             // 5606-119\r
 187         RESERVED36,             // 5606-120\r
 188         RESERVED37,             // 5606-121\r
 189         RESERVED38,             // 5606-122\r
 190         RESERVED39,             // 5606-123\r
 191         RESERVED40,             // 5606-124\r
 192 \r
 193     I2C_0_INT,              // 5606-125\r
 194     I2C_1_INT,              // 5606-126\r
 195 \r
 196     PIT_INT3,               // 5606-127\r
 197 \r
 198     RESERVED41,             // 5606-128\r
 199     RESERVED42,             // 5606-129\r
 200     RESERVED43,             // 5606-130\r
 201     RESERVED44,             // 5606-131\r
 202     RESERVED45,             // 5606-132\r
 203     RESERVED46,             // 5606-133\r
 204     RESERVED47,             // 5606-134\r
 205     RESERVED48,             // 5606-135\r
 206     RESERVED49,             // 5606-136\r
 207     RESERVED50,             // 5606-137\r
 208     RESERVED51,             // 5606-138\r
 209     RESERVED52,             // 5606-139\r
 210     RESERVED53,             // 5606-140\r
 211 #if defined (CFG_MPC5604B)\r
 212     EMIOS_0_GFR_F0_F1,      // 5606-141\r
 213     EMIOS_0_GFR_F2_F3,      // 5606-142\r
 214     EMIOS_0_GFR_F4_F5,      // 5606-143\r
 215     EMIOS_0_GFR_F6_F7,      // 5606-144\r
 216     EMIOS_0_GFR_F8_F9,      // 5606-145\r
 217     EMIOS_0_GFR_F10_F11,    // 5606-146\r
 218     EMIOS_0_GFR_F12_F13,    // 5606-147\r
 219     EMIOS_0_GFR_F14_F15,    // 5606-148\r
 220     EMIOS_0_GFR_F16_F17,    // 5606-149\r
 221     EMIOS_0_GFR_F18_F19,    // 5606-150\r
 222     EMIOS_0_GFR_F20_F21,    // 5606-151\r
 223     EMIOS_0_GFR_F22_F23,    // 5606-152\r
 224     EMIOS_0_GFR_F24_F25,    // 5606-153\r
 225     EMIOS_0_GFR_F26_F27,    // 5606-154\r
 226     RESERVED54,             // 5606-155\r
 227     RESERVED55,             // 5606-156\r
 228     EMIOS_1_GFR_F0_F1,      // 5606-157\r
 229     EMIOS_1_GFR_F2_F3,      // 5606-158\r
 230     EMIOS_1_GFR_F4_F5,      // 5606-159\r
 231     EMIOS_1_GFR_F6_F7,      // 5606-160\r
 232     EMIOS_1_GFR_F8_F9,      // 5606-161\r
 233     EMIOS_1_GFR_F10_F11,    // 5606-162\r
 234     EMIOS_1_GFR_F12_F13,    // 5606-163\r
 235     EMIOS_1_GFR_F14_F15,    // 5606-164\r
 236     EMIOS_1_GFR_F16_F17,    // 5606-165\r
 237     EMIOS_1_GFR_F18_F19,    // 5606-166\r
 238     EMIOS_1_GFR_F20_F21,    // 5606-167\r
 239     EMIOS_1_GFR_F22_F23,    // 5606-168\r
 240     EMIOS_1_GFR_F24_F25,    // 5606-169\r
 241     EMIOS_1_GFR_F26_F27,    // 5606-170\r
 242 \r
 243         RESERVED56,             // 5606-171\r
 244         RESERVED57,             // 5606-172\r
 245 \r
 246     FLEXCAN_3_ESR_ERR_INT,  // 5606-173\r
 247     FLEXCAN_3_ESR_BOFF_INT, // 5606-174\r
 248 \r
 249         RESERVED58,             // 5606-175\r
 250 \r
 251         FLEXCAN_3_BUF_00_03,    // 5606-176\r
 252         FLEXCAN_3_BUF_04_07,    // 5606-177\r
 253         FLEXCAN_3_BUF_08_11,    // 5606-178\r
 254         FLEXCAN_3_BUF_12_15,    // 5606-179\r
 255         FLEXCAN_3_BUF_16_31,    // 5606-180\r
 256         FLEXCAN_3_BUF_32_63,    // 5606-181\r
 257     RESERVED59,             // 5606-182\r
 258     RESERVED60,             // 5606-183\r
 259     RESERVED61,             // 5606-184\r
 260     RESERVED62,             // 5606-185\r
 261     RESERVED63,             // 5606-186\r
 262     RESERVED64,             // 5606-187\r
 263     RESERVED65,             // 5606-188\r
 264     RESERVED66,             // 5606-189\r
 265     FLEXCAN_4_ESR_ERR_INT,  // 5606-190\r
 266     FLEXCAN_4_ESR_BOFF_INT, // 5606-191\r
 267 \r
 268         RESERVED67,             // 5606-192\r
 269 \r
 270         FLEXCAN_4_BUF_00_03,    // 5606-193\r
 271         FLEXCAN_4_BUF_04_07,    // 5606-194\r
 272         FLEXCAN_4_BUF_08_11,    // 5606-195\r
 273         FLEXCAN_4_BUF_12_15,    // 5606-196\r
 274         FLEXCAN_4_BUF_16_31,    // 5606-197\r
 275         FLEXCAN_4_BUF_32_63,    // 5606-198\r
 276     RESERVED68,             // 5606-199\r
 277     RESERVED69,             // 5606-200\r
 278     RESERVED70,             // 5606-201\r
 279     FLEXCAN_5_ESR_ERR_INT,  // 5606-202\r
 280     FLEXCAN_5_ESR_BOFF_INT, // 5606-203\r
 281         RESERVED71,             // 5606-204\r
 282         FLEXCAN_5_BUF_00_03,    // 5606-205\r
 283         FLEXCAN_5_BUF_04_07,    // 5606-206\r
 284         FLEXCAN_5_BUF_08_11,    // 5606-207\r
 285         FLEXCAN_5_BUF_12_15,    // 5606-208\r
 286         FLEXCAN_5_BUF_16_31,    // 5606-209\r
 287         FLEXCAN_5_BUF_32_63,    // 5606-210\r
 288     RESERVED72,             // 5606-211\r
 289     RESERVED73,             // 5606-212\r
 290     RESERVED74,             // 5606-213\r
 291     RESERVED75,             // 5606-214\r
 292     RESERVED76,             // 5606-215\r
 293     RESERVED77,             // 5606-216\r
 294 #else if defined (CFG_MPC5606S)\r
 295     EMIOS_0_GFR_F8_F9,      // 5606-141\r
 296     EMIOS_0_GFR_F10_F11,    // 5606-142\r
 297     EMIOS_0_GFR_F12_F13,    // 5606-143\r
 298     EMIOS_0_GFR_F14_F15,    // 5606-144\r
 299     EMIOS_0_GFR_F16_F17,    // 5606-145\r
 300     EMIOS_0_GFR_F18_F19,    // 5606-146\r
 301     EMIOS_0_GFR_F20_F21,    // 5606-147\r
 302     EMIOS_0_GFR_F22_F23,    // 5606-148\r
 303 \r
 304     RESERVED54,             // 5606-149\r
 305     RESERVED55,             // 5606-150\r
 306     RESERVED56,             // 5606-151\r
 307     RESERVED57,             // 5606-152\r
 308     RESERVED58,             // 5606-153\r
 309     RESERVED59,             // 5606-154\r
 310     RESERVED60,             // 5606-155\r
 311     RESERVED61,             // 5606-156\r
 312 \r
 313     EMIOS_1_GFR_F16_F17,    // 5606-157\r
 314     EMIOS_1_GFR_F18_F19,    // 5606-158\r
 315     EMIOS_1_GFR_F20_F21,    // 5606-159\r
 316     EMIOS_1_GFR_F22_F23,    // 5606-160\r
 317 \r
 318     RESERVED62,             // 5606-161\r
 319     RESERVED63,             // 5606-162\r
 320     RESERVED64,             // 5606-163\r
 321     RESERVED65,             // 5606-164\r
 322     RESERVED66,             // 5606-165\r
 323     RESERVED67,             // 5606-166\r
 324     RESERVED68,             // 5606-167\r
 325     RESERVED69,             // 5606-168\r
 326     RESERVED70,             // 5606-169\r
 327     RESERVED71,             // 5606-170\r
 328     RESERVED72,             // 5606-171\r
 329     RESERVED73,             // 5606-172\r
 330 \r
 331     I2C_2_INT,              // 5606-173\r
 332     I2C_3_INT,              // 5606-174\r
 333 \r
 334         RESERVED74,             // 5606-175\r
 335         RESERVED75,             // 5606-176\r
 336         RESERVED76,             // 5606-177\r
 337         RESERVED77,             // 5606-178\r
 338         RESERVED78,             // 5606-179\r
 339         RESERVED79,             // 5606-180\r
 340         RESERVED80,             // 5606-181\r
 341         RESERVED81,             // 5606-182\r
 342 \r
 343         SDCI_INT,               // 5606-183\r
 344         DCUN0_VSYNC_INT,        // 5606-184\r
 345         DCUN0_UNDRUN,           // 5606-185\r
 346         DCUN0_PARERR,           // 5606-186\r
 347         DCUN0_PDI,              // 5606-187\r
 348 \r
 349         RESERVED82,             // 5606-188\r
 350         RESERVED83,             // 5606-189\r
 351         RESERVED84,             // 5606-190\r
 352         RESERVED85,             // 5606-191\r
 353 \r
 354         SMD0_INT,               // 5606-192\r
 355         SSD0_INT,               // 5606-193\r
 356         SSD1_INT,               // 5606-194\r
 357         SSD2_INT,               // 5606-195\r
 358         SSD3_INT,               // 5606-196\r
 359         SSD4_INT,               // 5606-197\r
 360         SSD5_INT,               // 5606-198\r
 361 \r
 362         LCD0_EOF_INT,           // 5606-199\r
 363 \r
 364         RESERVED86,             // 5606-200\r
 365 \r
 366         QSPI0_TFUF,             // 5606-201\r
 367         QSPI0_EOQF,             // 5606-202\r
 368         QSPI0_TFFF,             // 5606-203\r
 369         QSPI0_TCF,              // 5606-204\r
 370         QSPI0_RFDF,             // 5606-205\r
 371         QSPI0_IPAEF,            // 5606-206\r
 372 #endif\r
 373 \r
 374         INTC_NUMBER_OF_INTERRUPTS,\r
 375 #else\r
 376         MCM_MSWTIR_SWTIC,               // 8\r
 377         ECC_ERROR,                              // 9, some variant call it MCM_ESR_COMB\r
 378         /* eDMA */\r
 379         EDMA_ERRL_ERR31_0,          // 10\r
 380         EDMA_INTL_INT0,                 // 11\r
 381         EDMA_INTL_INT1,\r
 382         EDMA_INTL_INT2,\r
 383         EDMA_INTL_INT3,\r
 384         EDMA_INTL_INT4,\r
 385         EDMA_INTL_INT5,\r
 386         EDMA_INTL_INT6,\r
 387         EDMA_INTL_INT7,\r
 388         EDMA_INTL_INT8,\r
 389         EDMA_INTL_INT9,\r
 390         EDMA_INTL_INT10,\r
 391         EDMA_INTL_INT11,\r
 392         EDMA_INTL_INT12,\r
 393         EDMA_INTL_INT13,\r
 394         EDMA_INTL_INT14,\r
 395         EDMA_INTL_INT15,                // 26\r
 396 #if defined(CFG_MPC5554)||defined(CFG_MPC5567) ||defined(CFG_MPC5668)\r
 397         EDMA_INTL_INT16,\r
 398         EDMA_INTL_INT17,\r
 399         EDMA_INTL_INT18,\r
 400         EDMA_INTL_INT19,                // 30\r
 401         EDMA_INTL_INT20,\r
 402         EDMA_INTL_INT21,\r
 403         EDMA_INTL_INT22,\r
 404         EDMA_INTL_INT23,\r
 405         EDMA_INTL_INT24,\r
 406         EDMA_INTL_INT25,\r
 407         EDMA_INTL_INT26,\r
 408         EDMA_INTL_INT27,\r
 409         EDMA_INTL_INT28,\r
 410         EDMA_INTL_INT29,\r
 411         EDMA_INTL_INT30,\r
 412         EDMA_INTL_INT31,                // 42\r
 413 #else\r
 414         RESERVED0,\r
 415         RESERVED1,\r
 416         RESERVED2,\r
 417         RESERVED3,                              // 30\r
 418         RESERVED4,\r
 419         RESERVED5,\r
 420         RESERVED6,\r
 421         RESERVED7,\r
 422         RESERVED8,\r
 423         RESERVED9,\r
 424         RESERVED10,\r
 425         RESERVED11,\r
 426         RESERVED12,\r
 427         RESERVED13,\r
 428         RESERVED14,\r
 429         RESERVED15,                             // 42\r
 430 #endif\r
 431 \r
 432 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)\r
 433         /* Semahpore's */\r
 434         SEMAPHORE_INT0,                 // 43\r
 435         SEMAPHORE_INT1,\r
 436         PIN_WAKEUP,\r
 437         CRP_INTERRUPT,                  // API/RTC interrupt\r
 438         LVI_INTERRUPT,\r
 439         I2C_A,\r
 440         I2C_B,\r
 441 #endif\r
 442         PLL_SYNSR_LOCF,                 // 54-43,  16-50\r
 443         PLL_SYNSR_LOLF,                 // 54-44,  16-51\r
 444         SIU_OSR_OVER,\r
 445         /* External interrupts */\r
 446         SIU_EISR_EIF0,                  // 53\r
 447         SIU_EISR_EIF1,\r
 448         SIU_EISR_EIF2,\r
 449         SIU_EISR_EIF3,\r
 450         SIU_EISR_EIF15_4,               // 54-50, 57\r
 451 \r
 452         /* eMIOS */\r
 453         EMISOS200_FLAG_F0,              // 58\r
 454         EMISOS200_FLAG_F1,\r
 455         EMISOS200_FLAG_F2,\r
 456         EMISOS200_FLAG_F3,\r
 457         EMISOS200_FLAG_F4,\r
 458         EMISOS200_FLAG_F5,\r
 459         EMISOS200_FLAG_F6,\r
 460         EMISOS200_FLAG_F7,\r
 461         EMISOS200_FLAG_F8,\r
 462         EMISOS200_FLAG_F9,\r
 463         EMISOS200_FLAG_F10,\r
 464         EMISOS200_FLAG_F11,\r
 465         EMISOS200_FLAG_F12,\r
 466         EMISOS200_FLAG_F13,\r
 467         EMISOS200_FLAG_F14,\r
 468         EMISOS200_FLAG_F15,             // 73\r
 469 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)\r
 470         EMISOS200_FLAG_F16,\r
 471         EMISOS200_FLAG_F17,\r
 472         EMISOS200_FLAG_F18,\r
 473         EMISOS200_FLAG_F19,\r
 474         EMISOS200_FLAG_F20,\r
 475         EMISOS200_FLAG_F21,\r
 476         EMISOS200_FLAG_F22,\r
 477         EMISOS200_FLAG_F23,             // 16-81\r
 478 #elif defined(CFG_MPC5554)||defined(CFG_MPC5567)\r
 479         ETPU_GLOBAL,                    // 54-67\r
 480         ETPU_A_CIS_0,\r
 481         ETPU_A_CIS_1,\r
 482         ETPU_A_CIS_2,                   // 54-70\r
 483         ETPU_A_CIS_3,\r
 484         ETPU_A_CIS_4,\r
 485         ETPU_A_CIS_5,\r
 486         ETPU_A_CIS_6,\r
 487         ETPU_A_CIS_7,\r
 488         ETPU_A_CIS_8,\r
 489         ETPU_A_CIS_9,\r
 490         ETPU_A_CIS_10,\r
 491         ETPU_A_CIS_11,\r
 492         ETPU_A_CIS_12,                  // 54-80\r
 493         ETPU_A_CIS_13,\r
 494         ETPU_A_CIS_14,\r
 495         ETPU_A_CIS_15,\r
 496         ETPU_A_CIS_16,\r
 497         ETPU_A_CIS_17,\r
 498         ETPU_A_CIS_18,\r
 499         ETPU_A_CIS_19,\r
 500         ETPU_A_CIS_20,\r
 501         ETPU_A_CIS_21,\r
 502         ETPU_A_CIS_22,                  // 54-90\r
 503         ETPU_A_CIS_23,\r
 504         ETPU_A_CIS_24,\r
 505         ETPU_A_CIS_25,\r
 506         ETPU_A_CIS_26,\r
 507         ETPU_A_CIS_27,\r
 508         ETPU_A_CIS_28,\r
 509         ETPU_A_CIS_29,\r
 510         ETPU_A_CIS_30,\r
 511         ETPU_A_CIS_31,                  // 99\r
 512 #endif\r
 513 #if defined(CFG_MPC5668)\r
 514         ADC_A_EOC,                      // 82\r
 515         ADC_A_ERR,\r
 516         ADC_A_WD,\r
 517         ADC_B_EOC,\r
 518         ADC_B_ERR,\r
 519         ADC_B_WD,\r
 520         ADC_C_EOC,\r
 521         ADC_C_ERR,\r
 522         ADC_C_WD,\r
 523         RESERVED100,\r
 524         CRP_FLASH_READY,\r
 525         CTU_TRIGGER,\r
 526         RESERVED101,\r
 527         MLB_COMB_CH_0_15,\r
 528         MLB_SYSTEM_INT,\r
 529         MLB_CH_0,\r
 530         MLB_CH_1,\r
 531         MLB_CH_2,\r
 532         MLB_CH_3,\r
 533         MLB_CH_4,\r
 534         MLB_CH_5,\r
 535         MLB_CH_6,\r
 536         MLB_CH_7,\r
 537         MLB_CH_8,\r
 538         MLB_CH_9,\r
 539         MLB_CH_10,\r
 540         MLB_CH_11,\r
 541         MLB_CH_12,\r
 542         MLB_CH_13,\r
 543         MLB_CH_14,\r
 544         MLB_CH_15,              // 112\r
 545 #else\r
 546 \r
 547         /* eQADC */\r
 548         EQADC_FISR_OVER,                // 54-100, 16-82\r
 549         EQADC_FISR0_NCF0,\r
 550         EQADC_FISR0_PF0,\r
 551         EQADC_FISR0_EOQF0,\r
 552         EQADC_FISR0_CFFF0,\r
 553         EQADC_FISR0_RFDF0,\r
 554         EQADC_FISR1_NCF1,\r
 555         EQADC_FISR1_PF1,\r
 556         EQADC_FISR1_EOQF1,\r
 557         EQADC_FISR1_CFFF1,\r
 558         EQADC_FISR1_RFDF1,              // 110, 92\r
 559         EQADC_FISR2_NCF2,\r
 560         EQADC_FISR2_PF2,\r
 561         EQADC_FISR2_EOQF2,\r
 562         EQADC_FISR2_CFFF2,\r
 563         EQADC_FISR2_RFDF2,\r
 564         EQADC_FISR3_NCF3,\r
 565         EQADC_FISR3_PF3,\r
 566         EQADC_FISR3_EOQF3,\r
 567         EQADC_FISR3_CFFF3,\r
 568         EQADC_FISR3_RFDF3,              // 120, 102\r
 569         EQADC_FISR4_NCF4,\r
 570         EQADC_FISR4_PF4,\r
 571         EQADC_FISR4_EOQF4,\r
 572         EQADC_FISR4_CFFF4,\r
 573         EQADC_FISR4_RFDF4,\r
 574         EQADC_FISR5_NCF5,\r
 575         EQADC_FISR5_PF5,\r
 576         EQADC_FISR5_EOQF5,\r
 577         EQADC_FISR5_CFFF5,\r
 578         EQADC_FISR5_RFDF5,              // 130, 112\r
 579 #endif\r
 580 \r
 581 #if defined(CFG_MPC5516)\r
 582         /* SCI */\r
 583         SCI_A_COMB,                             // 16-113\r
 584         SCI_B_COMB,\r
 585         SCI_C_COMB,\r
 586         SCI_D_COMB,\r
 587         /* DSPI A,B */\r
 588         DSPI_A_ISR_OVER,\r
 589         DSPI_A_ISR_EOQF,\r
 590         DSPI_A_ISR_TFFF,\r
 591         DSPI_A_ISR_TCF,\r
 592         DSPI_A_ISR_RFDF,\r
 593         DSPI_B_ISR_OVER,                // 16-122\r
 594         DSPI_B_ISR_EOQF,\r
 595         DSPI_B_ISR_TFFF,\r
 596         DSPI_B_ISR_TCF,\r
 597         DSPI_B_ISR_RFDF,\r
 598 #elif defined(CFG_MPC5554)||defined(CFG_MPC5567)\r
 599         DSPI_B_COMB,                    // 54-131\r
 600         DSPI_B_ISR_EOQF,\r
 601         DSPI_B_ISR_TFFF,\r
 602         DSPI_B_ISR_TCF,\r
 603         DSPI_B_ISR_RFDF,                // 54-135\r
 604         DSPI_C_COMB,\r
 605         DSPI_C_ISR_EOQF,\r
 606         DSPI_C_ISR_TFFF,\r
 607         DSPI_C_ISR_TCF,\r
 608         DSPI_C_ISR_RFDF,                // 54-140\r
 609         DSPI_D_COMB,\r
 610         DSPI_D_ISR_EOQF,\r
 611         DSPI_D_ISR_TFFF,\r
 612         DSPI_D_ISR_TCF,\r
 613         DSPI_D_ISR_RFDF,                // 54-145\r
 614 \r
 615         ESCI_A_COMB0,\r
 616         RESERVED0,\r
 617         RESERVED1,\r
 618         ESCI_A_COMB1,\r
 619         RESERVED2,\r
 620         RESERVED3,                              // 54-151\r
 621 #endif\r
 622 \r
 623         /* FlexCAN A */\r
 624 #if defined(CFG_MPC5516) || defined(CFG_MPC5554)||defined(CFG_MPC5567) || defined(CFG_MPC5668)\r
 625         FLEXCAN_A_ESR_BOFF_INT, // 54-152, 16-127\r
 626         FLEXCAN_A_ESR_ERR_INT,\r
 627         RESERVED18,\r
 628         FLEXCAN_A_IFLAG1_BUF0I,\r
 629         FLEXCAN_A_IFLAG1_BUF1I,\r
 630         FLEXCAN_A_IFLAG1_BUF2I,\r
 631         FLEXCAN_A_IFLAG1_BUF3I,\r
 632         FLEXCAN_A_IFLAG1_BUF4I,\r
 633         FLEXCAN_A_IFLAG1_BUF5I,\r
 634         FLEXCAN_A_IFLAG1_BUF6I,\r
 635         FLEXCAN_A_IFLAG1_BUF7I,\r
 636         FLEXCAN_A_IFLAG1_BUF8I,\r
 637         FLEXCAN_A_IFLAG1_BUF9I,\r
 638         FLEXCAN_A_IFLAG1_BUF10I,\r
 639         FLEXCAN_A_IFLAG1_BUF11I,\r
 640         FLEXCAN_A_IFLAG1_BUF12I,\r
 641         FLEXCAN_A_IFLAG1_BUF13I,\r
 642         FLEXCAN_A_IFLAG1_BUF14I,\r
 643         FLEXCAN_A_IFLAG1_BUF15I,\r
 644         FLEXCAN_A_IFLAG1_BUF31_16I,\r
 645         FLEXCAN_A_IFLAG1_BUF63_32I,  // 16 - 147\r
 646 #endif\r
 647 \r
 648 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)\r
 649         /* Periodic interrupt timer */\r
 650         PIT_PITFLG_RTIF,        // 16 - 148\r
 651         PIT_PITFLG_PIT1,\r
 652         PIT_PITFLG_PIT2,\r
 653         PIT_PITFLG_PIT3,\r
 654         PIT_PITFLG_PIT4,\r
 655         PIT_PITFLG_PIT5,\r
 656         PIT_PITFLG_PIT6,\r
 657         PIT_PITFLG_PIT7,\r
 658         PIT_PITFLG_PIT8,\r
 659 \r
 660         /* FlexCAN B */\r
 661         FLEXCAN_B_ESR_BOFF_INT,\r
 662         FLEXCAN_B_ESR_ERR_INT,\r
 663         RESERVED19,\r
 664         FLEXCAN_B_IFLAG1_BUF0I,\r
 665         FLEXCAN_B_IFLAG1_BUF1I,\r
 666         FLEXCAN_B_IFLAG1_BUF2I,\r
 667         FLEXCAN_B_IFLAG1_BUF3I,\r
 668         FLEXCAN_B_IFLAG1_BUF4I,\r
 669         FLEXCAN_B_IFLAG1_BUF5I,\r
 670         FLEXCAN_B_IFLAG1_BUF6I,\r
 671         FLEXCAN_B_IFLAG1_BUF7I,\r
 672         FLEXCAN_B_IFLAG1_BUF8I,\r
 673         FLEXCAN_B_IFLAG1_BUF9I,\r
 674         FLEXCAN_B_IFLAG1_BUF10I,\r
 675         FLEXCAN_B_IFLAG1_BUF11I,\r
 676         FLEXCAN_B_IFLAG1_BUF12I,\r
 677         FLEXCAN_B_IFLAG1_BUF13I,\r
 678         FLEXCAN_B_IFLAG1_BUF14I,\r
 679         FLEXCAN_B_IFLAG1_BUF15I,\r
 680         FLEXCAN_B_IFLAG1_BUF31_16I,\r
 681         FLEXCAN_B_IFLAG1_BUF63_32I,\r
 682         /* FlexCAN C */\r
 683         FLEXCAN_C_ESR_BOFF_INT,\r
 684         FLEXCAN_C_ESR_ERR_INT,\r
 685         RESERVED20,\r
 686         FLEXCAN_C_IFLAG1_BUF0I,\r
 687         FLEXCAN_C_IFLAG1_BUF1I,\r
 688         FLEXCAN_C_IFLAG1_BUF2I,\r
 689         FLEXCAN_C_IFLAG1_BUF3I,\r
 690         FLEXCAN_C_IFLAG1_BUF4I,\r
 691         FLEXCAN_C_IFLAG1_BUF5I,\r
 692         FLEXCAN_C_IFLAG1_BUF6I,\r
 693         FLEXCAN_C_IFLAG1_BUF7I,\r
 694         FLEXCAN_C_IFLAG1_BUF8I,\r
 695         FLEXCAN_C_IFLAG1_BUF9I,\r
 696         FLEXCAN_C_IFLAG1_BUF10I,\r
 697         FLEXCAN_C_IFLAG1_BUF11I,\r
 698         FLEXCAN_C_IFLAG1_BUF12I,\r
 699         FLEXCAN_C_IFLAG1_BUF13I,\r
 700         FLEXCAN_C_IFLAG1_BUF14I,\r
 701         FLEXCAN_C_IFLAG1_BUF15I,\r
 702         FLEXCAN_C_IFLAG1_BUF31_16I,\r
 703         FLEXCAN_C_IFLAG1_BUF63_32I,\r
 704         /* FlexCAN D */\r
 705         FLEXCAN_D_ESR_BOFF_INT,\r
 706         FLEXCAN_D_ESR_ERR_INT,\r
 707         RESERVED21,\r
 708         FLEXCAN_D_IFLAG1_BUF0I,\r
 709         FLEXCAN_D_IFLAG1_BUF1I,\r
 710         FLEXCAN_D_IFLAG1_BUF2I,\r
 711         FLEXCAN_D_IFLAG1_BUF3I,\r
 712         FLEXCAN_D_IFLAG1_BUF4I,\r
 713         FLEXCAN_D_IFLAG1_BUF5I,\r
 714         FLEXCAN_D_IFLAG1_BUF6I,\r
 715         FLEXCAN_D_IFLAG1_BUF7I,\r
 716         FLEXCAN_D_IFLAG1_BUF8I,\r
 717         FLEXCAN_D_IFLAG1_BUF9I,\r
 718         FLEXCAN_D_IFLAG1_BUF10I,\r
 719         FLEXCAN_D_IFLAG1_BUF11I,\r
 720         FLEXCAN_D_IFLAG1_BUF12I,\r
 721         FLEXCAN_D_IFLAG1_BUF13I,\r
 722         FLEXCAN_D_IFLAG1_BUF14I,\r
 723         FLEXCAN_D_IFLAG1_BUF15I,\r
 724         FLEXCAN_D_IFLAG1_BUF31_16I,\r
 725         FLEXCAN_D_IFLAG1_BUF63_32I,\r
 726         /* FlexCAN E */\r
 727         FLEXCAN_E_ESR_BOFF_INT,\r
 728         FLEXCAN_E_ESR_ERR_INT,\r
 729         RESERVED22,\r
 730         FLEXCAN_E_IFLAG1_BUF0I,\r
 731         FLEXCAN_E_IFLAG1_BUF1I,\r
 732         FLEXCAN_E_IFLAG1_BUF2I,\r
 733         FLEXCAN_E_IFLAG1_BUF3I,\r
 734         FLEXCAN_E_IFLAG1_BUF4I,\r
 735         FLEXCAN_E_IFLAG1_BUF5I,\r
 736         FLEXCAN_E_IFLAG1_BUF6I,\r
 737         FLEXCAN_E_IFLAG1_BUF7I,\r
 738         FLEXCAN_E_IFLAG1_BUF8I,\r
 739         FLEXCAN_E_IFLAG1_BUF9I,\r
 740         FLEXCAN_E_IFLAG1_BUF10I,\r
 741         FLEXCAN_E_IFLAG1_BUF11I,\r
 742         FLEXCAN_E_IFLAG1_BUF12I,\r
 743         FLEXCAN_E_IFLAG1_BUF13I,\r
 744         FLEXCAN_E_IFLAG1_BUF14I,\r
 745         FLEXCAN_E_IFLAG1_BUF15I,\r
 746         FLEXCAN_E_IFLAG1_BUF31_16I,\r
 747         FLEXCAN_E_IFLAG1_BUF63_32I,\r
 748         /* FlexCAN F */\r
 749         FLEXCAN_F_ESR_BOFF_INT,\r
 750         FLEXCAN_F_ESR_ERR_INT,\r
 751         RESERVED23,\r
 752         FLEXCAN_F_IFLAG1_BUF0I,\r
 753         FLEXCAN_F_IFLAG1_BUF1I,\r
 754         FLEXCAN_F_IFLAG1_BUF2I,\r
 755         FLEXCAN_F_IFLAG1_BUF3I,\r
 756         FLEXCAN_F_IFLAG1_BUF4I,\r
 757         FLEXCAN_F_IFLAG1_BUF5I,\r
 758         FLEXCAN_F_IFLAG1_BUF6I,\r
 759         FLEXCAN_F_IFLAG1_BUF7I,\r
 760         FLEXCAN_F_IFLAG1_BUF8I,\r
 761         FLEXCAN_F_IFLAG1_BUF9I,\r
 762         FLEXCAN_F_IFLAG1_BUF10I,\r
 763         FLEXCAN_F_IFLAG1_BUF11I,\r
 764         FLEXCAN_F_IFLAG1_BUF12I,\r
 765         FLEXCAN_F_IFLAG1_BUF13I,\r
 766         FLEXCAN_F_IFLAG1_BUF14I,\r
 767         FLEXCAN_F_IFLAG1_BUF15I,\r
 768         FLEXCAN_F_IFLAG1_BUF31_16I,\r
 769         FLEXCAN_F_IFLAG1_BUF63_32I,\r
 770 #if defined(CFG_MPC5668)\r
 771         EMIOS200_FLAG_F24,\r
 772         EMIOS200_FLAG_F25,\r
 773         EMIOS200_FLAG_F26,\r
 774         EMIOS200_FLAG_F27,\r
 775         EMIOS200_FLAG_F28,\r
 776         EMIOS200_FLAG_F29,\r
 777         EMIOS200_FLAG_F30,\r
 778         EMIOS200_FLAG_F31,\r
 779 #else\r
 780         RESERVED24,\r
 781         RESERVED25,\r
 782         RESERVED26,\r
 783         RESERVED27,\r
 784         RESERVED28,\r
 785         RESERVED29,\r
 786         RESERVED30,\r
 787         RESERVED31,\r
 788 #endif\r
 789         /* SCI */\r
 790         SCI_E_COMB,             // 68-270\r
 791         SCI_F_COMB,\r
 792         SCI_G_COMB,\r
 793         SCI_H_COMB,\r
 794         /* DSPI */\r
 795         DSPI_C_ISR_OVER,\r
 796         DSPI_C_ISR_EOQF,\r
 797         DSPI_C_ISR_TFFF,\r
 798         DSPI_C_ISR_TCF,\r
 799         DSPI_C_ISR_RFDF,\r
 800         DSPI_D_ISR_OVER,\r
 801         DSPI_D_ISR_EOQF,\r
 802         DSPI_D_ISR_TFFF,\r
 803         DSPI_D_ISR_TCF,\r
 804         DSPI_D_ISR_RFDF,\r
 805         /* Flexray */\r
 806         FLEXRAY_GLOB,\r
 807         FLEXRAY_PRIF,\r
 808         FLEXRAY_CHIF,\r
 809         FLEXRAY_WUP_IF,\r
 810         FLEXRAY_FBNE_F,\r
 811         FLEXRAY_FANE_F,\r
 812         FLEXRAY_RBIF,\r
 813         FLEXRAY_TBIF,\r
 814         RESERVED32,\r
 815         MLB_SERVICE_REQUEST,\r
 816 #if defined(MPC5668)\r
 817         STM_CH0,\r
 818         STM_CH1,\r
 819         STM_CH2,\r
 820         STM_CH3,\r
 821         FEC_TX,\r
 822         FEC_RX,\r
 823         FEC_WORLD,\r
 824         RESERVED201,\r
 825         RESERVED202,\r
 826         RESERVED203,\r
 827         RESERVED204,\r
 828         RESERVED205,\r
 829         SCI_J_COMB,\r
 830         SCI_K_COMB,\r
 831         SCI_L_COMB,\r
 832         SCI_M_COMB,\r
 833         SCI_N_COMB,\r
 834         SCI_P_COMB,\r
 835         SCI_Q_COMB,\r
 836         SCI_R_COMB,\r
 837         I2C_C,\r
 838         I2C_D,\r
 839 #endif\r
 840         INTC_NUMBER_OF_INTERRUPTS,\r
 841         /* End of INTC interrupts. The vectors below are used to handle exceptions. */\r
 842         RESERVED_SPACE_BEFORE_EXCEPTIONS1,\r
 843         RESERVED_SPACE_BEFORE_EXCEPTIONS2,\r
 844         RESERVED_SPACE_BEFORE_EXCEPTIONS3,\r
 845         RESERVED_SPACE_BEFORE_EXCEPTIONS4,\r
 846         RESERVED_SPACE_BEFORE_EXCEPTIONS5,\r
 847         RESERVED_SPACE_BEFORE_EXCEPTIONS6,\r
 848         RESERVED_SPACE_BEFORE_EXCEPTIONS7,\r
 849         RESERVED_SPACE_BEFORE_EXCEPTIONS8,\r
 850         RESERVED_SPACE_BEFORE_EXCEPTIONS9,\r
 851         RESERVED_SPACE_BEFORE_EXCEPTIONS10,\r
 852         RESERVED_SPACE_BEFORE_EXCEPTIONS11,\r
 853         RESERVED_SPACE_BEFORE_EXCEPTIONS12,\r
 854         RESERVED_SPACE_BEFORE_EXCEPTIONS13,\r
 855         RESERVED_SPACE_BEFORE_EXCEPTIONS14,\r
 856         RESERVED_SPACE_BEFORE_EXCEPTIONS15,\r
 857         RESERVED_SPACE_BEFORE_EXCEPTIONS16,\r
 858         RESERVED_SPACE_BEFORE_EXCEPTIONS17,\r
 859         RESERVED_SPACE_BEFORE_EXCEPTIONS18,\r
 860         RESERVED_SPACE_BEFORE_EXCEPTIONS19,\r
 861         RESERVED_SPACE_BEFORE_EXCEPTIONS20,\r
 862         RESERVED_SPACE_BEFORE_EXCEPTIONS21,\r
 863         RESERVED_SPACE_BEFORE_EXCEPTIONS22,\r
 864         RESERVED_SPACE_BEFORE_EXCEPTIONS23,\r
 865         RESERVED_SPACE_BEFORE_EXCEPTIONS24,\r
 866         RESERVED_SPACE_BEFORE_EXCEPTIONS25,\r
 867 #endif\r
 868 \r
 869 #if defined(CFG_MPC5554)||defined(CFG_MPC5567)\r
 870         /* FlexCAN C */\r
 871         FLEXCAN_C_ESR_BOFF_INT = 173,\r
 872         FLEXCAN_C_ESR_ERR_INT,\r
 873         RESERVED20,\r
 874         FLEXCAN_C_IFLAG1_BUF0I,\r
 875         FLEXCAN_C_IFLAG1_BUF1I,\r
 876         FLEXCAN_C_IFLAG1_BUF2I,\r
 877         FLEXCAN_C_IFLAG1_BUF3I,\r
 878         FLEXCAN_C_IFLAG1_BUF4I,\r
 879         FLEXCAN_C_IFLAG1_BUF5I,\r
 880         FLEXCAN_C_IFLAG1_BUF6I,\r
 881         FLEXCAN_C_IFLAG1_BUF7I,\r
 882         FLEXCAN_C_IFLAG1_BUF8I,\r
 883         FLEXCAN_C_IFLAG1_BUF9I,\r
 884         FLEXCAN_C_IFLAG1_BUF10I,\r
 885         FLEXCAN_C_IFLAG1_BUF11I,\r
 886         FLEXCAN_C_IFLAG1_BUF12I,\r
 887         FLEXCAN_C_IFLAG1_BUF13I,\r
 888         FLEXCAN_C_IFLAG1_BUF14I,\r
 889         FLEXCAN_C_IFLAG1_BUF15I,\r
 890         FLEXCAN_C_IFLAG1_BUF31_16I,\r
 891         FLEXCAN_C_IFLAG1_BUF63_32I,\r
 892 \r
 893         // ....\r
 894 \r
 895         // 275\r
 896         DSPI_A_COMB = 275,              // 54-131\r
 897         DSPI_A_ISR_EOQF,\r
 898         DSPI_A_ISR_TFFF,\r
 899         DSPI_A_ISR_TCF,\r
 900         DSPI_A_ISR_RFDF,        // 54-135\r
 901 \r
 902         /* FlexCAN B */\r
 903         FLEXCAN_B_ESR_BOFF_INT = 280,\r
 904         FLEXCAN_B_ESR_ERR_INT,\r
 905         RESERVED21,\r
 906         FLEXCAN_B_IFLAG1_BUF0I,\r
 907         FLEXCAN_B_IFLAG1_BUF1I,\r
 908         FLEXCAN_B_IFLAG1_BUF2I,\r
 909         FLEXCAN_B_IFLAG1_BUF3I,\r
 910         FLEXCAN_B_IFLAG1_BUF4I,\r
 911         FLEXCAN_B_IFLAG1_BUF5I,\r
 912         FLEXCAN_B_IFLAG1_BUF6I,\r
 913         FLEXCAN_B_IFLAG1_BUF7I,\r
 914         FLEXCAN_B_IFLAG1_BUF8I,\r
 915         FLEXCAN_B_IFLAG1_BUF9I,\r
 916         FLEXCAN_B_IFLAG1_BUF10I,\r
 917         FLEXCAN_B_IFLAG1_BUF11I,\r
 918         FLEXCAN_B_IFLAG1_BUF12I,\r
 919         FLEXCAN_B_IFLAG1_BUF13I,\r
 920         FLEXCAN_B_IFLAG1_BUF14I,\r
 921         FLEXCAN_B_IFLAG1_BUF15I,\r
 922         FLEXCAN_B_IFLAG1_BUF31_16I,\r
 923         FLEXCAN_B_IFLAG1_BUF63_32I,\r
 924 \r
 925         /* FlexCAN D */\r
 926         FLEXCAN_D_ESR_BOFF_INT = 308,\r
 927         FLEXCAN_D_ESR_ERR_INT,\r
 928         RESERVED22,\r
 929         FLEXCAN_D_IFLAG1_BUF0I,\r
 930         FLEXCAN_D_IFLAG1_BUF1I,\r
 931         FLEXCAN_D_IFLAG1_BUF2I,\r
 932         FLEXCAN_D_IFLAG1_BUF3I,\r
 933         FLEXCAN_D_IFLAG1_BUF4I,\r
 934         FLEXCAN_D_IFLAG1_BUF5I,\r
 935         FLEXCAN_D_IFLAG1_BUF6I,\r
 936         FLEXCAN_D_IFLAG1_BUF7I,\r
 937         FLEXCAN_D_IFLAG1_BUF8I,\r
 938         FLEXCAN_D_IFLAG1_BUF9I,\r
 939         FLEXCAN_D_IFLAG1_BUF10I,\r
 940         FLEXCAN_D_IFLAG1_BUF11I,\r
 941         FLEXCAN_D_IFLAG1_BUF12I,\r
 942         FLEXCAN_D_IFLAG1_BUF13I,\r
 943         FLEXCAN_D_IFLAG1_BUF14I,\r
 944         FLEXCAN_D_IFLAG1_BUF15I,\r
 945         FLEXCAN_D_IFLAG1_BUF31_16I,\r
 946         FLEXCAN_D_IFLAG1_BUF63_32I,\r
 947 \r
 948         /* FlexCAN E */\r
 949         FLEXCAN_E_ESR_BOFF_INT = 329,\r
 950         FLEXCAN_E_ESR_ERR_INT,\r
 951         RESERVED23,\r
 952         FLEXCAN_E_IFLAG1_BUF0I,\r
 953         FLEXCAN_E_IFLAG1_BUF1I,\r
 954         FLEXCAN_E_IFLAG1_BUF2I,\r
 955         FLEXCAN_E_IFLAG1_BUF3I,\r
 956         FLEXCAN_E_IFLAG1_BUF4I,\r
 957         FLEXCAN_E_IFLAG1_BUF5I,\r
 958         FLEXCAN_E_IFLAG1_BUF6I,\r
 959         FLEXCAN_E_IFLAG1_BUF7I,\r
 960         FLEXCAN_E_IFLAG1_BUF8I,\r
 961         FLEXCAN_E_IFLAG1_BUF9I,\r
 962         FLEXCAN_E_IFLAG1_BUF10I,\r
 963         FLEXCAN_E_IFLAG1_BUF11I,\r
 964         FLEXCAN_E_IFLAG1_BUF12I,\r
 965         FLEXCAN_E_IFLAG1_BUF13I,\r
 966         FLEXCAN_E_IFLAG1_BUF14I,\r
 967         FLEXCAN_E_IFLAG1_BUF15I,\r
 968         FLEXCAN_E_IFLAG1_BUF31_16I,\r
 969         FLEXCAN_E_IFLAG1_BUF63_32I,\r
 970 \r
 971         INTC_NUMBER_OF_INTERRUPTS,\r
 972 \r
 973         DUMMY_DUMMY = 319,\r
 974 \r
 975 #endif /* defined(CFG_MPC5554)||defined(CFG_MPC5567) */\r
 976 #endif\r
 977         CRITICAL_INPUT_EXCEPTION,\r
 978         MACHINE_CHECK_EXCEPTION,\r
 979         DATA_STORAGE_EXCEPTION,\r
 980         INSTRUCTION_STORAGE_EXCEPTION,\r
 981         EXTERNAL_INTERRUPT,                    /* This is the place where the "normal" interrupts will hit the CPU... */\r
 982         ALIGNMENT_EXCEPTION,\r
 983         PROGRAM_EXCEPTION,\r
 984         FLOATING_POINT_EXCEPTION,\r
 985         SYSTEM_CALL_EXCEPTION,\r
 986         AUX_EXCEPTION,\r
 987         DECREMENTER_EXCEPTION,\r
 988         FIXED_INTERVAL_TIMER_EXCEPTION,\r
 989         WATCHDOG_TIMER_EXCEPTION,\r
 990         DATA_TLB_EXCEPTION,\r
 991         INSTRUCTION_TLB_EXCEPTION,\r
 992         DEBUG_EXCEPTION,\r
 993         NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS\r
 994 \r
 995 }IrqType;\r
 996 \r
 997 typedef enum\r
 998 {\r
 999         PERIPHERAL_CLOCK_FLEXCAN_A,\r
1000         PERIPHERAL_CLOCK_FLEXCAN_B,\r
1001         PERIPHERAL_CLOCK_FLEXCAN_C,\r
1002         PERIPHERAL_CLOCK_FLEXCAN_D,\r
1003         PERIPHERAL_CLOCK_FLEXCAN_E,\r
1004         PERIPHERAL_CLOCK_FLEXCAN_F,\r
1005         PERIPHERAL_CLOCK_PIT,\r
1006         PERIPHERAL_CLOCK_DSPI_A,\r
1007         PERIPHERAL_CLOCK_DSPI_B,\r
1008         PERIPHERAL_CLOCK_DSPI_C,\r
1009         PERIPHERAL_CLOCK_DSPI_D,\r
1010 #if defined(CFG_MPC560X)\r
1011         PERIPHERAL_CLOCK_EMIOS_0,\r
1012         PERIPHERAL_CLOCK_EMIOS_1,\r
1013 #else\r
1014         PERIPHERAL_CLOCK_EMIOS,\r
1015 #endif\r
1016         PERIPHERAL_CLOCK_ESCI_A,\r
1017         PERIPHERAL_CLOCK_ESCI_B,\r
1018         PERIPHERAL_CLOCK_ESCI_C,\r
1019         PERIPHERAL_CLOCK_ESCI_D,\r
1020         PERIPHERAL_CLOCK_ESCI_E,\r
1021         PERIPHERAL_CLOCK_ESCI_F,\r
1022         PERIPHERAL_CLOCK_ESCI_G,\r
1023         PERIPHERAL_CLOCK_ESCI_H,\r
1024 #if defined(CFG_MPC560X)\r
1025         PERIPHERAL_CLOCK_LIN_A,\r
1026         PERIPHERAL_CLOCK_LIN_B,\r
1027         PERIPHERAL_CLOCK_LIN_C,\r
1028         PERIPHERAL_CLOCK_LIN_D,\r
1029 #endif\r
1030         PERIPHERAL_CLOCK_IIC_A,\r
1031         PERIPHERAL_CLOCK_IIC_B,\r
1032         PERIPHERAL_CLOCK_MLB,\r
1033         PERIPHERAL_CLOCK_ADC_A,\r
1034 } McuE_PeriperalClock_t;\r
1035 \r
1036 \r
1037 typedef enum\r
1038 {\r
1039         CPU_CORE0,\r
1040         CPU_CORE1\r
1041 } Cpu_t;\r
1042 \r
1043 /* Offset from exceptions to interrupts */\r
1044 #define IRQ_INTERRUPT_OFFSET            0\r
1045 \r
1046 #endif /* IRQ_H_ */\r