1 #/***********************************************************************/
2 #/* Startup file for LPC21xx MCU applications */
3 #/* Partially inspired by KEIL ELEKTRONIK startup code */
4 #/***********************************************************************/
7 # *** Startup Code (executed after Reset) ***
9 # Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
10 .set MODE_USR, 0x10 // User Mode
11 .set MODE_FIQ, 0x11 // FIQ Mode
12 .set MODE_IRQ, 0x12 // IRQ Mode
13 .set MODE_SVC, 0x13 // Supervisor Mode
14 .set MODE_ABT, 0x17 // Abort Mode
15 .set MODE_UND, 0x1B // Undefined Mode
16 .set MODE_SYS, 0x1F // System Mode
18 .equ I_BIT, 0x80 // when I bit is set, IRQ is disabled
19 .equ F_BIT, 0x40 // when F bit is set, FIQ is disabled
21 .set UND_STACK_SIZE, 0x00000004
22 .set ABT_STACK_SIZE, 0x00000004
23 .set FIQ_STACK_SIZE, 0x00000004
24 .set IRQ_STACK_SIZE, 0X00000400
25 .set SVC_STACK_SIZE, 0x00000004
27 # Starupt Code must be linked first at Address at which it expects to run.
32 .global _stack // top of stack
40 # Memory Mapping (when Interrupt Vectors are in RAM)
41 .equ MEMMAP, 0xE01FC040 /* Memory Mapping Control */
52 # Initialize Interrupt System
53 # - Set stack location for each mode
54 # - Leave in System Mode with Interrupts Disabled
55 # -----------------------------------------------
57 msr CPSR_c,#MODE_UND|I_BIT|F_BIT // Undefined Instruction Mode
59 sub r0,r0,#UND_STACK_SIZE
60 msr CPSR_c,#MODE_ABT|I_BIT|F_BIT // Abort Mode
62 sub r0,r0,#ABT_STACK_SIZE
63 msr CPSR_c,#MODE_FIQ|I_BIT|F_BIT // FIQ Mode
65 sub r0,r0,#FIQ_STACK_SIZE
66 msr CPSR_c,#MODE_IRQ|I_BIT|F_BIT // IRQ Mode
68 sub r0,r0,#IRQ_STACK_SIZE
69 msr CPSR_c,#MODE_SVC|I_BIT|F_BIT // Supervisor Mode
71 sub r0,r0,#SVC_STACK_SIZE
72 msr CPSR_c,#MODE_SYS|I_BIT|F_BIT // System Mode
75 # Disable interrupt from VIC
76 .equ VICINTENABLE, 0xFFFFF010
77 .equ VICINTENCLR, 0xFFFFF014
78 .equ VICSOFTINT, 0xFFFFF018
79 .equ VICSOFTINTCLEAR, 0xFFFFF01C
84 STR R1, [R0,#VICINTENCLR-VICINTENABLE]
85 STR R1, [R0,#VICSOFTINTCLEAR-VICINTENABLE]
87 # Enable interrupts and return back into supervisor mode
88 msr CPSR_c,#MODE_SVC // Supervisor Mode
90 # Relocate .data section (Copy from ROM to RAM)
102 # Clear .bss section (Zero init)
104 LDR R1, =__bss_start__
111 # Enter the C _setup_board code
113 LDR R0, =_setup_board
123 __main_exit: B __main_exit
125 .size _start, . - _start