From 55321cec6a72dd9b2e0ad6fb94ff2cc42937a14a Mon Sep 17 00:00:00 2001 From: sreenivasulu velpula Date: Fri, 11 Jul 2014 17:27:25 +0530 Subject: [PATCH] arm: tegra: vcm30t124: Enable CPU CVB support - Add cl-dvfs platform data - Add function call to get cpu clock switch cooling device trip points. Bug 200002255 Change-Id: I07e0a9e8d170543906f91979fb35b98c02fe18cb Signed-off-by: sreenivasulu velpula Reviewed-on: http://git-master/r/437195 Reviewed-by: Sandeep Trasi Tested-by: Sandeep Trasi --- .../tegra_vcm30t124_gnu_linux_defconfig | 2 +- arch/arm/mach-tegra/board-common.c | 7 +++ arch/arm/mach-tegra/board-common.h | 5 +- arch/arm/mach-tegra/board-vcm30_t124-power.c | 58 ++++++++++++++++++- 4 files changed, 69 insertions(+), 3 deletions(-) diff --git a/arch/arm/configs/tegra_vcm30t124_gnu_linux_defconfig b/arch/arm/configs/tegra_vcm30t124_gnu_linux_defconfig index c8528d5a4b6..e6187be6356 100644 --- a/arch/arm/configs/tegra_vcm30t124_gnu_linux_defconfig +++ b/arch/arm/configs/tegra_vcm30t124_gnu_linux_defconfig @@ -31,7 +31,7 @@ CONFIG_MACH_VCM30_T124=y CONFIG_TEGRA_CLOCK_DEBUG_WRITE=y # CONFIG_TEGRA_CORE_CAP is not set CONFIG_TEGRA_DYNAMIC_PWRDET=y -CONFIG_TEGRA_USE_DFLL_RANGE=0 +CONFIG_TEGRA_USE_DFLL_RANGE=3 CONFIG_TEGRA_PLLM_SCALED=y CONFIG_TEGRA_PLLCX_FIXED=y CONFIG_ARM_LPAE=y diff --git a/arch/arm/mach-tegra/board-common.c b/arch/arm/mach-tegra/board-common.c index 4a0a73709b1..9af108c0d20 100644 --- a/arch/arm/mach-tegra/board-common.c +++ b/arch/arm/mach-tegra/board-common.c @@ -227,6 +227,13 @@ void tegra_add_core_vmax_trips(struct thermal_trip_info *trips, int *num_trips) tegra_dvfs_get_core_vmax_cdev()); } +void tegra_add_cpu_clk_switch_trips(struct thermal_trip_info *trips, + int *num_trips) +{ + tegra_add_trip_points(trips, num_trips, + tegra_dvfs_get_cpu_clk_switch_cdev()); +} + struct pinctrl_dev *tegra_get_pinctrl_device_handle(void) { static struct pinctrl_dev *pctl_dev = NULL; diff --git a/arch/arm/mach-tegra/board-common.h b/arch/arm/mach-tegra/board-common.h index f87c4c6406d..d6e314bf7e1 100644 --- a/arch/arm/mach-tegra/board-common.h +++ b/arch/arm/mach-tegra/board-common.h @@ -1,7 +1,7 @@ /* * board-common.h: Common function API declaration for all board files. * - * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -36,6 +36,9 @@ void tegra_add_core_vmin_trips(struct thermal_trip_info *trips, int *num_trips); void tegra_add_cpu_vmax_trips(struct thermal_trip_info *trips, int *num_trips); void tegra_add_core_edp_trips(struct thermal_trip_info *trips, int *num_trips); void tegra_add_tgpu_trips(struct thermal_trip_info *trips, int *num_trips); +void tegra_add_cpu_clk_switch_trips(struct thermal_trip_info *trips, + int *num_trips); + void tegra_add_vc_trips(struct thermal_trip_info *trips, int *num_trips); void tegra_add_core_vmax_trips(struct thermal_trip_info *trips, int *num_trips); struct pinctrl_dev *tegra_get_pinctrl_device_handle(void); diff --git a/arch/arm/mach-tegra/board-vcm30_t124-power.c b/arch/arm/mach-tegra/board-vcm30_t124-power.c index 5a29a4c8571..ab04c8db204 100644 --- a/arch/arm/mach-tegra/board-vcm30_t124-power.c +++ b/arch/arm/mach-tegra/board-vcm30_t124-power.c @@ -166,6 +166,57 @@ static struct i2c_board_info __initdata max15569_vddcpu_boardinfo[] = { }, }; +#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS +/* board parameters for cpu dfll */ +static struct tegra_cl_dvfs_cfg_param vcm30_t124_cl_dvfs_param = { + .sample_rate = 12500, + + .force_mode = TEGRA_CL_DVFS_FORCE_FIXED, + .cf = 10, + .ci = 0, + .cg = 2, + + .droop_cut_value = 0xF, + .droop_restore_ramp = 0x0, + .scale_out_ramp = 0x0, +}; + +/* MAX15569: fixed 10mV steps from 600mV to 1400mV, with offset 0x0b */ +#define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1) +static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE]; +static inline void fill_reg_map(void) +{ + int i; + for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) { + pmu_cpu_vdd_map[i].reg_value = i + 0x0b; + pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i; + } +} + +static struct tegra_cl_dvfs_platform_data vcm30_t124_cl_dvfs_data = { + .dfll_clk_name = "dfll_cpu", + .pmu_if = TEGRA_CL_DVFS_PMU_I2C, + .u.pmu_i2c = { + .fs_rate = 400000, + .slave_addr = 0x74, + .reg = 0x07, + }, + .vdd_map = pmu_cpu_vdd_map, + .vdd_map_size = PMU_CPU_VDD_MAP_SIZE, + .flags = TEGRA_CL_DVFS_DYN_OUTPUT_CFG, + .cfg_param = &vcm30_t124_cl_dvfs_param, +}; + +static int __init vcm30_t124_cl_dvfs_init(void) +{ + fill_reg_map(); + tegra_cl_dvfs_device.dev.platform_data = &vcm30_t124_cl_dvfs_data; + platform_device_register(&tegra_cl_dvfs_device); + + return 0; +} +#endif + /* MAX15569 switching regulator for vdd_gpu */ static struct regulator_consumer_supply max15569_vddgpu_supply[] = { REGULATOR_SUPPLY("vdd_gpu", NULL), @@ -210,6 +261,10 @@ int __init vcm30_t124_regulator_init(void) tegra_pmc_pmu_interrupt_polarity(true); +#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS + vcm30_t124_cl_dvfs_init(); +#endif + /* C01 boards have tegra gpio for gpu_pwr_req and * boards before C01 have PMU gpio for gpu_pwr_req */ @@ -297,7 +352,8 @@ int __init vcm30_t124_soctherm_init(void) { vcm30_t124_soctherm_data.tshut_pmu_trip_data = &tpdata_max77663; - tegra_add_cpu_vmax_trips(vcm30_t124_soctherm_data.therm[THERM_CPU].trips, + tegra_add_cpu_clk_switch_trips( + vcm30_t124_soctherm_data.therm[THERM_CPU].trips, &vcm30_t124_soctherm_data.therm[THERM_CPU].num_trips); tegra_add_tgpu_trips( -- 2.39.2