Jon Mayo [Thu, 6 Feb 2014 02:30:51 +0000 (18:30 -0800)]
video: tegra: dc: fix uninitialized var warning
if win_num is 0, then post_sync_val is not initialized.
Set it to 0 to match post_sync_id's default of NVSYNCPT_INVALID.
Change-Id: I8d4c4b1110d396978182c52e38ebff482490f64a Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/364131 Reviewed-by: Automatic_Commit_Validation_User
Jon Mayo [Wed, 5 Feb 2014 21:40:36 +0000 (13:40 -0800)]
video: tegra: dc: clean up checkpatch warnings
Clean up warnings from checkpatch and gcc.
Change-Id: I08bd2fc4374d0ccc644d9d16fe80db9c6521aa61 Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/364083 Reviewed-by: Daniel Solomon <daniels@nvidia.com>
Neil Gabriel [Mon, 27 Jan 2014 16:18:22 +0000 (10:18 -0600)]
Add firmware path to the firmware search paths.
If the kernel is able to find firmware in the kernel firmware
search path (when requested through request_firmware()) it will
load it directly without the involvement of the usermodehelper/
udev process (which is not always available).
Neil Gabriel [Tue, 21 Jan 2014 18:03:59 +0000 (12:03 -0600)]
Attempt kernel firmware load before going to udev.
request_firmware() should fall back to usermodehelper
routines to load firmware only after a failed attempt
to load it directly. Prior to this change, the code
will attempt to lock the usermodehelper state before
attempting to load the firmware directly. If the
usermodehelper is disabled, the lock attempts will
fail and request_firmware() will exit without even
attempting a direct load.
Based on battery soc value battery health
and other battery information passed to framework layer,
to sync with battery information such as health and capacity
level moving get_scaled_soc api to work thread.
power: max17048: report scaled SoC by manipulating kernel threshold
Make kernel threshold SoC as 0% and scale the SoC read from device
as:
Read from device: 0 to threshold -> report 0%
Read from device: threshold+1 to 100% -> report as 1 to 100%.
Laxman Dewangan [Mon, 3 Feb 2014 06:27:32 +0000 (11:57 +0530)]
power: lc709203f: report scaled SoC by manipulating kernel threshold
Make kernel threshold SoC as 0% and scale the SoC read from device
as:
Read from device: 0 to threshold-> report 0%
Read from device: threshold + 1 to 100% -> report as 1 to 100%.
Laxman Dewangan [Mon, 3 Feb 2014 06:22:30 +0000 (11:52 +0530)]
power: charger-gauge-comm: add API for scaling SoC
The bootloader and kernel usage the same configuration of fuel
gauge and so SoC read from device is same on both the places.
It is require to run the kernel properly and shutdown gracefully,
the minimum base SoC for the kernel is more than the bootloader
0% SoC.
Add generic API for scaling the reported SoC on kernel based on
kernel thresold SoC. This thresold SoC will be used by BL to jump
to kernel and kernel will report this thresold as 0% SoC.
Jack Pham [Fri, 15 Nov 2013 22:53:14 +0000 (22:53 +0000)]
usb: xhci: Check for XHCI_PLAT in xhci_cleanup_msix()
If CONFIG_PCI is enabled, make sure xhci_cleanup_msix()
doesn't try to free a bogus PCI IRQ or dereference an invalid
pci_dev when the xHCI device is actually a platform_device.
This patch should be backported to kernels as old as 3.9, that
contain the commit 52fb61250a7a132b0cfb9f4a1060a1f3c49e5a25
"xhci-plat: Don't enable legacy PCI interrupts."
Cc: stable@vger.kernel.org
Change-Id: I6601c3db7a0a4f5ebef6c64118eb62a67701c42a
Reviewed-on: http://git-master/r/358200 Signed-off-by: Jack Pham <jackp@codeaurora.org> Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Reviewed-on: http://git-master/r/361700 Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Tested-by: Thomas Cherry <tcherry@nvidia.com>
Xenia Ragiadakou [Wed, 14 Aug 2013 02:55:19 +0000 (02:55 +0000)]
xhci: fix dma mask setup in xhci.c
The function dma_set_mask() tests internally whether the dma_mask pointer
for the device is initialized and fails if the dma_mask pointer is NULL.
On pci platforms, the device dma_mask pointer is initialized, when pci
devices are enumerated, to point to the pci_dev->dma_mask which is 0xffffffff.
However, for non-pci platforms, the dma_mask pointer may not be initialized
and in that case dma_set_mask() will fail.
This patch initializes the dma_mask and the coherent_dma_mask to 32bits
in xhci_plat_probe(), before the call to usb_create_hcd() that sets the
"uses_dma" flag for the usb bus and the call to usb_add_hcd() that creates
coherent dma pools for the usb hcd.
Moreover, a call to dma_set_mask() does not set the device coherent_dma_mask.
Since the xhci-hcd driver calls dma_alloc_coherent() and dma_pool_alloc()
to allocate consistent DMA memory blocks, the coherent DMA address mask
has to be set explicitly.
This patch sets the coherent_dma_mask to 64bits in xhci_gen_setup() when
the xHC is capable for 64-bit DMA addressing.
If dma_set_mask() succeeds, for a given bitmask, it is guaranteed that
the given bitmask is also supported for consistent DMA mappings.
Other changes introduced in this patch are:
- The return value of dma_set_mask() is checked to ensure that the required
dma bitmask conforms with the host system's addressing capabilities.
- The dma_mask setup code for the non-primary hcd was removed since both
primary and non-primary hcd refer to the same generic device whose
dma_mask and coherent_dma_mask are already set during the setup of
the primary hcd.
- The code for reading the HCCPARAMS register to find out the addressing
capabilities of xHC was removed since its value is already cached in
xhci->hccparams.
- hcd->self.controller was replaced with the dev variable since it is
already available.
Change-Id: I4fae4a4c8cd419bb80fcf623da3e6b2a797440f4
Reviewed-on: http://git-master/r/357120 Signed-off-by: Xenia Ragiadakou <burzalodowa@gmail.com> Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Reviewed-on: http://git-master/r/361699 Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Tested-by: Thomas Cherry <tcherry@nvidia.com>
Alex Frid [Thu, 30 Jan 2014 08:17:05 +0000 (00:17 -0800)]
ARM: tegra: Support Ardbeg DT variants w/wo DFLL data
DT variants that are used for Ardbeg platforms with E1735 PMIC module
may or may not include DFLL data. To keep functionality intact in the
latter case DFLL platform data in Ardbeg board file was retained, but
the respective platform devices are registered from board file only if
DT DFLL node is not available. Also added a special hook to modify DT
for E1767 prototype module that yet to be productized, and does not
have separate DT variant.
Consolidated E1735 setting for suspend mode in ardbeg_suspend_init()
function. Set E1735 regulator idle mode thresholds during regulator
initialization.
Alex Frid [Thu, 30 Jan 2014 06:59:54 +0000 (22:59 -0800)]
ARM: dts: tegra: Prepare Ardbeg E1735 DT variants
Created device tree variants for Ardbeg platform with E1735 PMIC
module:
arch/arm/boot/dts/tegra124-ardbeg-e1735.dts
arch/arm/boot/dts/tegra124-ardbeg-e1735-a03-00.dts
For now, no changes in content: new variants just point to the
respective generic Ardbeg variants.
Songhee Baek [Mon, 3 Feb 2014 19:10:34 +0000 (11:10 -0800)]
ASoC: tegra-alt: fix checking error case.
To register max9487, this machine driver uses i2c_new_device,
i2c_new_device returns NULL when it is error case, not a error code.
So, IS_ERR is not proper to check the error.
Laxman Dewangan [Mon, 3 Feb 2014 12:19:30 +0000 (17:49 +0530)]
i2c: add flag for cancel transfer when adapter shutdown
Add support to cancel the transfer when the adapater in shutdown
state. Also add API to re-enable transfer when actually client
wants to do forcefully transfer.
Arto Merilainen [Mon, 13 Jan 2014 08:16:39 +0000 (10:16 +0200)]
video: tegra: host: Rework T132 power features
T132 power features were disabled using a single loop that went
through host1x devices and removed callbacks. Even though the solution
is simple and the loop will in the end be removed, it does not allow
enough control before all power features have been verified.
This patch creates new platform data structures for T132. The code
goes through T132 devices and if an override for platform data is
available, the original pdata is replaced by the override version.
Chaitanya Bandi [Thu, 30 Jan 2014 13:12:36 +0000 (18:42 +0530)]
ARM: tegra: tn8: Update parameters of lc709203f
Added parameters thermistor-b and initial-rsoc.
Also, as TN8 plaftorm that uses lc709203f FG has the
battery thermistor connected to FG, tz_name parameter
is not required.
Arto Merilainen [Thu, 23 Jan 2014 08:33:36 +0000 (10:33 +0200)]
video: tegra: host: gk20a: Export raw counters
GPU scaling in user space is moving towards using raw counter
readings instead of instantaneous load. This patch exports busy
and idle counters to userspace as sysfs nodes counters and
counters_reset. The first node shows raw counter values and
the second node shows the raw values and resets them.
This patch does not account for possible wrapping issues.
Charles Kong [Wed, 5 Feb 2014 00:46:47 +0000 (16:46 -0800)]
arm: tegra: ardbeg: force CAM_1V8_LDO1 to be true
Force CAM_1V8_LDO1 to remove the ~19mW power leakage at camera i2c
lines when camera is off. The power impact of CAM_1V8_LDO1 is ~0.55mW.
The idle battery power is also dropped by this change.
Bug: 1441261
Change-Id: I690b6e71d0935242dcb8211fd291c2d43441ec20 Signed-off-by: Charles Kong <charlesk@nvidia.com>
Reviewed-on: http://git-master/r/363528 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Chaitanya Bandi [Fri, 17 Jan 2014 11:57:45 +0000 (17:27 +0530)]
ARM: tegra: Enable I2Cs in t124 dt files
Enabled I2Cs in t124 SOC dt files instead of
doing it in board specific dt files. Also
made GEN1_I2C, PWR_I2C, CAM_I2C, I2C6 to operate
at FM mode and GEN2_I2C, DDC_I2C in Standard mode
as default from SOC dt files.
Seema Khowala [Mon, 3 Feb 2014 22:55:25 +0000 (14:55 -0800)]
arm: tegra: t132: add Innolux 11.6" eDP panel
Add support for Innolux 11.6" eDP panel.
The code assumes that the only variant of this panel
is NVSR-enabled. NVSR PWM support is work in progresss;
for now, Tegra PWM for backlight is present only as a
placeholder.
Catalin Marinas [Fri, 31 May 2013 15:30:58 +0000 (16:30 +0100)]
arm64: spinlock: retry trylock operation if strex fails on free lock
An exclusive store instruction may fail for reasons other than lock
contention (e.g. a cache eviction during the critical section) so, in
line with other architectures using similar exclusive instructions
(alpha, mips, powerpc), retry the trylock operation if the lock appears
to be free but the strex reported failure.
Reported-by: Tony Thompson <anthony.thompson@arm.com> Acked-by: Will Deacon <will.deacon@arm.com>
Change-Id: Id170c917f99b794ec7be23e0b8da0fd05fd78ca1
Reviewed-on: http://git-master/r/355768 Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-on: http://git-master/r/361691 Reviewed-by: Seema Khowala <seemaj@nvidia.com> Tested-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Raghavendra VK [Sat, 23 Nov 2013 15:54:36 +0000 (21:24 +0530)]
V3L: T124: dc: Support 1920x1200 mode
To support 1920x1200 HDMI monitor for T124.
- To reserve enough space for frame buffers for screen resolution up to
1920x1200. Each pixel consists with 4 bytes and a display controller
needs two set of FB, so each DC needs FB space reserved for
1920 * 1200 * 4 * 2 = 18432000 = 18M bytes
And the T124 has two DC.
- To limit the parent of HDMI pclk to 600MHz. Usually the pll_d2 is the
parent clock of hdmi pclk and T124 has 600MHz limit on it.
This change needs to be reviewed in the bug 1420652 because setting
the hdmi pclk has some problem with certain value.
Daniel Solomon [Wed, 29 Jan 2014 22:32:18 +0000 (14:32 -0800)]
video: tegra: dc: fix soft clipping correction
- Change "k" to be fractional part of HW_K, matching
what the algorithm assumes
- Fix reading of bin_width
- Enable soft clipping correction only if
soft clipping is enabled
Change-Id: I0c4872d7c009429d7c3c2abbac3658b5713e14c9 Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/361751 Reviewed-by: Jon Mayo <jmayo@nvidia.com> Tested-by: Jon Mayo <jmayo@nvidia.com>
Daniel Solomon [Thu, 30 Jan 2014 01:33:18 +0000 (17:33 -0800)]
video: tegra: dc: allow selection of bin_width -1
Valid bin_width values are -1, 1, 2, 4, and 8. We
allow setting of bin_width via sysfs to all these values
except for -1. Add this missing value to the allowed
settings.
Change-Id: Icb60574212c203238c6db2d1ada94d3ae3ea9a4f Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/361792 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Laxman Dewangan [Tue, 4 Feb 2014 11:36:43 +0000 (17:06 +0530)]
pinctrl: tegra: add register base address and group name when dumping
Add the register base address in the offset and group name when
dumping register content. This helps on quick reference of the
content of register and relate to the pin.
Timo Alho [Wed, 29 Jan 2014 18:45:38 +0000 (20:45 +0200)]
edp: tn8: set sysedp_dynamic capping pthrot ratio
soc_therm is set to throttle 75% on OC signal. To account the dynamic
budgeting to match this throttling (in the context of modem consumer),
set the pthrot_ratio parameter to 75%.
Change-Id: I320f1d5433c48c4f44e348f8a642b34c9da8cd4b Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/361615
(cherry picked from commit 8bb71b6df9c3932ac0922aec124d91203b85cd67)
Reviewed-on: http://git-master/r/362848 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Timo Alho [Wed, 29 Jan 2014 13:20:02 +0000 (15:20 +0200)]
edp: tn8: implement battery OC WAR
P1761-A02 battery temp sensing is not functional - this will cause
system EDP to battery OC limited (4A) already in room temperature. As
a workaround relax battery OC limit to 9A at any temperarure.
Arto Merilainen [Sat, 1 Feb 2014 10:44:40 +0000 (12:44 +0200)]
video: tegra: host: QoS triggers postscale
For some devices we use QoS to define the minimum required frequency.
As this mechanism bypasses totally devfreq and the usual device profile,
we need to trigger postscale callback also in these cases to ensure that
i.e. EMC is scaled correctly at the same time.
Arto Merilainen [Sat, 1 Feb 2014 10:14:03 +0000 (12:14 +0200)]
video: tegra: host: Inform EDP in prescale
This far EDP was informed about changed load as part of postscale
callback when we changed the frequency. The theory behind this idea
has been that we need to inform EDP due to changed constraint.
However, we have seen cases where updating load information for EDP
would be beneficial more often. This patch modifies the call sequence
so that we inform EDP each time we submit work to GPU.
Varun Wadekar [Thu, 16 Jan 2014 07:07:06 +0000 (12:37 +0530)]
arm: tegra: flush dcache before cluster switch
There's no point having the secure world flush the dcache
for us. This is more of a requirement from the NS world and
the chip, rather than the secure world.
Change-Id: I7186774e6fd6072f8260780b82203ce5d9ddf820 Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: http://git-master/r/361797 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Chris Johnson <cwj@nvidia.com>
Alex Frid [Tue, 28 Jan 2014 05:58:14 +0000 (21:58 -0800)]
Revert "ARM: tegra: power: Add VDD_GPU SiMon consumer"
This reverts commit 84169083f38a0b7b5e9282d0f095701059d51be9.
No need for direct consumers, since SiMon registration for vdd_gpu
notification has been moved to common DVFS rail interface.
Alex Frid [Tue, 28 Jan 2014 05:31:50 +0000 (21:31 -0800)]
ARM: tegra: power: Simplify SiMon GPU grading init
Simplified initial GPU SiMon grader registration with vdd_gpu regulator
by using DVFS rail interface (instead of creating/destroying temporary
regulator consumer).
projects / sojka / nv-tegra / linux-3.10.git / log