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ARM: tegra: t124: Set DDR mode's TRIM_VAL to 0
authorNaveen Kumar Arepalli <naveenk@nvidia.com>
Wed, 16 Oct 2013 08:52:15 +0000 (14:22 +0530)
committerNaveen Kumar Arepalli <naveenk@nvidia.com>
Thu, 17 Oct 2013 06:24:36 +0000 (23:24 -0700)
commitf9061c3e5e12cbfe33d351e730c65956b0b625ab
tree0d81a495fc045d85e6a6634777aa1764b002afc3tree | snapshot
parentce6802b982e3fd2b8259eea361868156ed376b37commit | diff
ARM: tegra: t124: Set DDR mode's TRIM_VAL to 0

-For eMMC change DDR mode's TRIM_VAL from 4 to 0
as per char team data.

Bug 1333552

Change-Id: Ia5d877be07de80dcfe55ca8f78528e8a6a6fa12c
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/299864
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
arch/arm/mach-tegra/board-ardbeg-sdhci.c diff | blob | history
arch/arm/mach-tegra/board-loki-sdhci.c diff | blob | history