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(parent: 22c184a) | patch
ARM: tegra21: make pinmux drive register range to 0x8d8 to 0xb78
authorLaxman Dewangan <ldewangan@nvidia.com>
Thu, 4 Jun 2015 10:00:19 +0000 (15:30 +0530)
committerLaxman Dewangan <ldewangan@nvidia.com>
Tue, 9 Jun 2015 05:41:44 +0000 (22:41 -0700)
commit92cf119f06c9fb7aa819e6911ea9c3e47407d21b
treea0fb2509cdf6057f7eeecdeb8b9b1e973fe7e38ftree | snapshot
parent22c184a3b1a45bb8799d1c37827f4a7154049a7acommit | diff
ARM: tegra21: make pinmux drive register range to 0x8d8 to 0xb78

Include the PAD control for QSPI i.e. QSPI comp control and
LPBK control inside driver control so that it can be configure
through pinmux DT for desired value.

bug 1650903

Change-Id: Id21e363b229ff0d14559cff29dbfe8134500c8e0
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
(cherry picked from commit ca29c2e5ea4d5181710ac4bcfc9ff5ea68a91a4c)
Reviewed-on: http://git-master/r/754582
arch/arm64/boot/dts/tegra210-soc-base.dtsi diff | blob | history