arm: tegra: PCIe Clock and Reset Conform to Spec

arm: tegra: PCIe Clock and Reset Conform to Spec

PCIe Reset line must be asserted for at least 100us after clock is enabled.
PEX 2 Controller Register fix, offsets are not at constant intervals.

Bug 1228219

Change-Id: I79d354a9cf25144a8109d7d84e01b28c09017563
Signed-off-by: sreenivasulu velpula <svelpula@nvidia.com>
Reviewed-on: http://git-master/r/227450
(cherry picked from commit 17075e925e7cc708cb9748e17966995b98ccc9c3)
Reviewed-on: http://git-master/r/266430
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>