]> rtime.felk.cvut.cz Git - sojka/nv-tegra/linux-3.10.git/commit
video: tegra: host: fix 64 bit regops
authorDeepak Nibade <dnibade@nvidia.com>
Tue, 18 Feb 2014 12:57:29 +0000 (18:27 +0530)
committerTerje Bergstrom <tbergstrom@nvidia.com>
Wed, 26 Feb 2014 13:46:37 +0000 (05:46 -0800)
commit1a11be3c7652d7a46842aa148012468c7bdf3561
treec0cf7612cb55ce26b073630000efb8c4970bb2c0
parenta31c820e9317e3dcfb570b4b26fd2d1b1589d631
video: tegra: host: fix 64 bit regops

In regops, there is a whitelist of allowed registers. The
whitelisted registers are always considered to be 32-bit.
However, we do not consider 64-bit read/write operations
during whitelist validation.
e.g. if register at 0x400500 is whitelisted, with a 64-bit
read we can also read register at 0x400504 which is not
whitelisted

To fix this, first separate out check_whitelists() function
from validate_reg_op_offset() which does the whitelist
validation of given offset.
Then pass offset to this function to check if it is
whitelisted or not.
If yes and if operation is 64-bit, then pass (offset + 4)
to check_whitelists() to check if next offset is also
whitelisted or not.

Bug 1440107

Change-Id: I9a08cc031e741987f5577d47d32b303ba114ff07
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/368437
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
drivers/video/tegra/host/gk20a/regops_gk20a.c