pcie: host: tegra: optimize boot time

pcie: host: tegra: optimize boot time

optimizes pcie link detection by initially checking for
DL_LINK_ACTIVE with a timeout out of 100ms (spec defined)
and further PERST and link detection cycles are based on
whether or not RDET_STATUS of UPHY lanes corresponding to
PCIe ports is set

Bug 200159257

Change-Id: I8dcbd37cdff5b60c0f36c61e492ba685862802d0
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: http://git-master/r/927110
(cherry picked from commit ed5b09a5ebfb576a5105ea5fd6633285a4f55030)
Reviewed-on: http://git-master/r/932523
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hayden Du <haydend@nvidia.com>