/*
* arch/arm/boot/dts/tegra124-vcm30_t124.dtsi
*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
-#include "tegra124.dtsi"
+#include "tegra124-soc-shield.dtsi"
#include <tegra124-platforms/tegra124-vcm30t124-fixed-reg.dtsi>
/ {
+ nvidia,dtbbuildtime = __DATE__, __TIME__;
+
#address-cells = <2>;
#size-cells = <2>;
spi@7000d400 {
status = "disabled";
+ nvidia,clk-parents = "pll_p";
spi@0 {
compatible = "spidev";
reg = <0>;
spi@7000d600 {
status = "disabled";
+ nvidia,clk-parents = "pll_p";
spi@1 {
compatible = "spidev";
reg = <1>;
spi@7000d800 {
status = "disabled";
+ nvidia,clk-parents = "pll_p";
spi@1 {
compatible = "spidev";
reg = <1>;
spi@7000dc00 {
status = "disabled";
+ nvidia,clk-parents = "pll_p";
spi@0 {
compatible = "spidev";
reg = <0>;
*/
nvidia,lane_owner = <0x2>; /* PCIE-0, SSP1 and SATA */
nvidia,ulpicap = <0>; /* No ulpi support */
+ nvidia,firmware_file = "tegra_xusb_firmware";
+
+ /*Characterization settings*/
+ prod-settings {
+ #prod-cells = <4>;
+ prod_c_ss0 {
+ prod = <
+ 3 0x00000058 0x00000000 0x26ec75f0
+ 3 0x00000068 0x00000000 0x007e08EE
+ 3 0x00000078 0x04ffc000 0x10000000
+ 3 0x00000090 0xfffc0e44 0x00000100
+ >;
+ };
+ prod_c_ss1 {
+ prod = <
+ 3 0x0000005c 0x00000000 0x26f070f0
+ 3 0x0000006c 0x00000000 0x002008ee
+ 3 0x0000007c 0x04ffc000 0x10000000
+ 3 0x00000094 0xfffc0e44 0x00000100
+ >;
+ };
+ };
+ };
+
+ pmc@7000e400 {
+ status = "okay";
+ nvidia,invert-interrupt;
};
pcie-controller {
status = "disabled";
pci@1,0 {
+ nvidia,disable-clock-request;
status = "disabled";
};
pci@2,0 {
+ nvidia,disable-clock-request;
status = "disabled";
};
};
sata@70020000 {
nvidia,enable-sata-port;
+ nvidia,l2p_fifo_depth = /bits/8 <0x7>;
status = "disabled";
};
+ /* SDMMC1 */
sdhci@700b0000 {
- tap-delay = <0x3B>;
+ tap-delay = <0x10>;
trim-delay = <0x2>;
nvidia,is-ddr-trim-delay;
- ddr-trim-delay = <0x4>;
+ ddr-trim-delay = <0x2>;
mmc-ocr-mask = <0>;
- uhs-mask = <0x40>;
+ uhs-mask = <0x68>; /* HS400, HS200, DDR50 modes are disabled */
bus-width = <4>;
built-in;
ddr-clk-limit = <51000000>;
vmmc-supply = <&vmmc_dummy>;
disable-clock-gate;
nvidia,disable-auto-cal;
+ /* clock freq based on mode: ID LEGACY MMC_HS SD_HS SDR12 SDR25 SDR50 SDR104 DDR50 HS200 HS400 */
+ fixed-clock-freq = <25500000 24000000 0 47000000 24000000 47000000 94000000 204000000 0 0 0>;
status = "disabled";
- nvidia,update-pinctrl-settings;
};
+ /* SDMMC4 */
sdhci@700b0600 {
tap-delay = <0x39>;
trim-delay = <0x3>;
ddr-trim-delay = <0x4>;
mmc-ocr-mask = <0>;
- uhs-mask = <0x40>;
+ uhs-mask = <0x40>; /* HS400 mode is disabled */
bus-width = <8>;
built-in;
ddr-clk-limit = <51000000>;
max-clk-limit = <200000000>;
pll_source = "pll_c", "pll_p";
vmmc-supply = <&vmmc_dummy>;
- nvidia,disable-auto-cal;
+ calib-3v3-offsets = <0x615F>;
+ calib-1v8-offsets = <0x615F>;
+ auto-cal-step = <0x7>;
+ /* clock freq based on mode: ID LEGACY MMC_HS SD_HS SDR12 SDR25 SDR50 SDR104 DDR50 HS200 HS400 */
+ fixed-clock-freq = <25500000 25500000 51000000 0 0 0 0 0 102000000 188000000 0>;
status = "disabled";
- nvidia,disable-auto-cal;
};
+ /* SDMMC2 */
sdhci@700b0200 {
tap-delay = <0x31>;
trim-delay = <0x3>;
ddr-trim-delay = <0x3>;
mmc-ocr-mask = <0>;
- uhs-mask = <0x28>;
+ uhs-mask = <0x60>; /* HS400, HS200 modes are disabled */
built-in;
- ddr-clk-limit = <30000000>;
- max-clk-limit = <51000000>;
+ ddr-clk-limit = <40800000>;
+ max-clk-limit = <81600000>;
pll_source = "pll_c", "pll_p";
vmmc-supply = <&vmmc_dummy>;
nvidia,disable-auto-cal;
+ /* clock freq based on mode: ID LEGACY MMC_HS SD_HS SDR12 SDR25 SDR50 SDR104 DDR50 HS200 HS400 */
+ fixed-clock-freq = <25500000 25500000 51000000 0 0 0 0 0 81600000 80500000 0>;
status = "disabled";
};
+ /* SDMMC3 */
sdhci@700b0400 {
cd-gpios = <&gpio 133 0>;
wp-gpios = <&gpio 132 0>;
- tap-delay = <0x39>;
+ tap-delay = <0x5>;
trim-delay = <0x3>;
mmc-ocr-mask = <3>;
- uhs-mask = <0x28>;
+ uhs-mask = <0x68>; /* HS400, HS200, DDR50 modes are disabled */
bus-width = <4>;
max-clk-limit = <204000000>;
pll_source = "pll_c", "pll_p";
vmmc-supply = <&vmmc_dummy>;
- nvidia,disable-auto-cal;
+ cd_wakeup_incapable = <1>;
+ calib-3v3-offsets = <0x710A>;
+ calib-1v8-offsets = <0x710A>;
+ auto-cal-step = <0x7>;
status = "disabled";
- nvidia,update-pinctrl-settings;
+ /* clock freq based on mode: ID LEGACY MMC_HS SD_HS SDR12 SDR25 SDR50 SDR104 DDR50 HS200 HS400 */
+ fixed-clock-freq = <25500000 24000000 0 47000000 24000000 47000000 94000000 204000000 0 0 0>;
nvidia,enable-ext-loopback;
+ nvidia,auto-cal-slew-override;
};
snor {
};
};
+ extcon {
+ compatible = "simple-bus";
+
+ id_gpio_extcon: extcon@0 {
+ compatible = "extcon-gpio";
+ extcon-gpio,name = "OTG-nID";
+ extcon-gpio,cable-name = "OTG nID";
+ #extcon-cells = <1>;
+ status="disabled";
+ };
+
+ vbus_gpio_extcon: extcon@1 {
+ compatible = "extcon-gpio";
+ extcon-gpio,name = "gadget-VBUS";
+ extcon-gpio,default-connected;
+ extcon-gpio,cable-name = "gadget VBUS";
+ #extcon-cells = <1>;
+ status="disabled";
+ };
+ };
+
+ udc@7d000000 {
+ nvidia,port-otg;
+ /*xcvr-setup-offset is in 2s complement for negative values*/
+ nvidia,xcvr-setup-offset = /bits/8 <16>;
+ status = "okay";
+ };
+
+ otg@7d000000 {
+ nvidia,id-detection-type = <2>;
+ status = "okay";
+ };
+
+ ehci@7d000000 {
+ nvidia,port-otg;
+ nvidia,has-hostpc;
+ nvidia,turn_off_vbus_on_lp0;
+ nvidia,id-detection-type = <2>;
+ nvidia,hssync-start-delay = <0>;
+ nvidia,idle-wait-delay = <17>;
+ nvidia,elastic-limit = <16>;
+ nvidia,term-range-adj = <6>;
+ nvidia,xcvr-setup = <15>;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ nvidia,xcvr-use-fuses;
+ nvidia,vbus-oc-map = <4>;
+ nvidia,xcvr-setup-offset = <0>;
+ status = "disabled";
+ };
+
+ ehci@7d004000 {
+ nvidia,has-hostpc;
+ nvidia,turn_off_vbus_on_lp0;
+ nvidia,hot_plug;
+ nvidia,hssync-start-delay = <0>;
+ nvidia,idle-wait-delay = <17>;
+ nvidia,elastic-limit = <16>;
+ nvidia,term-range-adj = <6>;
+ nvidia,xcvr-setup = <8>;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ nvidia,xcvr-use-fuses;
+ nvidia,vbus-oc-map = <5>;
+ nvidia,xcvr-setup-offset = <1>;
+ status = "okay";
+ };
+
+ ehci@7d008000 {
+ nvidia,has-hostpc;
+ nvidia,turn_off_vbus_on_lp0;
+ nvidia,hot_plug;
+ nvidia,hssync-start-delay = <0>;
+ nvidia,idle-wait-delay = <17>;
+ nvidia,elastic-limit = <16>;
+ nvidia,term-range-adj = <6>;
+ nvidia,xcvr-setup = <8>;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ nvidia,xcvr-use-fuses;
+ nvidia,vbus-oc-map = <5>;
+ nvidia,xcvr-setup-offset = <2>;
+ status = "okay";
+ };
+
dfll@70110000 {
board-params = <&{/cpu_dfll_board_params}>;
i2c-pmic-integration = <&{/cpu_dfll_pmic_integration}>;
gpu_edp {
status = "disabled";
};
+
+ therm_est_sensor {
+ status = "disabled";
+ };
+
+ thermal-zones {
+ therm_est {
+ status = "disabled";
+ };
+ };
+
+ pinmux@70000868 {
+ prod-settings {
+ prod {
+ status = "disabled";
+ };
+ };
+ };
+
+ bthrot_cdev {
+ status = "disabled";
+ };
+
+ /*Re-setting the clock frequencies for visibility*/
+ i2c@7000c000 {
+ clock-frequency = <400000>;
+ };
+
+ i2c@7000c400 {
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c500 {
+ clock-frequency = <400000>;
+ };
+
+ i2c@7000c700 {
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000d000 {
+ clock-frequency = <400000>;
+ };
+
+ i2c@7000d100 {
+ clock-frequency = <400000>;
+ };
+
+ soctherm@0x700E2000 {
+ soctherm-clock-frequency = <51000000>;
+ tsensor-clock-frequency = <400000>;
+ };
};
projects / sojka / nv-tegra / linux-3.10.git / blobdiff