/*
 * arch/arm/boot/dts/tegra124-vcm30_t124.dtsi
 *
 * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 */

#include "tegra124.dtsi"
#include <tegra124-platforms/tegra124-vcm30t124-fixed-reg.dtsi>

/ {
	#address-cells = <2>;
	#size-cells = <2>;

	chosen {
		nvidia,tegra-hypervisor-mode;
	};

	i2c@7000c400 {
		nvidia,clock-always-on;
	};

	/* vcm30t124 mcm doesn't need hda device */
	hda@70030000 {
		compatible = "nvidia,tegra30-hda";
		status = "disabled";
	};

	/*
	 * vcm30t124 mcm dtsi assumes all uart ports as high speed
	 *
	 * The board file has to update the compatible property to
	 * "nvidia,tegra20-uart" for debug uart port
	 */
	serial@70006000 {
		compatible = "nvidia,tegra114-hsuart";
		status = "disabled";
	};

	serial@70006040 {
		compatible = "nvidia,tegra114-hsuart";
		status = "disabled";
	};

	serial@70006200 {
		compatible = "nvidia,tegra114-hsuart";
		status = "disabled";
	};

	serial@70006300 {
		compatible = "nvidia,tegra114-hsuart";
		status = "disabled";
	};

	spi@7000d400 {
		status = "disabled";
		spi@0 {
			compatible = "spidev";
			reg = <0>;
			spi-max-frequency = <25000000>;
			/* spi-cpha;
			 * spi-cpol;
			 * spi-cs-high;
			 */
		};
	};

	spi@7000d600 {
		status = "disabled";
		spi@0 {
			compatible = "spidev";
			reg = <0>;
			spi-max-frequency = <25000000>;
		};
	};

	spi@7000d800 {
		status = "disabled";
		spi@0 {
			compatible = "spidev";
			reg = <0>;
			spi-max-frequency = <25000000>;
		};
	};

	spi@7000dc00 {
		status = "disabled";
		spi@0 {
			compatible = "spidev";
			reg = <0>;
			spi-max-frequency = <25000000>;
		};
	};

	xusb@70090000 {
		status = "disabled";
		nvidia,gpio_ss1_sata = <0>;

		/*
		 * BIT0 - BIT7 : SS ports
		 * BIT8 - BIT15 : USB2 UTMI ports
		 * BIT16 - BIT23 : HSIC ports
		 * BIT24 - BIT31 : ULPI ports
		 * XXXX XXXP XXXX XXHH XXXX XUUU XXXX XXSS
		 */
		nvidia,portmap = <0x402>; /* SSP1, USB2P2 */
		/* XXXX .. XSSS XSSS */
		nvidia,ss_portmap = <0x20>; /* SSP1 on USB2P2 */

		/*
		 * BIT 2 (0/1): PCIE-0/SSP0
		 * BIT 1 (0/1): PCIE-1/SSP1
		 * BIT 0 (0/1): SATA/SSP1
		 */
		nvidia,lane_owner = <0x2>; /* PCIE-0, SSP1 and SATA */
		nvidia,ulpicap = <0>; /* No ulpi support */
	};

	pcie-controller {
		nvidia,port0_status = <1>;
		nvidia,port1_status = <1>;
		status = "disabled";
	};

	sata@70020000 {
		nvidia,enable-sata-port;
		status = "disabled";
	};

	sdhci@700b0600 {
		tap-delay = <0x4>;
		trim-delay = <0x4>;
		ddr-trim-delay = <0x4>;
		mmc-ocr-mask = <0>;
		uhs_mask = <0x40>;
		bus-width = <8>;
		built-in;
		ddr-clk-limit = <51000000>;
		max-clk-limit = <200000000>;
		pll_source = "pll_m", "pll_p";
		vmmc-supply = <&vmmc_dummy>;
		status = "disabled";
	};

	sdhci@700b0200 {
		tap-delay = <0x1>;
		trim-delay = <0x3>;
		ddr-trim-delay = <0x3>;
		mmc-ocr-mask = <0>;
		uhs_mask = <0x20>;
		built-in;
		ddr-clk-limit = <30000000>;
		max-clk-limit = <51000000>;
		pll_source = "pll_m", "pll_p";
		vmmc-supply = <&vmmc_dummy>;
		status = "disabled";
	};

	sdhci@700b0400 {
		cd-gpios = <&gpio 133 0>;
		wp-gpios = <&gpio 132 0>;
		tap-delay = <0>;
		trim-delay = <3>;
		mmc-ocr-mask = <3>;
		uhs_mask = <0x28>;
		bus-width = <4>;
		max-clk-limit = <204000000>;
		pll_source = "pll_m", "pll_p";
		vmmc-supply = <&vmmc_dummy>;
		status = "disabled";
	};

	snor {
		pinctrl-names = "pi7_gmi_mode", "pi7_rsvd_mode";
		pinctrl-0 = <&nor_pi7_gmi>;
		pinctrl-1 = <&nor_pi7_rsvd>;
		nvidia,timing-default = <0x30300273>, <0x00030302>;
		nvidia,timing-read = <0x30300273>, <0x00030302>;
		nvidia,nor-mux-mode = <0x0>;
		nvidia,nor-read-mode = <0x1>;
		nvidia,nor-page-length = <0x2>;
		nvidia,nor-ready-active = <0x0>;
		nvidia,flash-map-name = "cfi_probe";
		nvidia,flash-width = <0x2>;
		nvidia,num-chips = <0x1>;
		use-advanced-sector-protection;
		nvidia,gmi-oe-pin = <&gpio 65 0>; /* gpio PI1 */
		status = "disabled";
		cs-info@0 {
			nvidia,cs = <0x0>;
			nvidia,num_cs_gpio = <0x0>;
			nvidia,phy_addr = <0x0 0x48000000>;
			nvidia,phy_size = <0x04000000>;
		};

	};
};