5 * Copyright (C) 2011 Texas Instruments, Inc.
6 * Copyright (C) 2011 Google, Inc.
8 * Copyright (C) 2014-2016 NVIDIA Corporation. All rights reserved.
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 #include <linux/init.h>
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
25 #include <linux/delay.h>
26 #include <linux/dma-buf.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/firmware.h>
29 #include <linux/tegra_nvadsp.h>
30 #include <linux/tegra-soc.h>
31 #include <linux/elf.h>
32 #include <linux/device.h>
33 #include <linux/clk.h>
34 #include <linux/clk/tegra.h>
35 #include <linux/irqchip/tegra-agic.h>
36 #include <linux/interrupt.h>
37 #include <linux/slab.h>
38 #include <linux/pm_runtime.h>
40 #include <asm-generic/uaccess.h>
42 #include "ape_actmon.h"
45 #include "dram_app_mem_manager.h"
46 #include "adsp_console_dbfs.h"
48 #define NVADSP_ELF "adsp.elf"
49 #define NVADSP_FIRMWARE NVADSP_ELF
51 #define MAILBOX_REGION ".mbox_shared_data"
52 #define DEBUG_RAM_REGION ".debug_mem_logs"
54 /* Maximum number of LOAD MAPPINGS supported */
55 #define NM_LOAD_MAPPINGS 20
57 #define EOT 0x04 /* End of Transmission */
58 #define SOH 0x01 /* Start of Header */
60 #define ADSP_TAG "\n[ADSP OS]"
62 #define UART_BAUD_RATE 9600
64 /* Intiialize with FIXED rate, once OS boots up DFS will set required freq */
65 #define ADSP_TO_APE_CLK_RATIO 2
66 /* 13.5 MHz, should be changed at bringup time */
67 #define APE_CLK_FIX_RATE 13500
69 * ADSP CLK = APE_CLK * ADSP_TO_APE_CLK_RATIO
71 * ADSP CLK = APE_CLK >> ADSP_TO_APE_CLK_RATIO
73 #define ADSP_CLK_FIX_RATE (APE_CLK_FIX_RATE * ADSP_TO_APE_CLK_RATIO)
75 /* total number of crashes allowed on adsp */
76 #define ALLOWED_CRASHES 1
78 #define DISABLE_MBOX2_FULL_INT 0x0
79 #define ENABLE_MBOX2_FULL_INT 0xFFFFFFFF
81 #define LOGGER_TIMEOUT 20 /* in ms */
82 #define ADSP_WFE_TIMEOUT 5000 /* in ms */
83 #define LOGGER_COMPLETE_TIMEOUT 5000 /* in ms */
85 #define MIN_ADSP_FREQ 51200000lu /* in Hz */
89 struct nvadsp_debug_log {
95 wait_queue_head_t wait_queue;
96 struct completion complete;
99 struct nvadsp_os_data {
100 void __iomem *unit_fpga_reset_reg;
101 const struct firmware *os_firmware;
102 struct platform_device *pdev;
103 struct global_sym_info *adsp_glo_sym_tbl;
104 void __iomem *misc_base;
105 struct resource **dram_region;
106 struct nvadsp_debug_log logger;
107 struct nvadsp_cnsl console;
108 struct work_struct restart_os_work;
109 int adsp_num_crashes;
110 bool adsp_os_fw_loaded;
111 struct mutex fw_load_lock;
113 struct mutex os_run_lock;
114 dma_addr_t adsp_os_addr;
116 dma_addr_t app_alloc_addr;
120 static struct nvadsp_os_data priv;
122 struct nvadsp_mappings {
128 static struct nvadsp_mappings adsp_map[NM_LOAD_MAPPINGS];
130 static struct nvadsp_mbox adsp_com_mbox;
132 static DECLARE_COMPLETION(entered_wfi);
134 static void __nvadsp_os_stop(bool);
136 #ifdef CONFIG_DEBUG_FS
137 static int adsp_logger_open(struct inode *inode, struct file *file)
139 struct nvadsp_debug_log *logger = inode->i_private;
140 struct nvadsp_os_data *os_data;
144 os_data = container_of(logger, struct nvadsp_os_data, logger);
147 * checks if os_opened decrements to zero and if returns true. If true
148 * then there has been no open.
150 if (!atomic_dec_and_test(&logger->is_opened)) {
151 atomic_inc(&logger->is_opened);
155 ret = wait_event_interruptible(logger->wait_queue,
156 os_data->adsp_os_fw_loaded);
157 if (ret == -ERESTARTSYS) /* check if interrupted */
160 /* loop till writer is initilized with SOH */
163 ret = wait_event_interruptible_timeout(logger->wait_queue,
164 memchr(logger->debug_ram_rdr, SOH,
165 logger->debug_ram_sz),
166 msecs_to_jiffies(LOGGER_TIMEOUT));
167 if (ret == -ERESTARTSYS) /* check if interrupted */
170 start = memchr(logger->debug_ram_rdr, SOH,
171 logger->debug_ram_sz);
174 /* maxdiff can be 0, therefore valid */
175 logger->ram_iter = start - logger->debug_ram_rdr;
177 file->private_data = logger;
180 /* reset to 1 so as to mention the node is free */
181 atomic_set(&logger->is_opened, 1);
187 static int adsp_logger_flush(struct file *file, fl_owner_t id)
189 struct nvadsp_debug_log *logger = file->private_data;
190 struct device *dev = logger->dev;
192 dev_dbg(dev, "%s\n", __func__);
194 /* reset to 1 so as to mention the node is free */
195 atomic_set(&logger->is_opened, 1);
199 static int adsp_logger_release(struct inode *inode, struct file *file)
204 static ssize_t adsp_logger_read(struct file *file, char __user *buf,
205 size_t count, loff_t *ppos)
207 struct nvadsp_debug_log *logger = file->private_data;
208 struct device *dev = logger->dev;
209 ssize_t ret_num_char = 1;
213 last_char = logger->debug_ram_rdr[logger->ram_iter];
215 if ((last_char != EOT) && (last_char != 0)) {
216 #if CONFIG_ADSP_DRAM_LOG_WITH_TAG
217 if ((last_char == '\n') || (last_char == '\r')) {
219 if (copy_to_user(buf, ADSP_TAG, sizeof(ADSP_TAG) - 1)) {
220 dev_err(dev, "%s failed\n", __func__);
221 ret_num_char = -EFAULT;
224 ret_num_char = sizeof(ADSP_TAG) - 1;
228 if (copy_to_user(buf, &last_char, 1)) {
229 dev_err(dev, "%s failed\n", __func__);
230 ret_num_char = -EFAULT;
235 (logger->ram_iter + 1) % logger->debug_ram_sz;
239 complete(&logger->complete);
240 ret_num_char = wait_event_interruptible_timeout(logger->wait_queue,
241 logger->debug_ram_rdr[logger->ram_iter] != EOT,
242 msecs_to_jiffies(LOGGER_TIMEOUT));
243 if (ret_num_char == -ERESTARTSYS) {
252 static const struct file_operations adsp_logger_operations = {
253 .read = adsp_logger_read,
254 .open = adsp_logger_open,
255 .release = adsp_logger_release,
256 .llseek = generic_file_llseek,
257 .flush = adsp_logger_flush,
260 static int adsp_create_debug_logger(struct dentry *adsp_debugfs_root)
262 struct nvadsp_debug_log *logger = &priv.logger;
263 struct device *dev = &priv.pdev->dev;
266 if (IS_ERR_OR_NULL(adsp_debugfs_root)) {
271 atomic_set(&logger->is_opened, 1);
272 init_waitqueue_head(&logger->wait_queue);
273 init_completion(&logger->complete);
274 if (!debugfs_create_file("adsp_logger", S_IRUGO,
275 adsp_debugfs_root, logger,
276 &adsp_logger_operations)) {
277 dev_err(dev, "unable to create adsp logger debug fs file\n");
286 bool is_adsp_dram_addr(u64 addr)
289 struct resource **dram = priv.dram_region;
291 for (i = 0; i < ADSP_MAX_DRAM_MAP; i++) {
292 if ((addr >= dram[i]->start) &&
293 (addr <= dram[i]->end)) {
300 int adsp_add_load_mappings(phys_addr_t pa, void *mapping, int len)
302 if (map_idx >= NM_LOAD_MAPPINGS)
305 adsp_map[map_idx].da = pa;
306 adsp_map[map_idx].va = mapping;
307 adsp_map[map_idx].len = len;
312 void *nvadsp_da_to_va_mappings(u64 da, int len)
317 for (i = 0; i < map_idx; i++) {
318 int offset = da - adsp_map[i].da;
320 /* try next carveout if da is too small */
324 /* try next carveout if da is too large */
325 if (offset + len > adsp_map[i].len)
328 ptr = adsp_map[i].va + offset;
333 EXPORT_SYMBOL(nvadsp_da_to_va_mappings);
335 void *nvadsp_alloc_coherent(size_t size, dma_addr_t *da, gfp_t flags)
341 pr_err("ADSP Driver is not initialized\n");
345 dev = &priv.pdev->dev;
346 va = dma_alloc_coherent(dev, size, da, flags);
348 dev_err(dev, "unable to allocate the memory for size %lu\n",
352 WARN(!is_adsp_dram_addr(*da), "bus addr %llx beyond %x\n",
357 EXPORT_SYMBOL(nvadsp_alloc_coherent);
359 void nvadsp_free_coherent(size_t size, void *va, dma_addr_t da)
364 pr_err("ADSP Driver is not initialized\n");
367 dev = &priv.pdev->dev;
368 dma_free_coherent(dev, size, va, da);
370 EXPORT_SYMBOL(nvadsp_free_coherent);
373 nvadsp_get_section(const struct firmware *fw, char *sec_name)
376 struct device *dev = &priv.pdev->dev;
377 const u8 *elf_data = fw->data;
378 struct elf32_hdr *ehdr = (struct elf32_hdr *)elf_data;
379 struct elf32_shdr *shdr;
380 const char *name_table;
382 /* look for the resource table and handle it */
383 shdr = (struct elf32_shdr *)(elf_data + ehdr->e_shoff);
384 name_table = elf_data + shdr[ehdr->e_shstrndx].sh_offset;
386 for (i = 0; i < ehdr->e_shnum; i++, shdr++)
387 if (!strcmp(name_table + shdr->sh_name, sec_name)) {
388 dev_dbg(dev, "found the section %s\n",
389 name_table + shdr->sh_name);
395 static inline void dump_global_symbol_table(void)
397 struct device *dev = &priv.pdev->dev;
398 struct global_sym_info *table = priv.adsp_glo_sym_tbl;
403 dev_err(dev, "no table not created\n");
406 num_ent = table[0].addr;
407 dev_info(dev, "total number of entries in global symbol table %d\n",
410 pr_info("NAME ADDRESS TYPE\n");
411 for (i = 1; i < num_ent; i++)
412 pr_info("%s %x %s\n", table[i].name, table[i].addr,
413 ELF32_ST_TYPE(table[i].info) == STT_FUNC ?
414 "STT_FUNC" : "STT_OBJECT");
418 create_global_symbol_table(const struct firmware *fw)
421 struct device *dev = &priv.pdev->dev;
422 struct elf32_shdr *sym_shdr = nvadsp_get_section(fw, ".symtab");
423 struct elf32_shdr *str_shdr = nvadsp_get_section(fw, ".strtab");
424 const u8 *elf_data = fw->data;
425 const char *name_table;
426 /* The first entry stores the number of entries in the array */
428 struct elf32_sym *sym;
429 struct elf32_sym *last_sym;
431 sym = (struct elf32_sym *)(elf_data + sym_shdr->sh_offset);
432 name_table = elf_data + str_shdr->sh_offset;
434 num_ent += sym_shdr->sh_size / sizeof(struct elf32_sym);
435 priv.adsp_glo_sym_tbl = devm_kzalloc(dev,
436 sizeof(struct global_sym_info) * num_ent, GFP_KERNEL);
437 if (!priv.adsp_glo_sym_tbl)
440 last_sym = sym + num_ent;
442 for (i = 1; sym < last_sym; sym++) {
443 unsigned char info = sym->st_info;
444 unsigned char type = ELF32_ST_TYPE(info);
445 if ((ELF32_ST_BIND(sym->st_info) == STB_GLOBAL) &&
446 ((type == STT_OBJECT) || (type == STT_FUNC))) {
447 char *name = priv.adsp_glo_sym_tbl[i].name;
448 strncpy(name, name_table + sym->st_name, SYM_NAME_SZ);
449 priv.adsp_glo_sym_tbl[i].addr = sym->st_value;
450 priv.adsp_glo_sym_tbl[i].info = info;
454 priv.adsp_glo_sym_tbl[0].addr = i;
458 struct global_sym_info *find_global_symbol(const char *sym_name)
460 struct device *dev = &priv.pdev->dev;
461 struct global_sym_info *table = priv.adsp_glo_sym_tbl;
465 if (unlikely(!table)) {
466 dev_err(dev, "symbol table not present\n");
469 num_ent = table[0].addr;
471 for (i = 1; i < num_ent; i++) {
472 if (!strncmp(table[i].name, sym_name, SYM_NAME_SZ))
478 static void *get_mailbox_shared_region(const struct firmware *fw)
481 struct elf32_shdr *shdr;
486 pr_err("ADSP Driver is not initialized\n");
487 return ERR_PTR(-EINVAL);
490 dev = &priv.pdev->dev;
492 shdr = nvadsp_get_section(fw, MAILBOX_REGION);
494 dev_err(dev, "section %s not found\n", MAILBOX_REGION);
495 return ERR_PTR(-EINVAL);
498 dev_dbg(dev, "the shared section is present at 0x%x\n", shdr->sh_addr);
499 addr = shdr->sh_addr;
500 size = shdr->sh_size;
501 return nvadsp_da_to_va_mappings(addr, size);
504 static void copy_io_in_l(void *to, const void *from, int sz)
507 for (i = 0; i < sz; i += 4) {
508 int val = *(int *)(from + i);
513 static int nvadsp_os_elf_load(const struct firmware *fw)
515 struct device *dev = &priv.pdev->dev;
516 struct nvadsp_drv_data *drv_data = platform_get_drvdata(priv.pdev);
517 struct elf32_hdr *ehdr;
518 struct elf32_phdr *phdr;
520 const u8 *elf_data = fw->data;
522 ehdr = (struct elf32_hdr *)elf_data;
523 phdr = (struct elf32_phdr *)(elf_data + ehdr->e_phoff);
525 /* go through the available ELF segments */
526 for (i = 0; i < ehdr->e_phnum; i++, phdr++) {
528 u32 da = phdr->p_paddr;
529 u32 memsz = phdr->p_memsz;
530 u32 filesz = phdr->p_filesz;
531 u32 offset = phdr->p_offset;
533 if (phdr->p_type != PT_LOAD)
536 dev_dbg(dev, "phdr: type %d da 0x%x memsz 0x%x filesz 0x%x\n",
537 phdr->p_type, da, memsz, filesz);
539 va = nvadsp_da_to_va_mappings(da, filesz);
541 dev_err(dev, "no va for da 0x%x filesz 0x%x\n",
547 if (filesz > memsz) {
548 dev_err(dev, "bad phdr filesz 0x%x memsz 0x%x\n",
554 if (offset + filesz > fw->size) {
555 dev_err(dev, "truncated fw: need 0x%x avail 0x%zx\n",
556 offset + filesz, fw->size);
561 /* put the segment where the remote processor expects it */
563 if (!is_adsp_dram_addr(da)) {
564 drv_data->state.evp_ptr = va;
565 memcpy(drv_data->state.evp,
566 elf_data + offset, filesz);
568 memcpy(va, elf_data + offset, filesz);
575 static int allocate_memory_for_adsp_os(void)
577 struct platform_device *pdev = priv.pdev;
578 struct device *dev = &pdev->dev;
579 #if defined(CONFIG_TEGRA_NVADSP_ON_SMMU)
588 addr = priv.adsp_os_addr;
589 size = priv.adsp_os_size;
590 #if defined(CONFIG_TEGRA_NVADSP_ON_SMMU)
591 dram_va = dma_alloc_at_coherent(dev, size, &addr, GFP_KERNEL);
593 dev_err(dev, "unable to allocate SMMU pages\n");
598 dram_va = ioremap_nocache(addr, size);
600 dev_err(dev, "remap failed for addr 0x%llx\n", addr);
605 adsp_add_load_mappings(addr, dram_va, size);
610 static void deallocate_memory_for_adsp_os(struct device *dev)
612 #if defined(CONFIG_TEGRA_NVADSP_ON_SMMU)
613 void *va = nvadsp_da_to_va_mappings(priv.adsp_os_addr,
615 dma_free_coherent(dev, priv.adsp_os_addr, va, priv.adsp_os_size);
619 int nvadsp_os_load(void)
621 struct nvadsp_shared_mem *shared_mem;
622 struct nvadsp_drv_data *drv_data;
623 const struct firmware *fw;
628 pr_err("ADSP Driver is not initialized\n");
633 mutex_lock(&priv.fw_load_lock);
634 if (priv.adsp_os_fw_loaded)
637 dev = &priv.pdev->dev;
639 drv_data = platform_get_drvdata(priv.pdev);
641 ret = request_firmware(&fw, NVADSP_FIRMWARE, dev);
643 dev_err(dev, "reqest firmware for %s failed with %d\n",
644 NVADSP_FIRMWARE, ret);
648 ret = create_global_symbol_table(fw);
650 dev_err(dev, "unable to create global symbol table\n");
651 goto release_firmware;
654 ret = allocate_memory_for_adsp_os();
656 dev_err(dev, "unable to allocate memory for adsp os\n");
657 goto release_firmware;
660 shared_mem = get_mailbox_shared_region(fw);
661 drv_data->shared_adsp_os_data = shared_mem;
662 /* set logger strcuture with required properties */
663 priv.logger.debug_ram_rdr = shared_mem->os_args.logger;
664 priv.logger.debug_ram_sz = sizeof(shared_mem->os_args.logger);
665 priv.logger.dev = dev;
667 dev_info(dev, "Loading ADSP OS firmware %s\n", NVADSP_FIRMWARE);
669 ret = nvadsp_os_elf_load(fw);
671 dev_err(dev, "failed to load %s\n", NVADSP_FIRMWARE);
672 goto deallocate_os_memory;
675 ret = dram_app_mem_init(priv.app_alloc_addr, priv.app_size);
677 dev_err(dev, "Memory allocation dynamic apps failed\n");
678 goto deallocate_os_memory;
680 priv.os_firmware = fw;
681 priv.adsp_os_fw_loaded = true;
682 wake_up(&priv.logger.wait_queue);
684 mutex_unlock(&priv.fw_load_lock);
687 deallocate_os_memory:
688 deallocate_memory_for_adsp_os(dev);
690 release_firmware(fw);
692 mutex_unlock(&priv.fw_load_lock);
695 EXPORT_SYMBOL(nvadsp_os_load);
698 * Static adsp freq to emc freq lookup table
701 * adspfreq - adsp freq in KHz
704 * > 0 - expected emc freq at this adsp freq
706 u32 adsp_to_emc_freq(u32 adspfreq)
709 * Vote on memory bus frequency based on adsp frequency
710 * cpu rate is in kHz, emc rate is in Hz
712 if (adspfreq >= 204800)
713 return 102000; /* adsp >= 204.8 MHz, emc 102 MHz */
715 return 0; /* emc min */
718 static int nvadsp_set_ape_emc_freq(struct nvadsp_drv_data *drv_data)
720 unsigned long ape_emc_freq = drv_data->ape_emc_freq * 1000; /* in Hz */
721 struct device *dev = &priv.pdev->dev;
724 #ifdef CONFIG_TEGRA_ADSP_DFS
725 /* pass adsp freq in KHz. adsp_emc_freq in Hz */
726 ape_emc_freq = adsp_to_emc_freq(drv_data->adsp_freq / 1000) * 1000;
728 dev_dbg(dev, "requested adsp cpu freq %luKHz",
729 drv_data->adsp_freq / 1000);
730 dev_dbg(dev, "ape.emc freq %luHz\n", ape_emc_freq / 1000);
732 ret = clk_set_rate(drv_data->ape_emc_clk, ape_emc_freq);
734 dev_dbg(dev, "ape.emc freq %luKHz\n",
735 clk_get_rate(drv_data->ape_emc_clk) / 1000);
739 static int nvadsp_set_ape_freq(struct nvadsp_drv_data *drv_data)
741 unsigned long ape_freq = drv_data->ape_freq * 1000; /* in Hz*/
742 struct device *dev = &priv.pdev->dev;
745 #ifdef CONFIG_TEGRA_ADSP_ACTMON
746 ape_freq = drv_data->adsp_freq / ADSP_TO_APE_CLK_RATIO;
748 dev_dbg(dev, "ape freq %luKHz", ape_freq / 1000);
750 ret = clk_set_rate(drv_data->ape_clk, ape_freq);
752 dev_dbg(dev, "ape freq %luKHz\n",
753 clk_get_rate(drv_data->ape_clk) / 1000);
757 static int set_adsp_clks_and_timer_prescalar(struct nvadsp_drv_data *drv_data)
759 struct nvadsp_shared_mem *shared_mem = drv_data->shared_adsp_os_data;
760 struct nvadsp_os_args *os_args = &shared_mem->os_args;
761 struct device *dev = &priv.pdev->dev;
762 unsigned long max_adsp_freq;
763 unsigned long adsp_freq;
768 adsp_freq = drv_data->adsp_freq * 1000; /* in Hz*/
770 max_adsp_freq = clk_round_rate(drv_data->adsp_cpu_clk,
772 max_index = max_adsp_freq / MIN_ADSP_FREQ;
773 cur_index = adsp_freq / MIN_ADSP_FREQ;
777 /* Set max adsp boot freq */
778 cur_index = max_index;
780 if (adsp_freq % MIN_ADSP_FREQ) {
781 if (cur_index >= max_index)
782 cur_index = max_index;
785 } else if (cur_index >= max_index)
786 cur_index = max_index;
789 * timer interval = (prescalar + 1) * (count + 1) / periph_freq
790 * therefore for 0 count,
791 * 1 / TIMER_CLK_HZ = (prescalar + 1) / periph_freq
792 * Hence, prescalar = periph_freq / TIMER_CLK_HZ - 1
794 os_args->timer_prescalar = cur_index - 1;
796 adsp_freq = cur_index * MIN_ADSP_FREQ;
798 ret = clk_set_rate(drv_data->adsp_cpu_clk, adsp_freq);
802 drv_data->adsp_freq = adsp_freq / 1000; /* adsp_freq in KHz*/
805 dev_dbg(dev, "adsp cpu freq %luKHz\n",
806 clk_get_rate(drv_data->adsp_cpu_clk) / 1000);
807 dev_dbg(dev, "timer prescalar %x\n", os_args->timer_prescalar);
812 static int deassert_adsp(struct nvadsp_drv_data *drv_data)
814 struct device *dev = &priv.pdev->dev;
816 if (drv_data->adsp_unit_fpga) {
817 dev_info(dev, "De-asserting ADSP UNIT-FPGA\n");
818 writel(drv_data->unit_fpga_reset[ADSP_DEASSERT],
819 priv.unit_fpga_reset_reg);
823 if (drv_data->adsp_clk) {
824 dev_dbg(dev, "deasserting adsp...\n");
825 tegra_periph_reset_deassert(drv_data->adsp_clk);
833 static int assert_adsp(struct nvadsp_drv_data *drv_data)
835 struct device *dev = &priv.pdev->dev;
837 if (drv_data->adsp_unit_fpga) {
838 if (drv_data->unit_fpga_reset[ADSP_ASSERT]) {
839 dev_info(dev, "Asserting ADSP UNIT-FPGA\n");
840 writel(drv_data->unit_fpga_reset[ADSP_ASSERT],
841 priv.unit_fpga_reset_reg);
846 if (drv_data->adsp_clk) {
847 tegra_periph_reset_assert(drv_data->adsp_clk);
855 static int nvadsp_set_boot_freqs(struct nvadsp_drv_data *drv_data)
859 /* on Unit-FPGA do not set clocks, return Sucess */
860 if (drv_data->adsp_unit_fpga)
863 if (drv_data->adsp_cpu_clk) {
864 ret = set_adsp_clks_and_timer_prescalar(drv_data);
872 if (drv_data->ape_clk) {
873 ret = nvadsp_set_ape_freq(drv_data);
878 if (drv_data->ape_emc_clk) {
879 ret = nvadsp_set_ape_emc_freq(drv_data);
888 static int __nvadsp_os_start(void)
890 struct nvadsp_drv_data *drv_data;
894 dev = &priv.pdev->dev;
895 drv_data = platform_get_drvdata(priv.pdev);
898 dev_dbg(dev, "ADSP is booting on %s\n",
899 drv_data->adsp_unit_fpga ? "UNIT-FPGA" : "SILICON");
901 assert_adsp(drv_data);
903 dev_dbg(dev, "Copying EVP...\n");
904 copy_io_in_l(drv_data->state.evp_ptr,
908 ret = nvadsp_set_boot_freqs(drv_data);
911 ret = deassert_adsp(drv_data);
915 dev_dbg(dev, "Waiting for ADSP OS to boot up...\n");
916 ret = wait_for_adsp_os_load_complete();
918 dev_err(dev, "Unable to start ADSP OS\n");
921 dev_dbg(dev, "ADSP OS boot up... Done!\n");
923 #ifdef CONFIG_TEGRA_ADSP_DFS
924 ret = adsp_dfs_core_init(priv.pdev);
926 dev_err(dev, "adsp dfs initialization failed\n");
931 #ifdef CONFIG_TEGRA_ADSP_ACTMON
932 ret = ape_actmon_init(priv.pdev);
934 dev_err(dev, "ape actmon initialization failed\n");
941 #ifdef CONFIG_TEGRA_ADSP_DFS
943 __nvadsp_os_stop(true);
948 static void dump_adsp_logs(void)
951 char buff[DUMP_BUFF] = { };
954 struct nvadsp_debug_log *logger = &priv.logger;
955 struct device *dev = &priv.pdev->dev;
956 char *ptr = logger->debug_ram_rdr;
958 dev_err(dev, "Dumping ADSP logs ........\n");
960 for (i = 0; i < logger->debug_ram_sz; i++) {
961 last_char = *(ptr + i);
962 if ((last_char != EOT) && (last_char != 0)) {
963 if ((last_char == '\n') || (last_char == '\r') ||
964 (buff_iter == DUMP_BUFF)) {
965 dev_err(dev, "[ADSP OS] %s\n", buff);
966 memset(buff, 0, sizeof(buff));
969 buff[buff_iter++] = last_char;
973 dev_err(dev, "End of ADSP log dump .....\n");
976 static void print_agic_irq_states(void)
978 struct device *dev = &priv.pdev->dev;
981 for (i = INT_AMISC_MBOX_FULL0; i <= INT_ADSP_ACTMON; i++) {
982 dev_info(dev, "irq %d is %s and %s\n", i,
983 tegra_agic_irq_is_pending(INT_ADSP_WDT) ?
984 "pending" : "not pending",
985 tegra_agic_irq_is_active(INT_ADSP_WDT) ?
986 "active" : "not active");
990 static void dump_adsp_sys(void)
994 print_agic_irq_states();
997 int nvadsp_os_start(void)
999 struct nvadsp_drv_data *drv_data;
1004 pr_err("ADSP Driver is not initialized\n");
1009 drv_data = platform_get_drvdata(priv.pdev);
1010 dev = &priv.pdev->dev;
1012 /* check if fw is loaded then start the adsp os */
1013 if (!priv.adsp_os_fw_loaded) {
1014 dev_err(dev, "Call to nvadsp_os_load not made\n");
1019 mutex_lock(&priv.os_run_lock);
1020 /* if adsp is started/running exit gracefully */
1021 if (priv.os_running)
1024 #ifdef CONFIG_PM_RUNTIME
1025 ret = pm_runtime_get_sync(&priv.pdev->dev);
1029 ret = __nvadsp_os_start();
1031 priv.os_running = drv_data->adsp_os_running = false;
1032 /* if start fails call pm suspend of adsp driver */
1033 #ifdef CONFIG_PM_RUNTIME
1034 pm_runtime_put_sync(&priv.pdev->dev);
1036 dev_err(dev, "adsp failed to boot with ret = %d\n", ret);
1041 priv.os_running = drv_data->adsp_os_running = true;
1042 drv_data->adsp_os_suspended = false;
1043 wake_up(&priv.logger.wait_queue);
1045 mutex_unlock(&priv.os_run_lock);
1049 EXPORT_SYMBOL(nvadsp_os_start);
1051 static int __nvadsp_os_suspend(void)
1053 struct device *dev = &priv.pdev->dev;
1054 struct nvadsp_drv_data *drv_data;
1055 uint16_t com_mid = ADSP_COM_MBOX_ID;
1058 drv_data = platform_get_drvdata(priv.pdev);
1060 #ifdef CONFIG_TEGRA_ADSP_ACTMON
1061 ape_actmon_exit(priv.pdev);
1064 #ifdef CONFIG_TEGRA_ADSP_DFS
1065 adsp_dfs_core_exit(priv.pdev);
1068 ret = nvadsp_mbox_open(&adsp_com_mbox, &com_mid, "adsp_com_mbox",
1071 dev_err(dev, "failed to open adsp com mbox\n");
1075 ret = nvadsp_mbox_send(&adsp_com_mbox, ADSP_OS_SUSPEND,
1076 NVADSP_MBOX_SMSG, true, UINT_MAX);
1078 dev_err(dev, "failed to send with adsp com mbox\n");
1082 dev_dbg(dev, "Waiting for ADSP OS suspend...\n");
1083 ret = wait_for_completion_interruptible_timeout(&entered_wfi,
1084 msecs_to_jiffies(ADSP_WFE_TIMEOUT));
1085 if (WARN_ON(ret <= 0)) {
1086 dev_err(dev, "Unable to suspend ADSP OS\n");
1090 dev_dbg(dev, "ADSP OS suspended!\n");
1092 ret = nvadsp_mbox_close(&adsp_com_mbox);
1094 dev_err(dev, "failed to close adsp com mbox\n");
1098 drv_data->adsp_os_suspended = true;
1100 assert_adsp(drv_data);
1102 #ifdef CONFIG_PM_RUNTIME
1103 ret = pm_runtime_put_sync(&priv.pdev->dev);
1105 dev_err(dev, "failed in pm_runtime_put_sync\n");
1113 static void __nvadsp_os_stop(bool reload)
1115 const struct firmware *fw = priv.os_firmware;
1116 struct nvadsp_drv_data *drv_data;
1120 dev = &priv.pdev->dev;
1121 drv_data = platform_get_drvdata(priv.pdev);
1123 #ifdef CONFIG_TEGRA_ADSP_ACTMON
1124 ape_actmon_exit(priv.pdev);
1127 #ifdef CONFIG_TEGRA_ADSP_DFS
1128 adsp_dfs_core_exit(priv.pdev);
1131 writel(ENABLE_MBOX2_FULL_INT, priv.misc_base + HWMBOX2_REG);
1132 err = wait_for_completion_interruptible_timeout(&entered_wfi,
1133 msecs_to_jiffies(ADSP_WFE_TIMEOUT));
1134 writel(DISABLE_MBOX2_FULL_INT, priv.misc_base + HWMBOX2_REG);
1137 * ADSP needs to be in WFI/WFE state to properly reset it.
1138 * However, when ADSPOS is getting stopped on error path,
1139 * it cannot gaurantee that ADSP is in WFI/WFE state.
1140 * Reset it in either case. On failure, whole APE reset is
1141 * required (happens on next APE power domain cycle).
1143 assert_adsp(drv_data);
1144 /* Don't reload ADSPOS if ADSP state is not WFI/WFE */
1145 if (WARN_ON(err <= 0)) {
1146 dev_err(dev, "ADSP is unable to enter wfi state\n");
1151 struct nvadsp_debug_log *logger = &priv.logger;
1153 wake_up(&logger->wait_queue);
1154 /* wait for LOGGER_TIMEOUT to complete filling the buffer */
1155 wait_for_completion_interruptible_timeout(&logger->complete,
1156 msecs_to_jiffies(LOGGER_COMPLETE_TIMEOUT));
1158 * move ram iterator to 0, since after restart the iterator
1159 * will be pointing to initial position of start.
1161 logger->debug_ram_rdr[0] = EOT;
1162 logger->ram_iter = 0;
1164 /* load a fresh copy of adsp.elf */
1165 if (nvadsp_os_elf_load(fw))
1166 dev_err(dev, "failed to reload %s\n", NVADSP_FIRMWARE);
1174 void nvadsp_os_stop(void)
1176 struct nvadsp_drv_data *drv_data;
1181 pr_err("ADSP Driver is not initialized\n");
1185 dev = &priv.pdev->dev;
1186 drv_data = platform_get_drvdata(priv.pdev);
1188 mutex_lock(&priv.os_run_lock);
1189 /* check if os is running else exit */
1190 if (!priv.os_running)
1193 __nvadsp_os_stop(true);
1195 priv.os_running = drv_data->adsp_os_running = false;
1197 #ifdef CONFIG_PM_RUNTIME
1198 err = pm_runtime_put_sync(dev);
1200 dev_err(dev, "failed in pm_runtime_put_sync\n");
1203 mutex_unlock(&priv.os_run_lock);
1205 EXPORT_SYMBOL(nvadsp_os_stop);
1207 int nvadsp_os_suspend(void)
1209 struct nvadsp_drv_data *drv_data;
1213 pr_err("ADSP Driver is not initialized\n");
1218 * No os suspend/stop on linsim as
1219 * APE can be reset only once.
1221 if (tegra_platform_is_linsim())
1224 drv_data = platform_get_drvdata(priv.pdev);
1226 mutex_lock(&priv.os_run_lock);
1227 /* check if os is running else exit */
1228 if (!priv.os_running) {
1232 ret = __nvadsp_os_suspend();
1234 priv.os_running = drv_data->adsp_os_running = false;
1236 dev_err(&priv.pdev->dev, "suspend failed with %d\n", ret);
1240 mutex_unlock(&priv.os_run_lock);
1244 EXPORT_SYMBOL(nvadsp_os_suspend);
1246 static void nvadsp_os_restart(struct work_struct *work)
1248 struct nvadsp_os_data *data =
1249 container_of(work, struct nvadsp_os_data, restart_os_work);
1250 int wdt_virq = tegra_agic_irq_get_virq(INT_ADSP_WDT);
1251 struct device *dev = &data->pdev->dev;
1253 disable_irq(wdt_virq);
1257 if (tegra_agic_irq_is_active(INT_ADSP_WDT)) {
1258 dev_info(dev, "wdt interrupt is active hence clearing\n");
1259 tegra_agic_clear_active(INT_ADSP_WDT);
1262 if (tegra_agic_irq_is_pending(INT_ADSP_WDT)) {
1263 dev_info(dev, "wdt interrupt is pending hence clearing\n");
1264 tegra_agic_clear_pending(INT_ADSP_WDT);
1267 dev_info(dev, "wdt interrupt is not pending or active...enabling\n");
1268 enable_irq(wdt_virq);
1270 data->adsp_num_crashes++;
1271 if (data->adsp_num_crashes >= ALLOWED_CRASHES) {
1272 /* making pdev NULL so that externally start is not called */
1274 dev_crit(dev, "ADSP has crashed too many times(%d)\n",
1275 data->adsp_num_crashes);
1279 if (nvadsp_os_start())
1280 dev_crit(dev, "Unable to restart ADSP OS\n");
1283 static irqreturn_t adsp_wfi_handler(int irq, void *arg)
1285 struct nvadsp_os_data *data = arg;
1286 struct device *dev = &data->pdev->dev;
1288 dev_dbg(dev, "%s\n", __func__);
1289 complete(&entered_wfi);
1294 static irqreturn_t adsp_wdt_handler(int irq, void *arg)
1296 struct nvadsp_os_data *data = arg;
1297 struct nvadsp_drv_data *drv_data;
1298 struct device *dev = &data->pdev->dev;
1300 drv_data = platform_get_drvdata(data->pdev);
1301 if (!drv_data->adsp_unit_fpga) {
1302 dev_crit(dev, "ADSP OS Hanged or Crashed! Restarting...\n");
1303 schedule_work(&data->restart_os_work);
1305 dev_crit(dev, "ADSP OS Hanged or Crashed!\n");
1310 int __init nvadsp_os_probe(struct platform_device *pdev)
1312 struct nvadsp_drv_data *drv_data = platform_get_drvdata(pdev);
1313 int wdt_virq = tegra_agic_irq_get_virq(INT_ADSP_WDT);
1314 int wfi_virq = tegra_agic_irq_get_virq(INT_WFI);
1315 struct device *dev = &pdev->dev;
1318 priv.unit_fpga_reset_reg = drv_data->base_regs[UNIT_FPGA_RST];
1319 priv.misc_base = drv_data->base_regs[AMISC];
1320 priv.dram_region = drv_data->dram_region;
1322 priv.adsp_os_addr = drv_data->adsp_mem[ADSP_OS_ADDR];
1323 priv.adsp_os_size = drv_data->adsp_mem[ADSP_OS_SIZE];
1324 priv.app_alloc_addr = drv_data->adsp_mem[ADSP_APP_ADDR];
1325 priv.app_size = drv_data->adsp_mem[ADSP_APP_SIZE];
1327 ret = devm_request_irq(dev, wdt_virq, adsp_wdt_handler,
1328 IRQF_TRIGGER_RISING, "adsp watchdog", &priv);
1330 dev_err(dev, "failed to get adsp watchdog interrupt\n");
1334 ret = devm_request_irq(dev, wfi_virq, adsp_wfi_handler,
1335 IRQF_TRIGGER_RISING, "adsp wfi", &priv);
1337 dev_err(dev, "cannot request for wfi interrupt\n");
1341 ret = tegra_agic_route_interrupt(INT_AMISC_MBOX_FULL2,
1344 dev_err(dev, "failed to route fiq interrupt\n");
1348 writel(DISABLE_MBOX2_FULL_INT, priv.misc_base + HWMBOX2_REG);
1350 INIT_WORK(&priv.restart_os_work, nvadsp_os_restart);
1351 mutex_init(&priv.fw_load_lock);
1352 mutex_init(&priv.os_run_lock);
1355 #ifdef CONFIG_DEBUG_FS
1356 priv.logger.dev = &pdev->dev;
1357 if (adsp_create_debug_logger(drv_data->adsp_debugfs_root))
1358 dev_err(dev, "unable to create adsp debug logger file\n");
1359 #ifdef CONFIG_TEGRA_ADSP_CONSOLE
1360 priv.console.dev = &pdev->dev;
1361 if (adsp_create_cnsl(drv_data->adsp_debugfs_root, &priv.console))
1362 dev_err(dev, "unable to create adsp console file\n");
1363 #endif /* CONFIG_TEGRA_ADSP_CONSOLE */
1364 #endif /* CONFIG_DEBUG_FS */