2 * arch/arm/mach-tegra/board-ardbeg-sensors.c
4 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 #include <linux/i2c.h>
17 #include <linux/gpio.h>
18 #include <linux/mpu.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/nct1008.h>
22 #include <linux/pid_thermal_gov.h>
23 #include <linux/tegra-fuse.h>
24 #include <linux/of_platform.h>
26 #include <mach/pinmux-t12.h>
27 #include <mach/pinmux.h>
28 #include <mach/io_dpd.h>
29 #include <media/camera.h>
30 #include <media/ar0330.h>
31 #include <media/ar0261.h>
32 #include <media/imx135.h>
33 #include <media/imx179.h>
34 #include <media/dw9718.h>
35 #include <media/as364x.h>
36 #include <media/ov5693.h>
37 #include <media/ov7695.h>
38 #include <media/mt9m114.h>
39 #include <media/ad5823.h>
40 #include <media/max77387.h>
42 #include <linux/platform_device.h>
43 #include <media/soc_camera.h>
44 #include <media/soc_camera_platform.h>
45 #include <media/tegra_v4l2_camera.h>
46 #include <linux/generic_adc_thermal.h>
48 #include "cpu-tegra.h"
51 #include "board-common.h"
52 #include "board-ardbeg.h"
53 #include "tegra-board-id.h"
55 #if defined(ARCH_TEGRA_12x_SOC)
56 static struct i2c_board_info ardbeg_i2c_board_info_cm32181[] = {
58 I2C_BOARD_INFO("cm32181", 0x48),
63 /* MPU board file definition */
64 static struct mpu_platform_data mpu9250_gyro_data = {
67 /* Located in board_[platformname].h */
68 .orientation = MPU_GYRO_ORIENTATION,
69 .sec_slave_type = SECONDARY_SLAVE_TYPE_NONE,
70 .key = {0x4E, 0xCC, 0x7E, 0xEB, 0xF6, 0x1E, 0x35, 0x22,
71 0x00, 0x34, 0x0D, 0x65, 0x32, 0xE9, 0x94, 0x89},
74 static struct mpu_platform_data mpu9250_gyro_data_e1762 = {
77 /* Located in board_[platformname].h */
78 .orientation = MPU_GYRO_ORIENTATION_E1762,
79 .sec_slave_type = SECONDARY_SLAVE_TYPE_NONE,
80 .key = {0x4E, 0xCC, 0x7E, 0xEB, 0xF6, 0x1E, 0x35, 0x22,
81 0x00, 0x34, 0x0D, 0x65, 0x32, 0xE9, 0x94, 0x89},
84 static struct mpu_platform_data mpu_compass_data = {
85 .orientation = MPU_COMPASS_ORIENTATION,
86 .config = NVI_CONFIG_BOOT_MPU,
89 static struct mpu_platform_data mpu_bmp_pdata = {
90 .config = NVI_CONFIG_BOOT_MPU,
93 static struct i2c_board_info __initdata inv_mpu9250_i2c0_board_info[] = {
95 I2C_BOARD_INFO(MPU_GYRO_NAME, MPU_GYRO_ADDR),
96 .platform_data = &mpu9250_gyro_data,
99 /* The actual BMP180 address is 0x77 but because this conflicts
100 * with another device, this address is hacked so Linux will
101 * call the driver. The conflict is technically okay since the
102 * BMP180 is behind the MPU. Also, the BMP180 driver uses a
103 * hard-coded address of 0x77 since it can't be changed anyway.
105 I2C_BOARD_INFO(MPU_BMP_NAME, MPU_BMP_ADDR),
106 .platform_data = &mpu_bmp_pdata,
109 I2C_BOARD_INFO(MPU_COMPASS_NAME, MPU_COMPASS_ADDR),
110 .platform_data = &mpu_compass_data,
114 static void mpuirq_init(void)
117 unsigned gyro_irq_gpio = MPU_GYRO_IRQ_GPIO;
118 unsigned gyro_bus_num = MPU_GYRO_BUS_NUM;
119 char *gyro_name = MPU_GYRO_NAME;
120 struct board_info board_info;
122 pr_info("*** MPU START *** mpuirq_init...\n");
124 tegra_get_board_info(&board_info);
126 ret = gpio_request(gyro_irq_gpio, gyro_name);
128 pr_err("%s: gpio_request failed %d\n", __func__, ret);
132 ret = gpio_direction_input(gyro_irq_gpio);
134 pr_err("%s: gpio_direction_input failed %d\n", __func__, ret);
135 gpio_free(gyro_irq_gpio);
138 pr_info("*** MPU END *** mpuirq_init...\n");
140 /* TN8 with diferent Compass address from ardbeg */
141 if (of_machine_is_compatible("nvidia,tn8"))
142 inv_mpu9250_i2c0_board_info[2].addr = MPU_COMPASS_ADDR_TN8;
144 if (board_info.board_id == BOARD_E1762)
145 inv_mpu9250_i2c0_board_info[0].platform_data =
146 &mpu9250_gyro_data_e1762;
147 inv_mpu9250_i2c0_board_info[0].irq = gpio_to_irq(MPU_GYRO_IRQ_GPIO);
148 i2c_register_board_info(gyro_bus_num, inv_mpu9250_i2c0_board_info,
149 ARRAY_SIZE(inv_mpu9250_i2c0_board_info));
153 * Soc Camera platform driver for testing
155 #if IS_ENABLED(CONFIG_SOC_CAMERA_PLATFORM)
156 static int ardbeg_soc_camera_add(struct soc_camera_device *icd);
157 static void ardbeg_soc_camera_del(struct soc_camera_device *icd);
159 static int ardbeg_soc_camera_set_capture(struct soc_camera_platform_info *info,
162 /* TODO: probably add clk opertaion here */
163 return 0; /* camera sensor always enabled */
166 static struct soc_camera_platform_info ardbeg_soc_camera_info = {
167 .format_name = "RGB4",
170 .code = V4L2_MBUS_FMT_RGBA8888_4X8_LE,
171 .colorspace = V4L2_COLORSPACE_SRGB,
172 .field = V4L2_FIELD_NONE,
176 .set_capture = ardbeg_soc_camera_set_capture,
179 static struct tegra_camera_platform_data ardbeg_camera_platform_data = {
182 .port = TEGRA_CAMERA_PORT_CSI_A,
187 static struct soc_camera_link ardbeg_soc_camera_link = {
188 .bus_id = 1, /* This must match the .id of tegra_vi01_device */
189 .add_device = ardbeg_soc_camera_add,
190 .del_device = ardbeg_soc_camera_del,
191 .module_name = "soc_camera_platform",
192 .priv = &ardbeg_camera_platform_data,
193 .dev_priv = &ardbeg_soc_camera_info,
196 static struct platform_device *ardbeg_pdev;
198 static void ardbeg_soc_camera_release(struct device *dev)
200 soc_camera_platform_release(&ardbeg_pdev);
203 static int ardbeg_soc_camera_add(struct soc_camera_device *icd)
205 return soc_camera_platform_add(icd, &ardbeg_pdev,
206 &ardbeg_soc_camera_link,
207 ardbeg_soc_camera_release, 0);
210 static void ardbeg_soc_camera_del(struct soc_camera_device *icd)
212 soc_camera_platform_del(icd, ardbeg_pdev, &ardbeg_soc_camera_link);
215 static struct platform_device ardbeg_soc_camera_device = {
216 .name = "soc-camera-pdrv",
219 .platform_data = &ardbeg_soc_camera_link,
224 #if IS_ENABLED(CONFIG_SOC_CAMERA_IMX135)
225 static int ardbeg_imx135_power(struct device *dev, int enable)
230 struct imx135_platform_data ardbeg_imx135_data;
232 static struct i2c_board_info ardbeg_imx135_camera_i2c_device = {
233 I2C_BOARD_INFO("imx135_v4l2", 0x10),
234 .platform_data = &ardbeg_imx135_data,
237 static struct tegra_camera_platform_data ardbeg_imx135_camera_platform_data = {
240 .port = TEGRA_CAMERA_PORT_CSI_A,
245 static struct soc_camera_link imx135_iclink = {
246 .bus_id = 0, /* This must match the .id of tegra_vi01_device */
247 .board_info = &ardbeg_imx135_camera_i2c_device,
248 .module_name = "imx135_v4l2",
250 .power = ardbeg_imx135_power,
251 .priv = &ardbeg_imx135_camera_platform_data,
254 static struct platform_device ardbeg_imx135_soc_camera_device = {
255 .name = "soc-camera-pdrv",
258 .platform_data = &imx135_iclink,
263 static struct regulator *ardbeg_vcmvdd;
265 static int ardbeg_get_extra_regulators(void)
267 if (!ardbeg_vcmvdd) {
268 ardbeg_vcmvdd = regulator_get(NULL, "avdd_af1_cam");
269 if (WARN_ON(IS_ERR(ardbeg_vcmvdd))) {
270 pr_err("%s: can't get regulator avdd_af1_cam: %ld\n",
271 __func__, PTR_ERR(ardbeg_vcmvdd));
272 regulator_put(ardbeg_vcmvdd);
273 ardbeg_vcmvdd = NULL;
281 static struct tegra_io_dpd csia_io = {
283 .io_dpd_reg_index = 0,
287 static struct tegra_io_dpd csib_io = {
289 .io_dpd_reg_index = 0,
293 static struct tegra_io_dpd csie_io = {
295 .io_dpd_reg_index = 1,
299 static int ardbeg_ar0330_front_power_on(struct ar0330_power_rail *pw)
303 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd)))
306 /* disable CSIE IOs DPD mode to turn on front camera for ardbeg */
307 tegra_io_dpd_disable(&csie_io);
309 gpio_set_value(CAM2_PWDN, 0);
311 err = regulator_enable(pw->iovdd);
313 goto ar0330_front_iovdd_fail;
315 usleep_range(1000, 1100);
316 err = regulator_enable(pw->avdd);
318 goto ar0330_front_avdd_fail;
321 gpio_set_value(CAM2_PWDN, 1);
324 ar0330_front_avdd_fail:
325 regulator_disable(pw->iovdd);
327 ar0330_front_iovdd_fail:
328 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
329 tegra_io_dpd_enable(&csie_io);
330 pr_err("%s failed.\n", __func__);
334 static int ardbeg_ar0330_front_power_off(struct ar0330_power_rail *pw)
336 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd))) {
337 /* put CSIE IOs into DPD mode to
338 * save additional power for ardbeg
340 tegra_io_dpd_enable(&csie_io);
344 gpio_set_value(CAM2_PWDN, 0);
348 regulator_disable(pw->iovdd);
349 regulator_disable(pw->avdd);
350 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
351 tegra_io_dpd_enable(&csie_io);
355 struct ar0330_platform_data ardbeg_ar0330_front_data = {
356 .power_on = ardbeg_ar0330_front_power_on,
357 .power_off = ardbeg_ar0330_front_power_off,
358 .dev_name = "ar0330.1",
359 .mclk_name = "mclk2",
362 static int ardbeg_ar0330_power_on(struct ar0330_power_rail *pw)
366 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd)))
369 /* disable CSIE IOs DPD mode to turn on front camera for ardbeg */
370 tegra_io_dpd_disable(&csia_io);
371 tegra_io_dpd_disable(&csib_io);
373 gpio_set_value(CAM1_PWDN, 0);
375 err = regulator_enable(pw->iovdd);
377 goto ar0330_iovdd_fail;
379 usleep_range(1000, 1100);
380 err = regulator_enable(pw->avdd);
382 goto ar0330_avdd_fail;
385 gpio_set_value(CAM1_PWDN, 1);
389 regulator_disable(pw->iovdd);
392 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
393 tegra_io_dpd_enable(&csia_io);
394 tegra_io_dpd_enable(&csib_io);
395 pr_err("%s failed.\n", __func__);
399 static int ardbeg_ar0330_power_off(struct ar0330_power_rail *pw)
401 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd))) {
402 /* put CSIE IOs into DPD mode to
403 * save additional power for ardbeg
405 tegra_io_dpd_enable(&csia_io);
406 tegra_io_dpd_enable(&csib_io);
410 gpio_set_value(CAM1_PWDN, 0);
414 regulator_disable(pw->iovdd);
415 regulator_disable(pw->avdd);
416 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
417 tegra_io_dpd_enable(&csia_io);
418 tegra_io_dpd_enable(&csib_io);
422 struct ar0330_platform_data ardbeg_ar0330_data = {
423 .power_on = ardbeg_ar0330_power_on,
424 .power_off = ardbeg_ar0330_power_off,
425 .dev_name = "ar0330",
428 static int ardbeg_ar0261_power_on(struct ar0261_power_rail *pw)
432 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd || !pw->dvdd)))
435 /* disable CSIE IOs DPD mode to turn on front camera for ardbeg */
436 tegra_io_dpd_disable(&csie_io);
438 if (ardbeg_get_extra_regulators())
439 goto ardbeg_ar0261_poweron_fail;
441 gpio_set_value(CAM_RSTN, 0);
442 gpio_set_value(CAM_AF_PWDN, 1);
445 err = regulator_enable(ardbeg_vcmvdd);
447 goto ar0261_vcm_fail;
449 err = regulator_enable(pw->dvdd);
451 goto ar0261_dvdd_fail;
453 err = regulator_enable(pw->avdd);
455 goto ar0261_avdd_fail;
457 err = regulator_enable(pw->iovdd);
459 goto ar0261_iovdd_fail;
462 gpio_set_value(CAM2_PWDN, 1);
464 gpio_set_value(CAM_RSTN, 1);
468 regulator_disable(pw->dvdd);
471 regulator_disable(pw->avdd);
474 regulator_disable(ardbeg_vcmvdd);
477 pr_err("%s vcmvdd failed.\n", __func__);
480 ardbeg_ar0261_poweron_fail:
481 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
482 tegra_io_dpd_enable(&csie_io);
483 pr_err("%s failed.\n", __func__);
487 static int ardbeg_ar0261_power_off(struct ar0261_power_rail *pw)
489 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd || !pw->dvdd ||
491 /* put CSIE IOs into DPD mode to
492 * save additional power for ardbeg
494 tegra_io_dpd_enable(&csie_io);
498 gpio_set_value(CAM_RSTN, 0);
502 regulator_disable(pw->iovdd);
503 regulator_disable(pw->dvdd);
504 regulator_disable(pw->avdd);
505 regulator_disable(ardbeg_vcmvdd);
506 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
507 tegra_io_dpd_enable(&csie_io);
511 struct ar0261_platform_data ardbeg_ar0261_data = {
512 .power_on = ardbeg_ar0261_power_on,
513 .power_off = ardbeg_ar0261_power_off,
514 .mclk_name = "mclk2",
517 static int ardbeg_imx135_get_extra_regulators(struct imx135_power_rail *pw)
520 pw->ext_reg1 = regulator_get(NULL, "imx135_reg1");
521 if (WARN_ON(IS_ERR(pw->ext_reg1))) {
522 pr_err("%s: can't get regulator imx135_reg1: %ld\n",
523 __func__, PTR_ERR(pw->ext_reg1));
530 pw->ext_reg2 = regulator_get(NULL, "imx135_reg2");
531 if (WARN_ON(IS_ERR(pw->ext_reg2))) {
532 pr_err("%s: can't get regulator imx135_reg2: %ld\n",
533 __func__, PTR_ERR(pw->ext_reg2));
542 static int ardbeg_imx135_power_on(struct imx135_power_rail *pw)
546 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd)))
549 /* disable CSIA/B IOs DPD mode to turn on camera for ardbeg */
550 tegra_io_dpd_disable(&csia_io);
551 tegra_io_dpd_disable(&csib_io);
553 if (ardbeg_imx135_get_extra_regulators(pw))
554 goto imx135_poweron_fail;
556 err = regulator_enable(pw->ext_reg1);
558 goto imx135_ext_reg1_fail;
560 err = regulator_enable(pw->ext_reg2);
562 goto imx135_ext_reg2_fail;
565 gpio_set_value(CAM_AF_PWDN, 1);
566 gpio_set_value(CAM1_PWDN, 0);
567 usleep_range(10, 20);
569 err = regulator_enable(pw->avdd);
571 goto imx135_avdd_fail;
573 err = regulator_enable(pw->iovdd);
575 goto imx135_iovdd_fail;
578 gpio_set_value(CAM1_PWDN, 1);
580 usleep_range(300, 310);
586 regulator_disable(pw->avdd);
590 regulator_disable(pw->ext_reg2);
592 imx135_ext_reg2_fail:
594 regulator_disable(pw->ext_reg1);
595 gpio_set_value(CAM_AF_PWDN, 0);
597 imx135_ext_reg1_fail:
599 tegra_io_dpd_enable(&csia_io);
600 tegra_io_dpd_enable(&csib_io);
601 pr_err("%s failed.\n", __func__);
605 static int ardbeg_imx135_power_off(struct imx135_power_rail *pw)
607 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd))) {
608 tegra_io_dpd_enable(&csia_io);
609 tegra_io_dpd_enable(&csib_io);
613 regulator_disable(pw->iovdd);
614 regulator_disable(pw->avdd);
616 regulator_disable(pw->ext_reg1);
617 regulator_disable(pw->ext_reg2);
619 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
620 tegra_io_dpd_enable(&csia_io);
621 tegra_io_dpd_enable(&csib_io);
625 static int ardbeg_imx179_power_on(struct imx179_power_rail *pw)
629 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd)))
632 /* disable CSIA/B IOs DPD mode to turn on camera for ardbeg */
633 tegra_io_dpd_disable(&csia_io);
634 tegra_io_dpd_disable(&csib_io);
636 gpio_set_value(CAM_AF_PWDN, 1);
637 gpio_set_value(CAM_RSTN, 0);
638 gpio_set_value(CAM1_PWDN, 0);
639 usleep_range(10, 20);
641 err = regulator_enable(pw->avdd);
643 goto imx179_avdd_fail;
645 err = regulator_enable(pw->iovdd);
647 goto imx179_iovdd_fail;
649 err = regulator_enable(pw->dvdd);
651 goto imx179_dvdd_fail;
654 gpio_set_value(CAM_RSTN, 1);
656 usleep_range(300, 310);
662 regulator_disable(pw->iovdd);
665 regulator_disable(pw->avdd);
668 tegra_io_dpd_enable(&csia_io);
669 tegra_io_dpd_enable(&csib_io);
670 pr_err("%s failed.\n", __func__);
674 static int ardbeg_imx179_power_off(struct imx179_power_rail *pw)
676 if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd))) {
677 tegra_io_dpd_enable(&csia_io);
678 tegra_io_dpd_enable(&csib_io);
682 regulator_disable(pw->dvdd);
683 regulator_disable(pw->iovdd);
684 regulator_disable(pw->avdd);
686 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
687 tegra_io_dpd_enable(&csia_io);
688 tegra_io_dpd_enable(&csib_io);
692 struct imx135_platform_data ardbeg_imx135_data = {
701 .power_on = ardbeg_imx135_power_on,
702 .power_off = ardbeg_imx135_power_off,
705 struct imx179_platform_data ardbeg_imx179_data = {
713 .power_on = ardbeg_imx179_power_on,
714 .power_off = ardbeg_imx179_power_off,
717 static int ardbeg_dw9718_power_on(struct dw9718_power_rail *pw)
720 pr_info("%s\n", __func__);
722 if (unlikely(!pw || !pw->vdd || !pw->vdd_i2c || !pw->vana))
725 err = regulator_enable(pw->vdd);
727 goto dw9718_vdd_fail;
729 err = regulator_enable(pw->vdd_i2c);
731 goto dw9718_i2c_fail;
733 err = regulator_enable(pw->vana);
735 goto dw9718_ana_fail;
737 usleep_range(1000, 1020);
739 /* return 1 to skip the in-driver power_on sequence */
740 pr_debug("%s --\n", __func__);
744 regulator_disable(pw->vdd_i2c);
747 regulator_disable(pw->vdd);
750 pr_err("%s FAILED\n", __func__);
754 static int ardbeg_dw9718_power_off(struct dw9718_power_rail *pw)
756 pr_info("%s\n", __func__);
758 if (unlikely(!pw || !pw->vdd || !pw->vdd_i2c || !pw->vana))
761 regulator_disable(pw->vdd);
762 regulator_disable(pw->vdd_i2c);
763 regulator_disable(pw->vana);
768 static u16 dw9718_devid;
769 static int ardbeg_dw9718_detect(void *buf, size_t size)
771 dw9718_devid = 0x9718;
775 static struct nvc_focus_cap dw9718_cap = {
777 .slew_rate = 0x3A200C,
779 .focus_infinity = 200,
783 static struct dw9718_platform_data ardbeg_dw9718_data = {
784 .cfg = NVC_CFG_NODEV,
787 .dev_name = "focuser",
789 .power_on = ardbeg_dw9718_power_on,
790 .power_off = ardbeg_dw9718_power_off,
791 .detect = ardbeg_dw9718_detect,
794 static struct as364x_platform_data ardbeg_as3648_data = {
797 .max_total_current_mA = 1000,
798 .max_peak_current_mA = 600,
799 .max_torch_current_mA = 600,
800 .vin_low_v_run_mV = 3070,
804 .mask = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0),
805 .values = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0)
809 .gpio_strobe = CAM_FLASH_STROBE,
812 static int ardbeg_ov7695_power_on(struct ov7695_power_rail *pw)
816 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd)))
819 /* disable CSIE IOs DPD mode to turn on front camera for ardbeg */
820 tegra_io_dpd_disable(&csie_io);
822 gpio_set_value(CAM2_PWDN, 0);
823 usleep_range(1000, 1020);
825 err = regulator_enable(pw->avdd);
827 goto ov7695_avdd_fail;
828 usleep_range(300, 320);
830 err = regulator_enable(pw->iovdd);
832 goto ov7695_iovdd_fail;
833 usleep_range(1000, 1020);
835 gpio_set_value(CAM2_PWDN, 1);
836 usleep_range(1000, 1020);
841 regulator_disable(pw->avdd);
844 gpio_set_value(CAM_RSTN, 0);
845 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
846 tegra_io_dpd_enable(&csie_io);
850 static int ardbeg_ov7695_power_off(struct ov7695_power_rail *pw)
852 if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd))) {
853 /* put CSIE IOs into DPD mode to
854 * save additional power for ardbeg
856 tegra_io_dpd_enable(&csie_io);
859 usleep_range(100, 120);
861 gpio_set_value(CAM2_PWDN, 0);
862 usleep_range(100, 120);
864 regulator_disable(pw->iovdd);
865 usleep_range(100, 120);
867 regulator_disable(pw->avdd);
869 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
870 tegra_io_dpd_enable(&csie_io);
874 struct ov7695_platform_data ardbeg_ov7695_pdata = {
875 .power_on = ardbeg_ov7695_power_on,
876 .power_off = ardbeg_ov7695_power_off,
877 .mclk_name = "mclk2",
880 static int ardbeg_mt9m114_power_on(struct mt9m114_power_rail *pw)
883 if (unlikely(!pw || !pw->avdd || !pw->iovdd))
886 /* disable CSIE IOs DPD mode to turn on front camera for ardbeg */
887 tegra_io_dpd_disable(&csie_io);
889 gpio_set_value(CAM_RSTN, 0);
890 gpio_set_value(CAM2_PWDN, 1);
891 usleep_range(1000, 1020);
893 err = regulator_enable(pw->iovdd);
895 goto mt9m114_iovdd_fail;
897 err = regulator_enable(pw->avdd);
899 goto mt9m114_avdd_fail;
901 usleep_range(1000, 1020);
902 gpio_set_value(CAM_RSTN, 1);
903 gpio_set_value(CAM2_PWDN, 0);
904 usleep_range(1000, 1020);
906 /* return 1 to skip the in-driver power_on swquence */
910 regulator_disable(pw->iovdd);
913 gpio_set_value(CAM_RSTN, 0);
914 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
915 tegra_io_dpd_enable(&csie_io);
919 static int ardbeg_mt9m114_power_off(struct mt9m114_power_rail *pw)
921 if (unlikely(!pw || !pw->avdd || !pw->iovdd)) {
922 /* put CSIE IOs into DPD mode to
923 * save additional power for ardbeg
925 tegra_io_dpd_enable(&csie_io);
929 usleep_range(100, 120);
930 gpio_set_value(CAM_RSTN, 0);
931 usleep_range(100, 120);
932 regulator_disable(pw->avdd);
933 usleep_range(100, 120);
934 regulator_disable(pw->iovdd);
936 /* put CSIE IOs into DPD mode to save additional power for ardbeg */
937 tegra_io_dpd_enable(&csie_io);
941 struct mt9m114_platform_data ardbeg_mt9m114_pdata = {
942 .power_on = ardbeg_mt9m114_power_on,
943 .power_off = ardbeg_mt9m114_power_off,
944 .mclk_name = "mclk2",
948 static int ardbeg_ov5693_power_on(struct ov5693_power_rail *pw)
952 if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd)))
955 /* disable CSIA/B IOs DPD mode to turn on camera for ardbeg */
956 tegra_io_dpd_disable(&csia_io);
957 tegra_io_dpd_disable(&csib_io);
959 if (ardbeg_get_extra_regulators())
960 goto ov5693_poweron_fail;
962 gpio_set_value(CAM1_PWDN, 0);
963 usleep_range(10, 20);
965 err = regulator_enable(pw->avdd);
967 goto ov5693_avdd_fail;
969 err = regulator_enable(pw->dovdd);
971 goto ov5693_iovdd_fail;
974 gpio_set_value(CAM1_PWDN, 1);
976 err = regulator_enable(ardbeg_vcmvdd);
978 goto ov5693_vcmvdd_fail;
980 usleep_range(1000, 1110);
985 regulator_disable(pw->dovdd);
988 regulator_disable(pw->avdd);
991 gpio_set_value(CAM1_PWDN, 0);
994 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
995 tegra_io_dpd_enable(&csia_io);
996 tegra_io_dpd_enable(&csib_io);
997 pr_err("%s FAILED\n", __func__);
1001 static int ardbeg_ov5693_power_off(struct ov5693_power_rail *pw)
1003 if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd))) {
1004 /* put CSIA/B IOs into DPD mode to
1005 * save additional power for ardbeg
1007 tegra_io_dpd_enable(&csia_io);
1008 tegra_io_dpd_enable(&csib_io);
1012 usleep_range(21, 25);
1013 gpio_set_value(CAM1_PWDN, 0);
1016 regulator_disable(ardbeg_vcmvdd);
1017 regulator_disable(pw->dovdd);
1018 regulator_disable(pw->avdd);
1020 /* put CSIA/B IOs into DPD mode to save additional power for ardbeg */
1021 tegra_io_dpd_enable(&csia_io);
1022 tegra_io_dpd_enable(&csib_io);
1026 static struct nvc_gpio_pdata ov5693_gpio_pdata[] = {
1027 { OV5693_GPIO_TYPE_PWRDN, CAM1_PWDN, true, 0, },
1030 #define NV_GUID(a, b, c, d, e, f, g, h) \
1031 ((u64) ((((a)&0xffULL) << 56ULL) | (((b)&0xffULL) << 48ULL) | \
1032 (((c)&0xffULL) << 40ULL) | (((d)&0xffULL) << 32ULL) | \
1033 (((e)&0xffULL) << 24ULL) | (((f)&0xffULL) << 16ULL) | \
1034 (((g)&0xffULL) << 8ULL) | (((h)&0xffULL))))
1036 static struct nvc_imager_cap ov5693_cap = {
1037 .identifier = "OV5693",
1038 .sensor_nvc_interface = 3,
1039 .pixel_types[0] = 0x101,
1042 .initial_clock_rate_khz = 6000,
1043 .clock_profiles[0] = {
1044 .external_clock_khz = 24000,
1045 .clock_multiplier = 8000000, /* value * 1000000 */
1047 .clock_profiles[1] = {
1048 .external_clock_khz = 0,
1049 .clock_multiplier = 0,
1056 .virtual_channel_id = 0,
1057 .discontinuous_clk_mode = 1,
1058 .cil_threshold_settle = 0,
1059 .min_blank_time_width = 16,
1060 .min_blank_time_height = 16,
1061 .preferred_mode_index = 0,
1063 NV_GUID('f', '_', 'A', 'D', '5', '8', '2', '3'),
1065 NV_GUID('l', '_', 'N', 'V', 'C', 'A', 'M', '0'),
1066 .cap_version = NVC_IMAGER_CAPABILITIES_VERSION2,
1067 .flash_control_enabled = 0,
1068 .adjustable_flash_timing = 0,
1073 static struct ov5693_platform_data ardbeg_ov5693_pdata = {
1074 .gpio_count = ARRAY_SIZE(ov5693_gpio_pdata),
1075 .gpio = ov5693_gpio_pdata,
1076 .power_on = ardbeg_ov5693_power_on,
1077 .power_off = ardbeg_ov5693_power_off,
1078 .dev_name = "ov5693",
1080 .mclk_name = "mclk",
1082 .avdd = "avdd_ov5693",
1089 static int ardbeg_ov5693_front_power_on(struct ov5693_power_rail *pw)
1093 if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd)))
1096 if (ardbeg_get_extra_regulators())
1097 goto ov5693_front_poweron_fail;
1099 gpio_set_value(CAM2_PWDN, 0);
1100 gpio_set_value(CAM_RSTN, 0);
1101 usleep_range(10, 20);
1103 err = regulator_enable(pw->avdd);
1105 goto ov5693_front_avdd_fail;
1107 err = regulator_enable(pw->dovdd);
1109 goto ov5693_front_iovdd_fail;
1112 gpio_set_value(CAM2_PWDN, 1);
1113 gpio_set_value(CAM_RSTN, 1);
1115 err = regulator_enable(ardbeg_vcmvdd);
1117 goto ov5693_front_vcmvdd_fail;
1119 usleep_range(1000, 1110);
1123 ov5693_front_vcmvdd_fail:
1124 regulator_disable(pw->dovdd);
1126 ov5693_front_iovdd_fail:
1127 regulator_disable(pw->avdd);
1129 ov5693_front_avdd_fail:
1130 gpio_set_value(CAM2_PWDN, 0);
1131 gpio_set_value(CAM_RSTN, 0);
1133 ov5693_front_poweron_fail:
1134 pr_err("%s FAILED\n", __func__);
1138 static int ardbeg_ov5693_front_power_off(struct ov5693_power_rail *pw)
1140 if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd))) {
1144 usleep_range(21, 25);
1145 gpio_set_value(CAM2_PWDN, 0);
1146 gpio_set_value(CAM_RSTN, 0);
1149 regulator_disable(ardbeg_vcmvdd);
1150 regulator_disable(pw->dovdd);
1151 regulator_disable(pw->avdd);
1156 static struct nvc_gpio_pdata ov5693_front_gpio_pdata[] = {
1157 { OV5693_GPIO_TYPE_PWRDN, CAM2_PWDN, true, 0, },
1158 { OV5693_GPIO_TYPE_PWRDN, CAM_RSTN, true, 0, },
1161 static struct nvc_imager_cap ov5693_front_cap = {
1162 .identifier = "OV5693.1",
1163 .sensor_nvc_interface = 4,
1164 .pixel_types[0] = 0x101,
1167 .initial_clock_rate_khz = 6000,
1168 .clock_profiles[0] = {
1169 .external_clock_khz = 24000,
1170 .clock_multiplier = 8000000, /* value * 1000000 */
1172 .clock_profiles[1] = {
1173 .external_clock_khz = 0,
1174 .clock_multiplier = 0,
1181 .virtual_channel_id = 0,
1182 .discontinuous_clk_mode = 1,
1183 .cil_threshold_settle = 0,
1184 .min_blank_time_width = 16,
1185 .min_blank_time_height = 16,
1186 .preferred_mode_index = 0,
1189 .cap_version = NVC_IMAGER_CAPABILITIES_VERSION2,
1190 .flash_control_enabled = 0,
1191 .adjustable_flash_timing = 0,
1195 static struct ov5693_platform_data ardbeg_ov5693_front_pdata = {
1196 .gpio_count = ARRAY_SIZE(ov5693_front_gpio_pdata),
1197 .gpio = ov5693_front_gpio_pdata,
1198 .power_on = ardbeg_ov5693_front_power_on,
1199 .power_off = ardbeg_ov5693_front_power_off,
1200 .dev_name = "ov5693.1",
1201 .mclk_name = "mclk2",
1202 .cap = &ov5693_front_cap,
1211 static int ardbeg_ad5823_power_on(struct ad5823_platform_data *pdata)
1215 pr_info("%s\n", __func__);
1216 gpio_set_value_cansleep(pdata->gpio, 1);
1217 pdata->pwr_dev = AD5823_PWR_DEV_ON;
1222 static int ardbeg_ad5823_power_off(struct ad5823_platform_data *pdata)
1224 pr_info("%s\n", __func__);
1225 gpio_set_value_cansleep(pdata->gpio, 0);
1226 pdata->pwr_dev = AD5823_PWR_DEV_OFF;
1231 static struct ad5823_platform_data ardbeg_ad5823_pdata = {
1232 .gpio = CAM_AF_PWDN,
1233 .power_on = ardbeg_ad5823_power_on,
1234 .power_off = ardbeg_ad5823_power_off,
1237 static struct camera_data_blob ardbeg_camera_lut[] = {
1238 {"ardbeg_imx135_pdata", &ardbeg_imx135_data},
1239 {"ardbeg_dw9718_pdata", &ardbeg_dw9718_data},
1240 {"ardbeg_ar0261_pdata", &ardbeg_ar0261_data},
1241 {"ardbeg_mt9m114_pdata", &ardbeg_mt9m114_pdata},
1242 {"ardbeg_ov5693_pdata", &ardbeg_ov5693_pdata},
1243 {"ardbeg_ad5823_pdata", &ardbeg_ad5823_pdata},
1244 {"ardbeg_as3648_pdata", &ardbeg_as3648_data},
1245 {"ardbeg_ov7695_pdata", &ardbeg_ov7695_pdata},
1246 {"ardbeg_ov5693f_pdata", &ardbeg_ov5693_front_pdata},
1247 {"ardbeg_ar0330_pdata", &ardbeg_ar0330_data},
1248 {"ardbeg_ar0330_front_pdata", &ardbeg_ar0330_front_data},
1252 void __init ardbeg_camera_auxdata(void *data)
1254 struct of_dev_auxdata *aux_lut = data;
1255 while (aux_lut && aux_lut->compatible) {
1256 if (!strcmp(aux_lut->compatible, "nvidia,tegra124-camera")) {
1257 pr_info("%s: update camera lookup table.\n", __func__);
1258 aux_lut->platform_data = ardbeg_camera_lut;
1264 static int ardbeg_camera_init(void)
1266 struct board_info board_info;
1268 pr_debug("%s: ++\n", __func__);
1269 tegra_get_board_info(&board_info);
1271 /* put CSIA/B/C/D/E IOs into DPD mode to
1272 * save additional power for ardbeg
1274 tegra_io_dpd_enable(&csia_io);
1275 tegra_io_dpd_enable(&csib_io);
1276 tegra_io_dpd_enable(&csie_io);
1278 #if IS_ENABLED(CONFIG_SOC_CAMERA_PLATFORM)
1279 platform_device_register(&ardbeg_soc_camera_device);
1282 #if IS_ENABLED(CONFIG_SOC_CAMERA_IMX135)
1283 platform_device_register(&ardbeg_imx135_soc_camera_device);
1289 static struct pid_thermal_gov_params cpu_pid_params = {
1290 .max_err_temp = 4000,
1291 .max_err_gain = 1000,
1296 .up_compensation = 15,
1297 .down_compensation = 15,
1300 static struct thermal_zone_params cpu_tzp = {
1301 .governor_name = "pid_thermal_gov",
1302 .governor_params = &cpu_pid_params,
1305 static struct thermal_zone_params board_tzp = {
1306 .governor_name = "pid_thermal_gov"
1309 static struct throttle_table cpu_throttle_table[] = {
1310 /* CPU_THROT_LOW cannot be used by other than CPU */
1311 /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
1312 { { 2295000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1313 { { 2269500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1314 { { 2244000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1315 { { 2218500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1316 { { 2193000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1317 { { 2167500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1318 { { 2142000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1319 { { 2116500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1320 { { 2091000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1321 { { 2065500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1322 { { 2040000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1323 { { 2014500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1324 { { 1989000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1325 { { 1963500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1326 { { 1938000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1327 { { 1912500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1328 { { 1887000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1329 { { 1861500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1330 { { 1836000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1331 { { 1810500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1332 { { 1785000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1333 { { 1759500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1334 { { 1734000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1335 { { 1708500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1336 { { 1683000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1337 { { 1657500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1338 { { 1632000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1339 { { 1606500, 790000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1340 { { 1581000, 776000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1341 { { 1555500, 762000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1342 { { 1530000, 749000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1343 { { 1504500, 735000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1344 { { 1479000, 721000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1345 { { 1453500, 707000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1346 { { 1428000, 693000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1347 { { 1402500, 679000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1348 { { 1377000, 666000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1349 { { 1351500, 652000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1350 { { 1326000, 638000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1351 { { 1300500, 624000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1352 { { 1275000, 610000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1353 { { 1249500, 596000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1354 { { 1224000, 582000, NO_CAP, NO_CAP, NO_CAP, 792000 } },
1355 { { 1198500, 569000, NO_CAP, NO_CAP, NO_CAP, 792000 } },
1356 { { 1173000, 555000, NO_CAP, NO_CAP, 360000, 792000 } },
1357 { { 1147500, 541000, NO_CAP, NO_CAP, 360000, 792000 } },
1358 { { 1122000, 527000, NO_CAP, 684000, 360000, 792000 } },
1359 { { 1096500, 513000, 444000, 684000, 360000, 792000 } },
1360 { { 1071000, 499000, 444000, 684000, 360000, 792000 } },
1361 { { 1045500, 486000, 444000, 684000, 360000, 792000 } },
1362 { { 1020000, 472000, 444000, 684000, 324000, 792000 } },
1363 { { 994500, 458000, 444000, 684000, 324000, 792000 } },
1364 { { 969000, 444000, 444000, 600000, 324000, 792000 } },
1365 { { 943500, 430000, 444000, 600000, 324000, 792000 } },
1366 { { 918000, 416000, 396000, 600000, 324000, 792000 } },
1367 { { 892500, 402000, 396000, 600000, 324000, 792000 } },
1368 { { 867000, 389000, 396000, 600000, 324000, 792000 } },
1369 { { 841500, 375000, 396000, 600000, 288000, 792000 } },
1370 { { 816000, 361000, 396000, 600000, 288000, 792000 } },
1371 { { 790500, 347000, 396000, 600000, 288000, 792000 } },
1372 { { 765000, 333000, 396000, 504000, 288000, 792000 } },
1373 { { 739500, 319000, 348000, 504000, 288000, 792000 } },
1374 { { 714000, 306000, 348000, 504000, 288000, 624000 } },
1375 { { 688500, 292000, 348000, 504000, 288000, 624000 } },
1376 { { 663000, 278000, 348000, 504000, 288000, 624000 } },
1377 { { 637500, 264000, 348000, 504000, 288000, 624000 } },
1378 { { 612000, 250000, 348000, 504000, 252000, 624000 } },
1379 { { 586500, 236000, 348000, 504000, 252000, 624000 } },
1380 { { 561000, 222000, 348000, 420000, 252000, 624000 } },
1381 { { 535500, 209000, 288000, 420000, 252000, 624000 } },
1382 { { 510000, 195000, 288000, 420000, 252000, 624000 } },
1383 { { 484500, 181000, 288000, 420000, 252000, 624000 } },
1384 { { 459000, 167000, 288000, 420000, 252000, 624000 } },
1385 { { 433500, 153000, 288000, 420000, 252000, 396000 } },
1386 { { 408000, 139000, 288000, 420000, 252000, 396000 } },
1387 { { 382500, 126000, 288000, 420000, 252000, 396000 } },
1388 { { 357000, 112000, 288000, 420000, 252000, 396000 } },
1389 { { 331500, 98000, 288000, 420000, 252000, 396000 } },
1390 { { 306000, 84000, 288000, 420000, 252000, 396000 } },
1391 { { 280500, 84000, 288000, 420000, 252000, 396000 } },
1392 { { 255000, 84000, 288000, 420000, 252000, 396000 } },
1393 { { 229500, 84000, 288000, 420000, 252000, 396000 } },
1394 { { 204000, 84000, 288000, 420000, 252000, 396000 } },
1397 static struct balanced_throttle cpu_throttle = {
1398 .throt_tab_size = ARRAY_SIZE(cpu_throttle_table),
1399 .throt_tab = cpu_throttle_table,
1402 static struct throttle_table gpu_throttle_table[] = {
1403 /* CPU_THROT_LOW cannot be used by other than CPU */
1404 /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
1405 { { 2295000, 782800, 480000, 756000, 384000, 924000 } },
1406 { { 2269500, 772200, 480000, 756000, 384000, 924000 } },
1407 { { 2244000, 761600, 480000, 756000, 384000, 924000 } },
1408 { { 2218500, 751100, 480000, 756000, 384000, 924000 } },
1409 { { 2193000, 740500, 480000, 756000, 384000, 924000 } },
1410 { { 2167500, 729900, 480000, 756000, 384000, 924000 } },
1411 { { 2142000, 719300, 480000, 756000, 384000, 924000 } },
1412 { { 2116500, 708700, 480000, 756000, 384000, 924000 } },
1413 { { 2091000, 698100, 480000, 756000, 384000, 924000 } },
1414 { { 2065500, 687500, 480000, 756000, 384000, 924000 } },
1415 { { 2040000, 676900, 480000, 756000, 384000, 924000 } },
1416 { { 2014500, 666000, 480000, 756000, 384000, 924000 } },
1417 { { 1989000, 656000, 480000, 756000, 384000, 924000 } },
1418 { { 1963500, 645000, 480000, 756000, 384000, 924000 } },
1419 { { 1938000, 635000, 480000, 756000, 384000, 924000 } },
1420 { { 1912500, 624000, 480000, 756000, 384000, 924000 } },
1421 { { 1887000, 613000, 480000, 756000, 384000, 924000 } },
1422 { { 1861500, 603000, 480000, 756000, 384000, 924000 } },
1423 { { 1836000, 592000, 480000, 756000, 384000, 924000 } },
1424 { { 1810500, 582000, 480000, 756000, 384000, 924000 } },
1425 { { 1785000, 571000, 480000, 756000, 384000, 924000 } },
1426 { { 1759500, 560000, 480000, 756000, 384000, 924000 } },
1427 { { 1734000, 550000, 480000, 756000, 384000, 924000 } },
1428 { { 1708500, 539000, 480000, 756000, 384000, 924000 } },
1429 { { 1683000, 529000, 480000, 756000, 384000, 924000 } },
1430 { { 1657500, 518000, 480000, 756000, 384000, 924000 } },
1431 { { 1632000, 508000, 480000, 756000, 384000, 924000 } },
1432 { { 1606500, 497000, 480000, 756000, 384000, 924000 } },
1433 { { 1581000, 486000, 480000, 756000, 384000, 924000 } },
1434 { { 1555500, 476000, 480000, 756000, 384000, 924000 } },
1435 { { 1530000, 465000, 480000, 756000, 384000, 924000 } },
1436 { { 1504500, 455000, 480000, 756000, 384000, 924000 } },
1437 { { 1479000, 444000, 480000, 756000, 384000, 924000 } },
1438 { { 1453500, 433000, 480000, 756000, 384000, 924000 } },
1439 { { 1428000, 423000, 480000, 756000, 384000, 924000 } },
1440 { { 1402500, 412000, 480000, 756000, 384000, 924000 } },
1441 { { 1377000, 402000, 480000, 756000, 384000, 924000 } },
1442 { { 1351500, 391000, 480000, 756000, 384000, 924000 } },
1443 { { 1326000, 380000, 480000, 756000, 384000, 924000 } },
1444 { { 1300500, 370000, 480000, 756000, 384000, 924000 } },
1445 { { 1275000, 359000, 480000, 756000, 384000, 924000 } },
1446 { { 1249500, 349000, 480000, 756000, 384000, 924000 } },
1447 { { 1224000, 338000, 480000, 756000, 384000, 792000 } },
1448 { { 1198500, 328000, 480000, 756000, 384000, 792000 } },
1449 { { 1173000, 317000, 480000, 756000, 360000, 792000 } },
1450 { { 1147500, 306000, 480000, 756000, 360000, 792000 } },
1451 { { 1122000, 296000, 480000, 684000, 360000, 792000 } },
1452 { { 1096500, 285000, 444000, 684000, 360000, 792000 } },
1453 { { 1071000, 275000, 444000, 684000, 360000, 792000 } },
1454 { { 1045500, 264000, 444000, 684000, 360000, 792000 } },
1455 { { 1020000, 253000, 444000, 684000, 324000, 792000 } },
1456 { { 994500, 243000, 444000, 684000, 324000, 792000 } },
1457 { { 969000, 232000, 444000, 600000, 324000, 792000 } },
1458 { { 943500, 222000, 444000, 600000, 324000, 792000 } },
1459 { { 918000, 211000, 396000, 600000, 324000, 792000 } },
1460 { { 892500, 200000, 396000, 600000, 324000, 792000 } },
1461 { { 867000, 190000, 396000, 600000, 324000, 792000 } },
1462 { { 841500, 179000, 396000, 600000, 288000, 792000 } },
1463 { { 816000, 169000, 396000, 600000, 288000, 792000 } },
1464 { { 790500, 158000, 396000, 600000, 288000, 792000 } },
1465 { { 765000, 148000, 396000, 504000, 288000, 792000 } },
1466 { { 739500, 137000, 348000, 504000, 288000, 792000 } },
1467 { { 714000, 126000, 348000, 504000, 288000, 624000 } },
1468 { { 688500, 116000, 348000, 504000, 288000, 624000 } },
1469 { { 663000, 105000, 348000, 504000, 288000, 624000 } },
1470 { { 637500, 95000, 348000, 504000, 288000, 624000 } },
1471 { { 612000, 84000, 348000, 504000, 252000, 624000 } },
1472 { { 586500, 84000, 348000, 504000, 252000, 624000 } },
1473 { { 561000, 84000, 348000, 420000, 252000, 624000 } },
1474 { { 535500, 84000, 288000, 420000, 252000, 624000 } },
1475 { { 510000, 84000, 288000, 420000, 252000, 624000 } },
1476 { { 484500, 84000, 288000, 420000, 252000, 624000 } },
1477 { { 459000, 84000, 288000, 420000, 252000, 624000 } },
1478 { { 433500, 84000, 288000, 420000, 252000, 396000 } },
1479 { { 408000, 84000, 288000, 420000, 252000, 396000 } },
1480 { { 382500, 84000, 288000, 420000, 252000, 396000 } },
1481 { { 357000, 84000, 288000, 420000, 252000, 396000 } },
1482 { { 331500, 84000, 288000, 420000, 252000, 396000 } },
1483 { { 306000, 84000, 288000, 420000, 252000, 396000 } },
1484 { { 280500, 84000, 288000, 420000, 252000, 396000 } },
1485 { { 255000, 84000, 288000, 420000, 252000, 396000 } },
1486 { { 229500, 84000, 288000, 420000, 252000, 396000 } },
1487 { { 204000, 84000, 288000, 420000, 252000, 396000 } },
1490 static struct balanced_throttle gpu_throttle = {
1491 .throt_tab_size = ARRAY_SIZE(gpu_throttle_table),
1492 .throt_tab = gpu_throttle_table,
1495 /* throttle table that sets all clocks to approximately 50% of their max */
1496 static struct throttle_table emergency_throttle_table[] = {
1497 /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
1498 { { 1122000, 391000, 288000, 420000, 252000, 396000 } },
1501 static struct balanced_throttle emergency_throttle = {
1502 .throt_tab_size = ARRAY_SIZE(emergency_throttle_table),
1503 .throt_tab = emergency_throttle_table,
1506 static int __init ardbeg_balanced_throttle_init(void)
1508 if (of_machine_is_compatible("nvidia,ardbeg") ||
1509 of_machine_is_compatible("nvidia,norrin") ||
1510 of_machine_is_compatible("nvidia,bowmore") ||
1511 of_machine_is_compatible("nvidia,tn8")) {
1513 if (!balanced_throttle_register(&cpu_throttle, "cpu-balanced"))
1514 pr_err("balanced_throttle_register 'cpu-balanced' FAILED.\n");
1515 if (!balanced_throttle_register(&gpu_throttle, "gpu-balanced"))
1516 pr_err("balanced_throttle_register 'gpu-balanced' FAILED.\n");
1517 if (!balanced_throttle_register(&emergency_throttle,
1518 "emergency-balanced"))
1519 pr_err("balanced_throttle_register 'emergency-balanced' FAILED\n");
1524 late_initcall(ardbeg_balanced_throttle_init);
1526 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
1527 static struct thermal_trip_info skin_trips[] = {
1529 .cdev_type = "skin-balanced",
1531 .trip_type = THERMAL_TRIP_PASSIVE,
1532 .upper = THERMAL_NO_LIMIT,
1533 .lower = THERMAL_NO_LIMIT,
1538 static struct therm_est_subdevice skin_devs[] = {
1540 .dev_data = "Tdiode_tegra",
1550 .dev_data = "Tboard_tegra",
1561 static struct therm_est_subdevice tn8ffd_skin_devs[] = {
1563 .dev_data = "Tdiode",
1573 .dev_data = "Tboard",
1584 static struct therm_est_subdevice tn8ffd_t132_skin_devs[] = {
1586 .dev_data = "Tdiode",
1596 .dev_data = "Tboard",
1607 static struct pid_thermal_gov_params skin_pid_params = {
1608 .max_err_temp = 4000,
1609 .max_err_gain = 1000,
1614 .up_compensation = 15,
1615 .down_compensation = 15,
1618 static struct thermal_zone_params skin_tzp = {
1619 .governor_name = "pid_thermal_gov",
1620 .governor_params = &skin_pid_params,
1623 static struct therm_est_data skin_data = {
1624 .num_trips = ARRAY_SIZE(skin_trips),
1625 .trips = skin_trips,
1626 .polling_period = 1100,
1627 .passive_delay = 15000,
1634 static struct throttle_table skin_throttle_table[] = {
1635 /* CPU_THROT_LOW cannot be used by other than CPU */
1636 /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
1637 { { 2295000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1638 { { 2269500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1639 { { 2244000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1640 { { 2218500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1641 { { 2193000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1642 { { 2167500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1643 { { 2142000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1644 { { 2116500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1645 { { 2091000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1646 { { 2065500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1647 { { 2040000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1648 { { 2014500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1649 { { 1989000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1650 { { 1963500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1651 { { 1938000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1652 { { 1912500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1653 { { 1887000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1654 { { 1861500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1655 { { 1836000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1656 { { 1810500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1657 { { 1785000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1658 { { 1759500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1659 { { 1734000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1660 { { 1708500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1661 { { 1683000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1662 { { 1657500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1663 { { 1632000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1664 { { 1606500, 790000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1665 { { 1581000, 776000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1666 { { 1555500, 762000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1667 { { 1530000, 749000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1668 { { 1504500, 735000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1669 { { 1479000, 721000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1670 { { 1453500, 707000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1671 { { 1428000, 693000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1672 { { 1402500, 679000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1673 { { 1377000, 666000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1674 { { 1351500, 652000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1675 { { 1326000, 638000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1676 { { 1300500, 624000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1677 { { 1275000, 610000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1678 { { 1249500, 596000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } },
1679 { { 1224000, 582000, NO_CAP, NO_CAP, NO_CAP, 792000 } },
1680 { { 1198500, 569000, NO_CAP, NO_CAP, NO_CAP, 792000 } },
1681 { { 1173000, 555000, NO_CAP, NO_CAP, 360000, 792000 } },
1682 { { 1147500, 541000, NO_CAP, NO_CAP, 360000, 792000 } },
1683 { { 1122000, 527000, NO_CAP, 684000, 360000, 792000 } },
1684 { { 1096500, 513000, 444000, 684000, 360000, 792000 } },
1685 { { 1071000, 499000, 444000, 684000, 360000, 792000 } },
1686 { { 1045500, 486000, 444000, 684000, 360000, 792000 } },
1687 { { 1020000, 472000, 444000, 684000, 324000, 792000 } },
1688 { { 994500, 458000, 444000, 684000, 324000, 792000 } },
1689 { { 969000, 444000, 444000, 600000, 324000, 792000 } },
1690 { { 943500, 430000, 444000, 600000, 324000, 792000 } },
1691 { { 918000, 416000, 396000, 600000, 324000, 792000 } },
1692 { { 892500, 402000, 396000, 600000, 324000, 792000 } },
1693 { { 867000, 389000, 396000, 600000, 324000, 792000 } },
1694 { { 841500, 375000, 396000, 600000, 288000, 792000 } },
1695 { { 816000, 361000, 396000, 600000, 288000, 792000 } },
1696 { { 790500, 347000, 396000, 600000, 288000, 792000 } },
1697 { { 765000, 333000, 396000, 504000, 288000, 792000 } },
1698 { { 739500, 319000, 348000, 504000, 288000, 792000 } },
1699 { { 714000, 306000, 348000, 504000, 288000, 624000 } },
1700 { { 688500, 292000, 348000, 504000, 288000, 624000 } },
1701 { { 663000, 278000, 348000, 504000, 288000, 624000 } },
1702 { { 637500, 264000, 348000, 504000, 288000, 624000 } },
1703 { { 612000, 250000, 348000, 504000, 252000, 624000 } },
1704 { { 586500, 236000, 348000, 504000, 252000, 624000 } },
1705 { { 561000, 222000, 348000, 420000, 252000, 624000 } },
1706 { { 535500, 209000, 288000, 420000, 252000, 624000 } },
1707 { { 510000, 195000, 288000, 420000, 252000, 624000 } },
1708 { { 484500, 181000, 288000, 420000, 252000, 624000 } },
1709 { { 459000, 167000, 288000, 420000, 252000, 624000 } },
1710 { { 433500, 153000, 288000, 420000, 252000, 396000 } },
1711 { { 408000, 139000, 288000, 420000, 252000, 396000 } },
1712 { { 382500, 126000, 288000, 420000, 252000, 396000 } },
1713 { { 357000, 112000, 288000, 420000, 252000, 396000 } },
1714 { { 331500, 98000, 288000, 420000, 252000, 396000 } },
1715 { { 306000, 84000, 288000, 420000, 252000, 396000 } },
1716 { { 280500, 84000, 288000, 420000, 252000, 396000 } },
1717 { { 255000, 84000, 288000, 420000, 252000, 396000 } },
1718 { { 229500, 84000, 288000, 420000, 252000, 396000 } },
1719 { { 204000, 84000, 288000, 420000, 252000, 396000 } },
1722 static struct balanced_throttle skin_throttle = {
1723 .throt_tab_size = ARRAY_SIZE(skin_throttle_table),
1724 .throt_tab = skin_throttle_table,
1727 static int __init ardbeg_skin_init(void)
1729 struct board_info board_info;
1731 if (of_machine_is_compatible("nvidia,ardbeg") ||
1732 of_machine_is_compatible("nvidia,norrin") ||
1733 of_machine_is_compatible("nvidia,bowmore") ||
1734 of_machine_is_compatible("nvidia,tn8")) {
1736 tegra_get_board_info(&board_info);
1738 if (board_info.board_id == BOARD_P1761 &&
1739 board_info.fab == BOARD_FAB_D) {
1740 skin_data.ndevs = ARRAY_SIZE(tn8ffd_t132_skin_devs);
1741 skin_data.devs = tn8ffd_t132_skin_devs;
1742 skin_data.toffset = 708;
1743 } else if (board_info.board_id == BOARD_P1761 ||
1744 board_info.board_id == BOARD_E1784 ||
1745 board_info.board_id == BOARD_E1971 ||
1746 board_info.board_id == BOARD_E1991 ||
1747 board_info.board_id == BOARD_E1922) {
1748 skin_data.ndevs = ARRAY_SIZE(tn8ffd_skin_devs);
1749 skin_data.devs = tn8ffd_skin_devs;
1750 skin_data.toffset = 4034;
1752 skin_data.ndevs = ARRAY_SIZE(skin_devs);
1753 skin_data.devs = skin_devs;
1754 skin_data.toffset = 9793;
1757 tegra_skin_therm_est_device.dev.platform_data = &skin_data;
1758 platform_device_register(&tegra_skin_therm_est_device);
1760 if (!balanced_throttle_register(&skin_throttle, "skin-balanced"))
1761 pr_err("balanced_throttle_register 'skin-balanced' FAILED.\n");
1766 late_initcall(ardbeg_skin_init);
1769 static struct nct1008_platform_data ardbeg_nct72_pdata = {
1770 .loc_name = "tegra",
1771 .supported_hwrev = true,
1772 .conv_rate = 0x06, /* 4Hz conversion rate */
1774 .extended_range = true,
1779 .shutdown_limit = 120, /* C */
1780 .passive_delay = 1000,
1784 .cdev_type = "therm_est_activ",
1786 .trip_type = THERMAL_TRIP_ACTIVE,
1788 .upper = THERMAL_NO_LIMIT,
1789 .lower = THERMAL_NO_LIMIT,
1796 .shutdown_limit = 95, /* C */
1797 .passive_delay = 1000,
1801 .cdev_type = "shutdown_warning",
1803 .trip_type = THERMAL_TRIP_PASSIVE,
1804 .upper = THERMAL_NO_LIMIT,
1805 .lower = THERMAL_NO_LIMIT,
1809 .cdev_type = "cpu-balanced",
1811 .trip_type = THERMAL_TRIP_PASSIVE,
1812 .upper = THERMAL_NO_LIMIT,
1813 .lower = THERMAL_NO_LIMIT,
1822 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
1823 static struct nct1008_platform_data ardbeg_nct72_tskin_pdata = {
1826 .supported_hwrev = true,
1827 .conv_rate = 0x06, /* 4Hz conversion rate */
1829 .extended_range = true,
1833 .shutdown_limit = 95, /* C */
1838 .shutdown_limit = 85, /* C */
1839 .passive_delay = 10000,
1840 .polling_delay = 1000,
1845 .cdev_type = "skin-balanced",
1847 .trip_type = THERMAL_TRIP_PASSIVE,
1848 .upper = THERMAL_NO_LIMIT,
1849 .lower = THERMAL_NO_LIMIT,
1858 static struct i2c_board_info ardbeg_i2c_nct72_board_info[] = {
1860 I2C_BOARD_INFO("nct72", 0x4c),
1861 .platform_data = &ardbeg_nct72_pdata,
1864 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
1866 I2C_BOARD_INFO("nct72", 0x4d),
1867 .platform_data = &ardbeg_nct72_tskin_pdata,
1873 static int ardbeg_nct72_init(void)
1875 int nct72_port = TEGRA_GPIO_PI6;
1878 struct thermal_trip_info *trip_state;
1879 struct board_info board_info;
1881 tegra_get_board_info(&board_info);
1882 /* raise NCT's thresholds if soctherm CP,FT fuses are ok */
1883 if ((tegra_fuse_calib_base_get_cp(NULL, NULL) >= 0) &&
1884 (tegra_fuse_calib_base_get_ft(NULL, NULL) >= 0)) {
1885 ardbeg_nct72_pdata.sensors[EXT].shutdown_limit += 20;
1886 for (i = 0; i < ardbeg_nct72_pdata.sensors[EXT].num_trips;
1888 trip_state = &ardbeg_nct72_pdata.sensors[EXT].trips[i];
1889 if (!strncmp(trip_state->cdev_type, "cpu-balanced",
1890 THERMAL_NAME_LENGTH)) {
1891 trip_state->cdev_type = "_none_";
1896 tegra_platform_edp_init(
1897 ardbeg_nct72_pdata.sensors[EXT].trips,
1898 &ardbeg_nct72_pdata.sensors[EXT].num_trips,
1899 12000); /* edp temperature margin */
1900 tegra_add_cpu_vmax_trips(
1901 ardbeg_nct72_pdata.sensors[EXT].trips,
1902 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
1903 tegra_add_tgpu_trips(
1904 ardbeg_nct72_pdata.sensors[EXT].trips,
1905 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
1907 ardbeg_nct72_pdata.sensors[EXT].trips,
1908 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
1909 tegra_add_core_vmax_trips(
1910 ardbeg_nct72_pdata.sensors[EXT].trips,
1911 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
1914 /* vmin trips are bound to soctherm on norrin */
1915 if (!(board_info.board_id == BOARD_PM374))
1916 tegra_add_all_vmin_trips(ardbeg_nct72_pdata.sensors[EXT].trips,
1917 &ardbeg_nct72_pdata.sensors[EXT].num_trips);
1919 ardbeg_i2c_nct72_board_info[0].irq = gpio_to_irq(nct72_port);
1921 ret = gpio_request(nct72_port, "temp_alert");
1925 ret = gpio_direction_input(nct72_port);
1927 pr_info("%s: calling gpio_free(nct72_port)", __func__);
1928 gpio_free(nct72_port);
1931 /* norrin has thermal sensor on GEN1-I2C i.e. instance 0 */
1932 if (board_info.board_id == BOARD_PM374)
1933 i2c_register_board_info(0, ardbeg_i2c_nct72_board_info,
1934 1); /* only register device[0] */
1935 /* ardbeg has thermal sensor on GEN2-I2C i.e. instance 1 */
1936 else if (board_info.board_id == BOARD_PM358 ||
1937 board_info.board_id == BOARD_PM359 ||
1938 board_info.board_id == BOARD_PM370 ||
1939 board_info.board_id == BOARD_PM363)
1940 i2c_register_board_info(1, ardbeg_i2c_nct72_board_info,
1941 ARRAY_SIZE(ardbeg_i2c_nct72_board_info));
1942 else if (board_info.board_id == BOARD_PM375 ||
1943 board_info.board_id == BOARD_PM377) {
1944 ardbeg_nct72_pdata.sensors[EXT].shutdown_limit = 100;
1945 ardbeg_nct72_pdata.sensors[LOC].shutdown_limit = 95;
1946 i2c_register_board_info(0, ardbeg_i2c_nct72_board_info,
1947 1); /* only register device[0] */
1950 i2c_register_board_info(1, ardbeg_i2c_nct72_board_info,
1951 ARRAY_SIZE(ardbeg_i2c_nct72_board_info));
1956 struct ntc_thermistor_adc_table {
1957 int temp; /* degree C */
1961 static struct ntc_thermistor_adc_table tn8_thermistor_table[] = {
1962 { -40, 2578 }, { -39, 2577 }, { -38, 2576 }, { -37, 2575 },
1963 { -36, 2574 }, { -35, 2573 }, { -34, 2572 }, { -33, 2571 },
1964 { -32, 2569 }, { -31, 2568 }, { -30, 2567 }, { -29, 2565 },
1965 { -28, 2563 }, { -27, 2561 }, { -26, 2559 }, { -25, 2557 },
1966 { -24, 2555 }, { -23, 2553 }, { -22, 2550 }, { -21, 2548 },
1967 { -20, 2545 }, { -19, 2542 }, { -18, 2539 }, { -17, 2536 },
1968 { -16, 2532 }, { -15, 2529 }, { -14, 2525 }, { -13, 2521 },
1969 { -12, 2517 }, { -11, 2512 }, { -10, 2507 }, { -9, 2502 },
1970 { -8, 2497 }, { -7, 2492 }, { -6, 2486 }, { -5, 2480 },
1971 { -4, 2473 }, { -3, 2467 }, { -2, 2460 }, { -1, 2452 },
1972 { 0, 2445 }, { 1, 2437 }, { 2, 2428 }, { 3, 2419 },
1973 { 4, 2410 }, { 5, 2401 }, { 6, 2391 }, { 7, 2380 },
1974 { 8, 2369 }, { 9, 2358 }, { 10, 2346 }, { 11, 2334 },
1975 { 12, 2322 }, { 13, 2308 }, { 14, 2295 }, { 15, 2281 },
1976 { 16, 2266 }, { 17, 2251 }, { 18, 2236 }, { 19, 2219 },
1977 { 20, 2203 }, { 21, 2186 }, { 22, 2168 }, { 23, 2150 },
1978 { 24, 2131 }, { 25, 2112 }, { 26, 2092 }, { 27, 2072 },
1979 { 28, 2052 }, { 29, 2030 }, { 30, 2009 }, { 31, 1987 },
1980 { 32, 1964 }, { 33, 1941 }, { 34, 1918 }, { 35, 1894 },
1981 { 36, 1870 }, { 37, 1845 }, { 38, 1820 }, { 39, 1795 },
1982 { 40, 1769 }, { 41, 1743 }, { 42, 1717 }, { 43, 1691 },
1983 { 44, 1664 }, { 45, 1637 }, { 46, 1610 }, { 47, 1583 },
1984 { 48, 1555 }, { 49, 1528 }, { 50, 1500 }, { 51, 1472 },
1985 { 52, 1445 }, { 53, 1417 }, { 54, 1390 }, { 55, 1362 },
1986 { 56, 1334 }, { 57, 1307 }, { 58, 1280 }, { 59, 1253 },
1987 { 60, 1226 }, { 61, 1199 }, { 62, 1172 }, { 63, 1146 },
1988 { 64, 1120 }, { 65, 1094 }, { 66, 1069 }, { 67, 1044 },
1989 { 68, 1019 }, { 69, 994 }, { 70, 970 }, { 71, 946 },
1990 { 72, 922 }, { 73, 899 }, { 74, 877 }, { 75, 854 },
1991 { 76, 832 }, { 77, 811 }, { 78, 789 }, { 79, 769 },
1992 { 80, 748 }, { 81, 729 }, { 82, 709 }, { 83, 690 },
1993 { 84, 671 }, { 85, 653 }, { 86, 635 }, { 87, 618 },
1994 { 88, 601 }, { 89, 584 }, { 90, 568 }, { 91, 552 },
1995 { 92, 537 }, { 93, 522 }, { 94, 507 }, { 95, 493 },
1996 { 96, 479 }, { 97, 465 }, { 98, 452 }, { 99, 439 },
1997 { 100, 427 }, { 101, 415 }, { 102, 403 }, { 103, 391 },
1998 { 104, 380 }, { 105, 369 }, { 106, 359 }, { 107, 349 },
1999 { 108, 339 }, { 109, 329 }, { 110, 320 }, { 111, 310 },
2000 { 112, 302 }, { 113, 293 }, { 114, 285 }, { 115, 277 },
2001 { 116, 269 }, { 117, 261 }, { 118, 254 }, { 119, 247 },
2002 { 120, 240 }, { 121, 233 }, { 122, 226 }, { 123, 220 },
2003 { 124, 214 }, { 125, 208 },
2006 static struct ntc_thermistor_adc_table *thermistor_table;
2007 static int thermistor_table_size;
2009 static int gadc_thermal_thermistor_adc_to_temp(
2010 struct gadc_thermal_platform_data *pdata, int val, int val2)
2012 int temp = 0, adc_hi, adc_lo;
2015 for (i = 0; i < thermistor_table_size; i++)
2016 if (val >= thermistor_table[i].adc)
2020 temp = thermistor_table[i].temp * 1000;
2021 } else if (i >= (thermistor_table_size - 1)) {
2022 temp = thermistor_table[thermistor_table_size - 1].temp * 1000;
2024 adc_hi = thermistor_table[i - 1].adc;
2025 adc_lo = thermistor_table[i].adc;
2026 temp = thermistor_table[i].temp * 1000;
2027 temp -= ((val - adc_lo) * 1000 / (adc_hi - adc_lo));
2033 #define TDIODE_PRECISION_MULTIPLIER 1000000000LL
2034 #define TDIODE_MIN_TEMP -25000LL
2035 #define TDIODE_MAX_TEMP 125000LL
2037 static int gadc_thermal_tdiode_adc_to_temp(
2038 struct gadc_thermal_platform_data *pdata, int val, int val2)
2041 * Series resistance cancellation using multi-current ADC measurement.
2042 * diode temp = ((adc2 - k * adc1) - (b2 - k * b1)) / (m2 - k * m1)
2043 * - adc1 : ADC raw with current source 400uA
2044 * - m1, b1 : calculated with current source 400uA
2045 * - adc2 : ADC raw with current source 800uA
2046 * - m2, b2 : calculated with current source 800uA
2047 * - k : 2 (= 800uA / 400uA)
2049 const s64 m1 = -0.00571005 * TDIODE_PRECISION_MULTIPLIER;
2050 const s64 b1 = 2524.29891 * TDIODE_PRECISION_MULTIPLIER;
2051 const s64 m2 = -0.005519811 * TDIODE_PRECISION_MULTIPLIER;
2052 const s64 b2 = 2579.354349 * TDIODE_PRECISION_MULTIPLIER;
2053 s64 temp = TDIODE_PRECISION_MULTIPLIER;
2055 temp *= (s64)((val2) - 2 * (val));
2056 temp -= (b2 - 2 * b1);
2057 temp = div64_s64(temp, (m2 - 2 * m1));
2058 temp = min_t(s64, max_t(s64, temp, TDIODE_MIN_TEMP), TDIODE_MAX_TEMP);
2062 static struct gadc_thermal_platform_data gadc_thermal_thermistor_pdata = {
2063 .iio_channel_name = "thermistor",
2064 .tz_name = "Tboard",
2066 .adc_to_temp = gadc_thermal_thermistor_adc_to_temp,
2068 .polling_delay = 15000,
2072 .cdev_type = "therm_est_activ",
2074 .trip_type = THERMAL_TRIP_ACTIVE,
2076 .upper = THERMAL_NO_LIMIT,
2077 .lower = THERMAL_NO_LIMIT,
2084 static struct gadc_thermal_platform_data gadc_thermal_tdiode_pdata = {
2085 .iio_channel_name = "tdiode",
2086 .tz_name = "Tdiode",
2089 .adc_to_temp = gadc_thermal_tdiode_adc_to_temp,
2092 static struct platform_device gadc_thermal_thermistor = {
2093 .name = "generic-adc-thermal",
2096 .platform_data = &gadc_thermal_thermistor_pdata,
2100 static struct platform_device gadc_thermal_tdiode = {
2101 .name = "generic-adc-thermal",
2104 .platform_data = &gadc_thermal_tdiode_pdata,
2108 static struct platform_device *gadc_thermal_devices[] = {
2109 &gadc_thermal_thermistor,
2110 &gadc_thermal_tdiode,
2113 int __init ardbeg_sensors_init(void)
2115 struct board_info board_info;
2116 tegra_get_board_info(&board_info);
2117 /* PM363 and PM359 don't have mpu 9250 mounted */
2118 /* TN8 sensors use Device Tree */
2119 if (board_info.board_id != BOARD_PM363 &&
2120 board_info.board_id != BOARD_PM359 &&
2121 !of_machine_is_compatible("nvidia,tn8") &&
2122 !of_machine_is_compatible("nvidia,bowmore") &&
2123 board_info.board_id != BOARD_PM375 &&
2124 board_info.board_id != BOARD_PM377)
2126 ardbeg_camera_init();
2128 if (board_info.board_id == BOARD_P1761 ||
2129 board_info.board_id == BOARD_E1784 ||
2130 board_info.board_id == BOARD_E1971 ||
2131 board_info.board_id == BOARD_E1991 ||
2132 board_info.board_id == BOARD_E1922) {
2133 platform_add_devices(gadc_thermal_devices,
2134 ARRAY_SIZE(gadc_thermal_devices));
2135 thermistor_table = &tn8_thermistor_table[0];
2136 thermistor_table_size = ARRAY_SIZE(tn8_thermistor_table);
2138 ardbeg_nct72_init();
2140 #if defined(ARCH_TEGRA_12x_SOC)
2141 /* TN8 and PM359 don't have ALS CM32181 */
2142 if (!of_machine_is_compatible("nvidia,tn8") &&
2143 board_info.board_id != BOARD_PM359 &&
2144 board_info.board_id != BOARD_PM375 &&
2145 board_info.board_id != BOARD_PM377)
2146 i2c_register_board_info(0, ardbeg_i2c_board_info_cm32181,
2147 ARRAY_SIZE(ardbeg_i2c_board_info_cm32181));