drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *  Copyright (C) 2012-2014, NVIDIA CORPORATION.  All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or (at
  10  * your option) any later version.
  11  *
  12  * Thanks to the following companies for their support:
  13  *
  14  *     - JMicron (hardware and technical support)
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/highmem.h>
  19 #include <linux/io.h>
  20 #include <linux/module.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/slab.h>
  23 #include <linux/scatterlist.h>
  24 #include <linux/regulator/consumer.h>
  25 #include <linux/pm_runtime.h>
  26
  27 #include <linux/leds.h>
  28
  29 #include <linux/mmc/mmc.h>
  30 #include <linux/mmc/host.h>
  31 #include <linux/mmc/card.h>
  32 #include <linux/mmc/slot-gpio.h>
  33
  34 #include <linux/sysedp.h>
  35 #ifdef CONFIG_DEBUG_FS
  36 #include <linux/debugfs.h>
  37 #include <linux/ktime.h>
  38 #endif
  39
  40 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
  41 #include <linux/tegra-soc.h>
  42 #endif
  43
  44 #include "sdhci.h"
  45
  46 #define DRIVER_NAME "sdhci"
  47
  48 #define DBG(f, x...) \
  49         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  50
  51 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  52         defined(CONFIG_MMC_SDHCI_MODULE))
  53 #define SDHCI_USE_LEDS_CLASS
  54 #endif
  55
  56 #define MAX_TUNING_LOOP 40
  57
  58 #define SDIO_CLK_GATING_TICK_TMOUT (HZ / 1000) /* 1msec timeout */
  59 #define EMMC_CLK_GATING_TICK_TMOUT (HZ / 50) /* 20msec timeout */
  60
  61 #define IS_SDIO_CARD(host) \
  62                 (host->mmc->card && \
  63                 (host->mmc->card->type == MMC_TYPE_SDIO))
  64
  65 #define IS_EMMC_CARD(host) \
  66                 (host->mmc->card && \
  67                 (host->mmc->card->type == MMC_TYPE_MMC))
  68
  69 #define IS_SDIO_CARD_OR_EMMC(host) \
  70                 (host->mmc->card && \
  71                 ((host->mmc->card->type == MMC_TYPE_SDIO) || \
  72                 (host->mmc->card->type == MMC_TYPE_MMC)))
  73
  74 #define IS_DELAYED_CLK_GATE(host) \
  75                 ((host->quirks2 & SDHCI_QUIRK2_DELAYED_CLK_GATE) && \
  76                 (IS_SDIO_CARD_OR_EMMC(host)) && \
  77                 (host->mmc->caps2 & MMC_CAP2_CLOCK_GATING))
  78
  79 #ifdef CONFIG_DEBUG_FS
  80 #define IS_32_BIT(x)    (x < (1ULL << 32))
  81 #endif
  82
  83 static unsigned int debug_quirks = 0;
  84 static unsigned int debug_quirks2;
  85
  86 static void sdhci_finish_data(struct sdhci_host *);
  87
  88 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  89 static void sdhci_finish_command(struct sdhci_host *);
  90 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
  91 static void sdhci_tuning_timer(unsigned long data);
  92 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
  93
  94 #ifdef CONFIG_PM_RUNTIME
  95 static int sdhci_runtime_pm_get(struct sdhci_host *host);
  96 static int sdhci_runtime_pm_put(struct sdhci_host *host);
  97 #else
  98 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
  99 {
 100         return 0;
 101 }
 102 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
 103 {
 104         return 0;
 105 }
 106 #endif
 107
 108 static void sdhci_dumpregs(struct sdhci_host *host)
 109 {
 110         pr_err(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
 111                 mmc_hostname(host->mmc));
 112
 113         pr_err(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
 114                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
 115                 sdhci_readw(host, SDHCI_HOST_VERSION));
 116         pr_err(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
 117                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
 118                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
 119         pr_err(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
 120                 sdhci_readl(host, SDHCI_ARGUMENT),
 121                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
 122         pr_err(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
 123                 sdhci_readl(host, SDHCI_PRESENT_STATE),
 124                 sdhci_readb(host, SDHCI_HOST_CONTROL));
 125         pr_err(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
 126                 sdhci_readb(host, SDHCI_POWER_CONTROL),
 127                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
 128         pr_err(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
 129                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
 130                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
 131         pr_err(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
 132                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
 133                 sdhci_readl(host, SDHCI_INT_STATUS));
 134         pr_err(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
 135                 sdhci_readl(host, SDHCI_INT_ENABLE),
 136                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
 137         pr_err(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 138                 sdhci_readw(host, SDHCI_ACMD12_ERR),
 139                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
 140         pr_err(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
 141                 sdhci_readl(host, SDHCI_CAPABILITIES),
 142                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
 143         pr_err(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
 144                 sdhci_readw(host, SDHCI_COMMAND),
 145                 sdhci_readl(host, SDHCI_MAX_CURRENT));
 146         pr_err(DRIVER_NAME ": Host ctl2: 0x%08x\n",
 147                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
 148
 149         if (host->flags & SDHCI_USE_ADMA)
 150                 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
 151                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
 152                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 153
 154         pr_err(DRIVER_NAME ": ===========================================\n");
 155 }
 156
 157 /*****************************************************************************\
 158  *                                                                           *
 159  * Low level functions                                                       *
 160  *                                                                           *
 161 \*****************************************************************************/
 162
 163 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
 164 {
 165         u32 ier;
 166
 167         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 168         ier &= ~clear;
 169         ier |= set;
 170         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 171         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 172 }
 173
 174 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
 175 {
 176         sdhci_clear_set_irqs(host, 0, irqs);
 177 }
 178
 179 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
 180 {
 181         sdhci_clear_set_irqs(host, irqs, 0);
 182 }
 183
 184 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 185 {
 186         u32 present, irqs;
 187
 188         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 189             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
 190                 return;
 191
 192         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 193                               SDHCI_CARD_PRESENT;
 194         irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
 195
 196         if (enable)
 197                 sdhci_unmask_irqs(host, irqs);
 198         else
 199                 sdhci_mask_irqs(host, irqs);
 200 }
 201
 202 static void sdhci_enable_card_detection(struct sdhci_host *host)
 203 {
 204         sdhci_set_card_detection(host, true);
 205 }
 206
 207 static void sdhci_disable_card_detection(struct sdhci_host *host)
 208 {
 209         sdhci_set_card_detection(host, false);
 210 }
 211
 212 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 213 {
 214         u32 ctrl;
 215         unsigned long timeout;
 216         u32 uninitialized_var(ier);
 217
 218         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 219                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 220                         SDHCI_CARD_PRESENT))
 221                         return;
 222         }
 223
 224         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 225                 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 226
 227         if (host->ops->platform_reset_enter)
 228                 host->ops->platform_reset_enter(host, mask);
 229
 230         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 231
 232         if (mask & SDHCI_RESET_ALL)
 233                 host->clock = 0;
 234
 235         /* Wait max 100 ms */
 236         timeout = 100;
 237
 238         /* hw clears the bit when it's done */
 239         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 240                 if (timeout == 0) {
 241                         pr_err("%s: Reset 0x%x never completed.\n",
 242                                 mmc_hostname(host->mmc), (int)mask);
 243                         sdhci_dumpregs(host);
 244                         return;
 245                 }
 246                 timeout--;
 247                 mdelay(1);
 248         }
 249
 250         if (host->ops->platform_reset_exit)
 251                 host->ops->platform_reset_exit(host, mask);
 252
 253         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 254                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
 255
 256         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 257                 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
 258                         host->ops->enable_dma(host);
 259         }
 260
 261         /*
 262          * VERSION_4_EN bit and 64BIT_EN bit are cleared after a full reset
 263          * need to re-configure them after each full reset
 264          */
 265         if ((mask & SDHCI_RESET_ALL) && host->version >= SDHCI_SPEC_400) {
 266                 ctrl = sdhci_readl(host, SDHCI_ACMD12_ERR);
 267                 ctrl |= SDHCI_HOST_VERSION_4_EN;
 268                 if (host->quirks2 & SDHCI_QUIRK2_SUPPORT_64BIT_DMA)
 269                         ctrl |= SDHCI_ADDRESSING_64BIT_EN;
 270                 sdhci_writel(host, ctrl, SDHCI_ACMD12_ERR);
 271         }
 272 }
 273
 274 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 275
 276 static void sdhci_init(struct sdhci_host *host, int soft)
 277 {
 278         if (soft)
 279                 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 280         else
 281                 sdhci_reset(host, SDHCI_RESET_ALL);
 282
 283         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
 284                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 285                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 286                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 287                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
 288
 289         if (soft) {
 290                 /* force clock reconfiguration */
 291                 host->clock = 0;
 292                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 293         }
 294 }
 295
 296 static void sdhci_reinit(struct sdhci_host *host)
 297 {
 298         sdhci_init(host, 0);
 299         /*
 300          * Retuning stuffs are affected by different cards inserted and only
 301          * applicable to UHS-I cards. So reset these fields to their initial
 302          * value when card is removed.
 303          */
 304         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
 305                 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
 306
 307                 del_timer_sync(&host->tuning_timer);
 308                 host->flags &= ~SDHCI_NEEDS_RETUNING;
 309                 host->mmc->max_blk_count =
 310                         (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
 311         }
 312         sdhci_enable_card_detection(host);
 313 }
 314
 315 static void sdhci_activate_led(struct sdhci_host *host)
 316 {
 317         u8 ctrl;
 318
 319         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 320         ctrl |= SDHCI_CTRL_LED;
 321         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 322 }
 323
 324 static void sdhci_deactivate_led(struct sdhci_host *host)
 325 {
 326         u8 ctrl;
 327
 328         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 329         ctrl &= ~SDHCI_CTRL_LED;
 330         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 331 }
 332
 333 #ifdef SDHCI_USE_LEDS_CLASS
 334 static void sdhci_led_control(struct led_classdev *led,
 335         enum led_brightness brightness)
 336 {
 337         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 338         unsigned long flags;
 339
 340         spin_lock_irqsave(&host->lock, flags);
 341
 342         if (host->runtime_suspended)
 343                 goto out;
 344
 345         if (brightness == LED_OFF)
 346                 sdhci_deactivate_led(host);
 347         else
 348                 sdhci_activate_led(host);
 349 out:
 350         spin_unlock_irqrestore(&host->lock, flags);
 351 }
 352 #endif
 353
 354 /*****************************************************************************\
 355  *                                                                           *
 356  * Core functions                                                            *
 357  *                                                                           *
 358 \*****************************************************************************/
 359
 360 static void sdhci_read_block_pio(struct sdhci_host *host)
 361 {
 362         unsigned long flags;
 363         size_t blksize, len, chunk;
 364         u32 uninitialized_var(scratch);
 365         u8 *buf;
 366
 367         DBG("PIO reading\n");
 368
 369         blksize = host->data->blksz;
 370         chunk = 0;
 371
 372         local_irq_save(flags);
 373
 374         while (blksize) {
 375                 if (!sg_miter_next(&host->sg_miter))
 376                         BUG();
 377
 378                 len = min(host->sg_miter.length, blksize);
 379
 380                 blksize -= len;
 381                 host->sg_miter.consumed = len;
 382
 383                 buf = host->sg_miter.addr;
 384
 385                 while (len) {
 386                         if (chunk == 0) {
 387                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 388                                 chunk = 4;
 389                         }
 390
 391                         *buf = scratch & 0xFF;
 392
 393                         buf++;
 394                         scratch >>= 8;
 395                         chunk--;
 396                         len--;
 397                 }
 398         }
 399
 400         sg_miter_stop(&host->sg_miter);
 401
 402         local_irq_restore(flags);
 403 }
 404
 405 static void sdhci_write_block_pio(struct sdhci_host *host)
 406 {
 407         unsigned long flags;
 408         size_t blksize, len, chunk;
 409         u32 scratch;
 410         u8 *buf;
 411
 412         DBG("PIO writing\n");
 413
 414         blksize = host->data->blksz;
 415         chunk = 0;
 416         scratch = 0;
 417
 418         local_irq_save(flags);
 419
 420         while (blksize) {
 421                 if (!sg_miter_next(&host->sg_miter))
 422                         BUG();
 423
 424                 len = min(host->sg_miter.length, blksize);
 425
 426                 blksize -= len;
 427                 host->sg_miter.consumed = len;
 428
 429                 buf = host->sg_miter.addr;
 430
 431                 while (len) {
 432                         scratch |= (u32)*buf << (chunk * 8);
 433
 434                         buf++;
 435                         chunk++;
 436                         len--;
 437
 438                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 439                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 440                                 chunk = 0;
 441                                 scratch = 0;
 442                         }
 443                 }
 444         }
 445
 446         sg_miter_stop(&host->sg_miter);
 447
 448         local_irq_restore(flags);
 449 }
 450
 451 static void sdhci_transfer_pio(struct sdhci_host *host)
 452 {
 453         u32 mask;
 454
 455         BUG_ON(!host->data);
 456
 457         if (host->blocks == 0)
 458                 return;
 459
 460         if (host->data->flags & MMC_DATA_READ)
 461                 mask = SDHCI_DATA_AVAILABLE;
 462         else
 463                 mask = SDHCI_SPACE_AVAILABLE;
 464
 465         /*
 466          * Some controllers (JMicron JMB38x) mess up the buffer bits
 467          * for transfers < 4 bytes. As long as it is just one block,
 468          * we can ignore the bits.
 469          */
 470         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 471                 (host->data->blocks == 1))
 472                 mask = ~0;
 473
 474         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 475                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 476                         udelay(100);
 477
 478                 if (host->data->flags & MMC_DATA_READ)
 479                         sdhci_read_block_pio(host);
 480                 else
 481                         sdhci_write_block_pio(host);
 482
 483                 host->blocks--;
 484                 if (host->blocks == 0)
 485                         break;
 486         }
 487
 488         DBG("PIO transfer complete.\n");
 489 }
 490
 491 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 492 {
 493         local_irq_save(*flags);
 494         return kmap_atomic(sg_page(sg)) + sg->offset;
 495 }
 496
 497 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 498 {
 499         kunmap_atomic(buffer);
 500         local_irq_restore(*flags);
 501 }
 502
 503 static void sdhci_set_adma_desc(struct sdhci_host *host, u8 *desc,
 504                                 dma_addr_t addr, int len, unsigned cmd)
 505 {
 506         __le32 *dataddr = (__le32 __force *)(desc + 4);
 507         __le64 *dataddr64 = (__le64 __force *)(desc + 4);
 508         __le16 *cmdlen = (__le16 __force *)desc;
 509         u32 ctrl;
 510
 511         /* SDHCI specification says ADMA descriptors should be 4 byte
 512          * aligned, so using 16 or 32bit operations should be safe. */
 513
 514         cmdlen[0] = cpu_to_le16(cmd);
 515         cmdlen[1] = cpu_to_le16(len);
 516
 517         ctrl = sdhci_readl(host, SDHCI_ACMD12_ERR);
 518         if (ctrl & SDHCI_ADDRESSING_64BIT_EN)
 519                 dataddr64[0] = cpu_to_le64(addr);
 520         else
 521                 dataddr[0] = cpu_to_le32(addr);
 522 }
 523
 524 static int sdhci_adma_table_pre(struct sdhci_host *host,
 525         struct mmc_data *data)
 526 {
 527         int direction;
 528
 529         u8 *desc;
 530         u8 *align;
 531         dma_addr_t addr;
 532         dma_addr_t align_addr;
 533         int len, offset;
 534
 535         struct scatterlist *sg;
 536         int i;
 537         char *buffer;
 538         unsigned long flags;
 539         int next_desc;
 540         u32 ctrl;
 541
 542         /*
 543          * The spec does not specify endianness of descriptor table.
 544          * We currently guess that it is LE.
 545          */
 546
 547         if (data->flags & MMC_DATA_READ)
 548                 direction = DMA_FROM_DEVICE;
 549         else
 550                 direction = DMA_TO_DEVICE;
 551
 552         /*
 553          * The ADMA descriptor table is mapped further down as we
 554          * need to fill it with data first.
 555          */
 556
 557         if (!host->use_dma_alloc) {
 558                 host->align_addr = dma_map_single(mmc_dev(host->mmc),
 559                         host->align_buffer, 128 * 8, direction);
 560                 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 561                         goto fail;
 562                 BUG_ON(host->align_addr & 0x3);
 563         }
 564
 565         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 566                 data->sg, data->sg_len, direction);
 567         if (host->sg_count == 0)
 568                 goto unmap_align;
 569
 570         desc = host->adma_desc;
 571         align = host->align_buffer;
 572
 573         align_addr = host->align_addr;
 574
 575         ctrl = sdhci_readl(host, SDHCI_ACMD12_ERR);
 576         if (ctrl & SDHCI_ADDRESSING_64BIT_EN) {
 577                 if (ctrl & SDHCI_HOST_VERSION_4_EN)
 578                         next_desc = 16;
 579                 else
 580                         next_desc = 12;
 581         } else {
 582                 /* 32 bit DMA mode supported */
 583                 next_desc = 8;
 584         }
 585
 586         for_each_sg(data->sg, sg, host->sg_count, i) {
 587                 addr = sg_dma_address(sg);
 588                 len = sg_dma_len(sg);
 589
 590                 /*
 591                  * The SDHCI specification states that ADMA
 592                  * addresses must be 32-bit aligned. If they
 593                  * aren't, then we use a bounce buffer for
 594                  * the (up to three) bytes that screw up the
 595                  * alignment.
 596                  */
 597                 offset = (4 - (addr & 0x3)) & 0x3;
 598                 if (offset) {
 599                         if (data->flags & MMC_DATA_WRITE) {
 600                                 buffer = sdhci_kmap_atomic(sg, &flags);
 601                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 602                                 memcpy(align, buffer, offset);
 603                                 sdhci_kunmap_atomic(buffer, &flags);
 604                         }
 605
 606                         /* tran, valid */
 607                         sdhci_set_adma_desc(host, desc, align_addr, offset,
 608                                                 0x21);
 609
 610                         BUG_ON(offset > 65536);
 611
 612                         align += 4;
 613                         align_addr += 4;
 614
 615                         desc += next_desc;
 616
 617                         addr += offset;
 618                         len -= offset;
 619                 }
 620
 621                 BUG_ON(len > 65536);
 622
 623                 /* tran, valid */
 624                 sdhci_set_adma_desc(host, desc, addr, len, 0x21);
 625                 desc += next_desc;
 626
 627                 /*
 628                  * If this triggers then we have a calculation bug
 629                  * somewhere. :/
 630                  */
 631                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 8);
 632         }
 633
 634         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 635                 /*
 636                 * Mark the last descriptor as the terminating descriptor
 637                 */
 638                 if (desc != host->adma_desc) {
 639                         desc -= next_desc;
 640                         desc[0] |= 0x2; /* end */
 641                 }
 642         } else {
 643                 /*
 644                 * Add a terminating entry.
 645                 */
 646
 647                 /* nop, end, valid */
 648                 sdhci_set_adma_desc(host, desc, 0, 0, 0x3);
 649         }
 650
 651         /*
 652          * Resync align buffer as we might have changed it.
 653          */
 654         if (data->flags & MMC_DATA_WRITE) {
 655                 dma_sync_single_for_device(mmc_dev(host->mmc),
 656                         host->align_addr, 128 * 8, direction);
 657         }
 658
 659         if (!host->use_dma_alloc) {
 660                 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
 661                         host->adma_desc, (128 * 2 + 1) * 8, DMA_TO_DEVICE);
 662                 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
 663                         goto unmap_entries;
 664                 BUG_ON(host->adma_addr & 0x3);
 665         }
 666
 667         return 0;
 668
 669 unmap_entries:
 670         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 671                 data->sg_len, direction);
 672 unmap_align:
 673         if (!host->use_dma_alloc)
 674                 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 675                                 128 * 8, direction);
 676 fail:
 677         return -EINVAL;
 678 }
 679
 680 static void sdhci_adma_table_post(struct sdhci_host *host,
 681         struct mmc_data *data)
 682 {
 683         int direction;
 684
 685         struct scatterlist *sg;
 686         int i, size;
 687         u8 *align;
 688         char *buffer;
 689         unsigned long flags;
 690
 691         if (data->flags & MMC_DATA_READ)
 692                 direction = DMA_FROM_DEVICE;
 693         else
 694                 direction = DMA_TO_DEVICE;
 695
 696         if (!host->use_dma_alloc) {
 697                 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
 698                         (128 * 2 + 1) * 8, DMA_TO_DEVICE);
 699
 700                 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 701                         128 * 8, direction);
 702         }
 703
 704         if (data->flags & MMC_DATA_READ) {
 705                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 706                         data->sg_len, direction);
 707
 708                 align = host->align_buffer;
 709
 710                 for_each_sg(data->sg, sg, host->sg_count, i) {
 711                         if (sg_dma_address(sg) & 0x3) {
 712                                 size = 4 - (sg_dma_address(sg) & 0x3);
 713
 714                                 buffer = sdhci_kmap_atomic(sg, &flags);
 715                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 716                                 memcpy(buffer, align, size);
 717                                 sdhci_kunmap_atomic(buffer, &flags);
 718
 719                                 align += 4;
 720                         }
 721                 }
 722         }
 723
 724         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 725                 data->sg_len, direction);
 726 }
 727
 728 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 729 {
 730         u8 count;
 731         struct mmc_data *data = cmd->data;
 732         unsigned target_timeout, current_timeout;
 733
 734         /*
 735          * If the host controller provides us with an incorrect timeout
 736          * value, just skip the check and use 0xE.  The hardware may take
 737          * longer to time out, but that's much better than having a too-short
 738          * timeout value.
 739          */
 740         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 741                 return 0xE;
 742
 743         /* Unspecified timeout, assume max */
 744         if (!data && !cmd->cmd_timeout_ms)
 745                 return 0xE;
 746
 747         /* timeout in us */
 748         if (!data)
 749                 target_timeout = cmd->cmd_timeout_ms * 1000;
 750         else {
 751                 target_timeout = data->timeout_ns / 1000;
 752                 if (host->clock)
 753                         target_timeout += data->timeout_clks / host->clock;
 754         }
 755
 756         /*
 757          * Figure out needed cycles.
 758          * We do this in steps in order to fit inside a 32 bit int.
 759          * The first step is the minimum timeout, which will have a
 760          * minimum resolution of 6 bits:
 761          * (1) 2^13*1000 > 2^22,
 762          * (2) host->timeout_clk < 2^16
 763          *     =>
 764          *     (1) / (2) > 2^6
 765          */
 766         count = 0;
 767         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 768         while (current_timeout < target_timeout) {
 769                 count++;
 770                 current_timeout <<= 1;
 771                 if (count >= 0xF)
 772                         break;
 773         }
 774
 775         if (count >= 0xF) {
 776                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
 777                     mmc_hostname(host->mmc), count, cmd->opcode);
 778                 count = 0xE;
 779         }
 780
 781         return count;
 782 }
 783
 784 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 785 {
 786         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 787         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 788
 789         if (host->flags & SDHCI_REQ_USE_DMA)
 790                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
 791         else
 792                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
 793 }
 794
 795 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 796 {
 797         u8 count;
 798         u8 ctrl;
 799         struct mmc_data *data = cmd->data;
 800         int ret;
 801
 802         WARN_ON(host->data);
 803
 804         if (data || (cmd->flags & MMC_RSP_BUSY)) {
 805                 count = sdhci_calc_timeout(host, cmd);
 806                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 807         }
 808
 809         if (!data)
 810                 return;
 811
 812         /* Sanity checks */
 813         BUG_ON(data->blksz * data->blocks > 524288);
 814         BUG_ON(data->blksz > host->mmc->max_blk_size);
 815         BUG_ON(data->blocks > 65535);
 816
 817         host->data = data;
 818         host->data_early = 0;
 819         host->data->bytes_xfered = 0;
 820
 821         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 822                 host->flags |= SDHCI_REQ_USE_DMA;
 823
 824         /*
 825          * FIXME: This doesn't account for merging when mapping the
 826          * scatterlist.
 827          */
 828         if (host->flags & SDHCI_REQ_USE_DMA) {
 829                 int broken, i;
 830                 struct scatterlist *sg;
 831
 832                 broken = 0;
 833                 if (host->flags & SDHCI_USE_ADMA) {
 834                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 835                                 broken = 1;
 836                 } else {
 837                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 838                                 broken = 1;
 839                 }
 840
 841                 if (unlikely(broken)) {
 842                         for_each_sg(data->sg, sg, data->sg_len, i) {
 843                                 if (sg->length & 0x3) {
 844                                         DBG("Reverting to PIO because of "
 845                                                 "transfer size (%d)\n",
 846                                                 sg->length);
 847                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 848                                         break;
 849                                 }
 850                         }
 851                 }
 852         }
 853
 854         /*
 855          * The assumption here being that alignment is the same after
 856          * translation to device address space.
 857          */
 858         if (host->flags & SDHCI_REQ_USE_DMA) {
 859                 int broken, i;
 860                 struct scatterlist *sg;
 861
 862                 broken = 0;
 863                 if (host->flags & SDHCI_USE_ADMA) {
 864                         /*
 865                          * As we use 3 byte chunks to work around
 866                          * alignment problems, we need to check this
 867                          * quirk.
 868                          */
 869                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 870                                 broken = 1;
 871                 } else {
 872                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 873                                 broken = 1;
 874                 }
 875
 876                 if (unlikely(broken)) {
 877                         for_each_sg(data->sg, sg, data->sg_len, i) {
 878                                 if (sg->offset & 0x3) {
 879                                         DBG("Reverting to PIO because of "
 880                                                 "bad alignment\n");
 881                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 882                                         break;
 883                                 }
 884                         }
 885                 }
 886         }
 887
 888         if (host->flags & SDHCI_REQ_USE_DMA) {
 889                 if (host->flags & SDHCI_USE_ADMA) {
 890                         ret = sdhci_adma_table_pre(host, data);
 891                         if (ret) {
 892                                 /*
 893                                  * This only happens when someone fed
 894                                  * us an invalid request.
 895                                  */
 896                                 WARN_ON(1);
 897                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 898                         } else {
 899                                 sdhci_writel(host,
 900                                         (host->adma_addr & 0xFFFFFFFF),
 901                                         SDHCI_ADMA_ADDRESS);
 902
 903                                 if ((host->version >= SDHCI_SPEC_400) &&
 904                                     (host->quirks2 &
 905                                      SDHCI_QUIRK2_SUPPORT_64BIT_DMA)) {
 906                                         if (host->quirks2 &
 907                                             SDHCI_QUIRK2_USE_64BIT_ADDR) {
 908
 909                                                 sdhci_writel(host,
 910                                                 (host->adma_addr >> 32)
 911                                                         & 0xFFFFFFFF,
 912                                                 SDHCI_UPPER_ADMA_ADDRESS);
 913                                         } else {
 914                                                 sdhci_writel(host, 0,
 915                                                 SDHCI_UPPER_ADMA_ADDRESS);
 916                                         }
 917                                 }
 918                         }
 919                 } else {
 920                         int sg_cnt;
 921
 922                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
 923                                         data->sg, data->sg_len,
 924                                         (data->flags & MMC_DATA_READ) ?
 925                                                 DMA_FROM_DEVICE :
 926                                                 DMA_TO_DEVICE);
 927                         if (sg_cnt == 0) {
 928                                 /*
 929                                  * This only happens when someone fed
 930                                  * us an invalid request.
 931                                  */
 932                                 WARN_ON(1);
 933                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 934                         } else {
 935                                 WARN_ON(sg_cnt != 1);
 936                                 sdhci_writel(host, sg_dma_address(data->sg),
 937                                         SDHCI_DMA_ADDRESS);
 938                         }
 939                 }
 940         }
 941
 942         /*
 943          * Always adjust the DMA selection as some controllers
 944          * (e.g. JMicron) can't do PIO properly when the selection
 945          * is ADMA.
 946          */
 947         if (host->version >= SDHCI_SPEC_200) {
 948                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 949                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 950                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 951                         (host->flags & SDHCI_USE_ADMA))
 952                         ctrl |= SDHCI_CTRL_ADMA2;
 953                 else
 954                         ctrl |= SDHCI_CTRL_SDMA;
 955                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 956         }
 957
 958         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 959                 int flags;
 960
 961                 flags = SG_MITER_ATOMIC;
 962                 if (host->data->flags & MMC_DATA_READ)
 963                         flags |= SG_MITER_TO_SG;
 964                 else
 965                         flags |= SG_MITER_FROM_SG;
 966                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 967                 host->blocks = data->blocks;
 968         }
 969
 970         sdhci_set_transfer_irqs(host);
 971
 972         /* Set the DMA boundary value and block size */
 973         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 974                 data->blksz), SDHCI_BLOCK_SIZE);
 975         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 976 }
 977
 978 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 979         struct mmc_command *cmd)
 980 {
 981         u16 mode;
 982         struct mmc_data *data = cmd->data;
 983
 984         if (data == NULL)
 985                 return;
 986
 987         WARN_ON(!host->data);
 988
 989         mode = SDHCI_TRNS_BLK_CNT_EN;
 990         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 991                 mode |= SDHCI_TRNS_MULTI;
 992                 /*
 993                  * If we are sending CMD23, CMD12 never gets sent
 994                  * on successful completion (so no Auto-CMD12).
 995                  */
 996                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
 997                         mmc_op_multi(cmd->opcode))
 998                         mode |= SDHCI_TRNS_AUTO_CMD12;
 999                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
1000                         mode |= SDHCI_TRNS_AUTO_CMD23;
1001                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
1002                 }
1003         }
1004
1005         if (data->flags & MMC_DATA_READ)
1006                 mode |= SDHCI_TRNS_READ;
1007         if (host->flags & SDHCI_REQ_USE_DMA)
1008                 mode |= SDHCI_TRNS_DMA;
1009
1010         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1011 }
1012
1013 #ifdef CONFIG_DEBUG_FS
1014 static void get_kbps_from_size_n_usec_32bit(
1015                 u32 size_in_bits_x1000, u32 time_usecs,
1016                 u32 *speed_in_kbps)
1017 {
1018         *speed_in_kbps = DIV_ROUND_CLOSEST(size_in_bits_x1000, time_usecs);
1019 }
1020
1021 static void get_kbps_from_size_n_usec_64bit(
1022                 u64 size_in_bits_x1000, u32 time_usecs,
1023                 u32 *speed_in_kbps)
1024 {
1025         u32 speed_32bit;
1026         u64 cp_size_bits_x1000;
1027         u32 cp_usecs;
1028         int i;
1029
1030         cp_size_bits_x1000 = size_in_bits_x1000;
1031         cp_usecs = time_usecs;
1032         /* convert 64 bit into 32 bits */
1033         i = 0;
1034         while (!(IS_32_BIT(cp_size_bits_x1000) && IS_32_BIT(cp_usecs))) {
1035                 /* shift right both the operands bytes and time */
1036                 cp_size_bits_x1000 >>= 1;
1037                 cp_usecs >>= 1;
1038                 i++;
1039         }
1040         if (i)
1041                 pr_debug("%s right shifted operands by %d, size=%lld, time=%d usec\n",
1042                         __func__, i, size_in_bits_x1000, time_usecs);
1043         /* check for 32 bit operations first */
1044         get_kbps_from_size_n_usec_32bit(
1045                 (u32)cp_size_bits_x1000, cp_usecs,
1046                 &speed_32bit);
1047         *speed_in_kbps = speed_32bit;
1048         return;
1049 }
1050
1051 static void free_stats_nodes(struct sdhci_host *host)
1052 {
1053         struct data_stat_entry *ptr, *ptr2;
1054
1055         ptr = host->sdhci_data_stat.head;
1056         while (ptr) {
1057                 ptr2 = ptr->next;
1058                 host->sdhci_data_stat.stat_size--;
1059                 kfree(ptr);
1060                 ptr = ptr2;
1061         }
1062         if (host->sdhci_data_stat.stat_size)
1063                 pr_err("stat_size=%d after free %s\n",
1064                         host->sdhci_data_stat.stat_size,
1065                         __func__);
1066 }
1067
1068 static struct data_stat_entry *add_entry_sorted(struct sdhci_host *host,
1069         unsigned int blk_size, unsigned int blk_count)
1070 {
1071         struct data_stat_entry *node, *ptr;
1072
1073         node = devm_kzalloc(host->mmc->parent, sizeof(struct data_stat_entry),
1074                 GFP_KERNEL);
1075         if (!node) {
1076                 pr_err("%s, %s, line=%d: unable to allocate data_stat_entry\n",
1077                         __FILE__, __func__, __LINE__);
1078                 return NULL;
1079         }
1080         node->stat_blk_size = blk_size;
1081         node->stat_blks_per_transfer = blk_count;
1082         host->sdhci_data_stat.stat_size++;
1083         /* assume existing list is sorted and try to insert this new node
1084          * into the increasing order sorted array
1085          */
1086         ptr = host->sdhci_data_stat.head;
1087         if (!ptr) {
1088                 /* first element */
1089                 host->sdhci_data_stat.head = node;
1090                 return node;
1091         }
1092         if (ptr && ((ptr->stat_blk_size > blk_size) ||
1093                 ((ptr->stat_blk_size == blk_size) &&
1094                 (ptr->stat_blks_per_transfer > blk_count)))) {
1095                 host->sdhci_data_stat.head = node;
1096                 /* update new head */
1097                 node->next = ptr;
1098                 return node;
1099         }
1100         while (ptr->next) {
1101                 if ((ptr->next->stat_blk_size < blk_size) ||
1102                         ((ptr->next->stat_blk_size == blk_size) &&
1103                         (ptr->next->stat_blks_per_transfer < blk_count)))
1104                         ptr = ptr->next;
1105                 else
1106                         break;
1107         }
1108         /* We are here if -
1109          * 1. ptr->next is null or
1110          * 2. blk_size of ptr->next is greater than new blk size, so we should
1111          *    place the new node between ptr and ptr->next
1112          */
1113         if (!ptr->next) {
1114                 ptr->next = node;
1115                 return node;
1116         }
1117         if ((ptr->next->stat_blk_size > blk_size) ||
1118                 ((ptr->next->stat_blk_size == blk_size) &&
1119                 (ptr->next->stat_blks_per_transfer > blk_count))) {
1120                 node->next = ptr->next;
1121                 ptr->next = node;
1122                 return node;
1123         }
1124         pr_err("%s line=%d should be unreachable\n", __func__, __LINE__);
1125         return NULL;
1126 }
1127
1128 static void free_data_entry(struct sdhci_host *host,
1129                                 unsigned int blk_size, unsigned int blk_count)
1130 {
1131         struct data_stat_entry *ptr, *ptr2;
1132
1133         ptr = host->sdhci_data_stat.head;
1134         if (!ptr)
1135                 return;
1136         if ((ptr->stat_blk_size == blk_size) &&
1137                 (ptr->stat_blks_per_transfer == blk_count)) {
1138                 host->sdhci_data_stat.head = ptr->next;
1139                 devm_kfree(host->mmc->parent, ptr);
1140                 return;
1141         }
1142         if ((!ptr->next) && ((ptr->stat_blk_size == blk_size) &&
1143                 (ptr->stat_blks_per_transfer == blk_count))) {
1144                 pr_err("Error %s: only data_entry found has blk_size=%d, given blk_size=%d not found\n",
1145                         __func__, ptr->stat_blk_size, blk_size);
1146                 return;
1147         }
1148         while (ptr->next) {
1149                 if ((ptr->next->stat_blk_size == blk_size) &&
1150                         (ptr->next->stat_blks_per_transfer == blk_count)) {
1151                         ptr2 = ptr->next->next;
1152                         devm_kfree(host->mmc->parent, ptr->next);
1153                         ptr->next = ptr2;
1154                         return;
1155                 }
1156                 ptr = ptr->next;
1157         }
1158         pr_err("Error %s: given blk_size=%d not found\n", __func__, blk_size);
1159         return;
1160 }
1161
1162 static void update_stat(struct sdhci_host *host, u32 blk_size, u8 blk_count,
1163                         bool is_start_stat, bool is_data_error)
1164 {
1165         u32 new_kbps;
1166         struct data_stat_entry *stat;
1167         ktime_t t;
1168
1169         if (!host->enable_sdhci_perf_stats)
1170                 return;
1171
1172         stat = host->sdhci_data_stat.head;
1173         while (stat) {
1174                 if ((stat->stat_blk_size == blk_size) &&
1175                         (stat->stat_blks_per_transfer == blk_count))
1176                         break;
1177                 stat = stat->next;
1178         }
1179         if (!stat) {
1180                 /* allocate an entry */
1181                 stat = add_entry_sorted(host, blk_size, blk_count);
1182                 if (!stat) {
1183                         pr_err("%s line=%d: stat entry not found\n",
1184                                 __func__, __LINE__);
1185                         return;
1186                 }
1187         }
1188
1189         if (is_start_stat) {
1190                 stat->start_ktime = ktime_get();
1191         } else {
1192                 if (is_data_error) {
1193                         memset(&stat->start_ktime, 0, sizeof(ktime_t));
1194                         if (!stat->total_bytes)
1195                                 free_data_entry(host, blk_size, blk_count);
1196                         return;
1197                 }
1198                 t = ktime_get();
1199                 stat->duration_usecs = ktime_us_delta(t, stat->start_ktime);
1200                 stat->current_transferred_bytes = (blk_size * blk_count);
1201                 get_kbps_from_size_n_usec_32bit(
1202                         (((u32)stat->current_transferred_bytes << 3) * 1000),
1203                         stat->duration_usecs,
1204                         &new_kbps);
1205                 if (stat->max_kbps == 0) {
1206                         stat->max_kbps = new_kbps;
1207                         stat->min_kbps = new_kbps;
1208                 } else {
1209                         if (new_kbps > stat->max_kbps)
1210                                 stat->max_kbps = new_kbps;
1211                         if (new_kbps < stat->min_kbps)
1212                                 stat->min_kbps = new_kbps;
1213                 }
1214                 /* update the total bytes figure for this entry */
1215                 stat->total_usecs += stat->duration_usecs;
1216                 stat->total_bytes += stat->current_transferred_bytes;
1217         }
1218 }
1219 #endif
1220
1221 static void sdhci_finish_data(struct sdhci_host *host)
1222 {
1223         struct mmc_data *data;
1224
1225         BUG_ON(!host->data);
1226
1227         data = host->data;
1228         host->data = NULL;
1229
1230         if (host->flags & SDHCI_REQ_USE_DMA) {
1231                 if (host->flags & SDHCI_USE_ADMA)
1232                         sdhci_adma_table_post(host, data);
1233                 else {
1234                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1235                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
1236                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
1237                 }
1238         }
1239
1240         /*
1241          * The specification states that the block count register must
1242          * be updated, but it does not specify at what point in the
1243          * data flow. That makes the register entirely useless to read
1244          * back so we have to assume that nothing made it to the card
1245          * in the event of an error.
1246          */
1247         if (data->error)
1248                 data->bytes_xfered = 0;
1249         else
1250                 data->bytes_xfered = data->blksz * data->blocks;
1251
1252         /*
1253          * Need to send CMD12 if -
1254          * a) open-ended multiblock transfer (no CMD23)
1255          * b) error in multiblock transfer
1256          */
1257         if (data->stop &&
1258             (data->error ||
1259              !host->mrq->sbc)) {
1260
1261                 /*
1262                  * The controller needs a reset of internal state machines
1263                  * upon error conditions.
1264                  */
1265                 if (data->error) {
1266                         sdhci_reset(host, SDHCI_RESET_CMD);
1267                         sdhci_reset(host, SDHCI_RESET_DATA);
1268                 }
1269
1270                 sdhci_send_command(host, data->stop);
1271         } else
1272                 tasklet_schedule(&host->finish_tasklet);
1273 #ifdef CONFIG_DEBUG_FS
1274         if (data->bytes_xfered) {
1275                 update_stat(host, data->blksz, data->blocks, false, false);
1276         } else {
1277                 host->no_data_transfer_count++;
1278                 /* performance stats does not include cases of data error */
1279                 update_stat(host, data->blksz, data->blocks, false, true);
1280         }
1281 #endif
1282 }
1283
1284 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1285 {
1286         int flags;
1287         u32 mask;
1288         unsigned long timeout;
1289
1290         WARN_ON(host->cmd);
1291
1292         /* Wait max 10 ms */
1293         timeout = 10;
1294
1295         mask = SDHCI_CMD_INHIBIT;
1296         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1297                 mask |= SDHCI_DATA_INHIBIT;
1298
1299         /* We shouldn't wait for data inihibit for stop commands, even
1300            though they might use busy signaling */
1301         if (host->mrq->data && (cmd == host->mrq->data->stop))
1302                 mask &= ~SDHCI_DATA_INHIBIT;
1303
1304         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1305                 if (timeout == 0) {
1306                         pr_err("%s: Controller never released "
1307                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1308                         sdhci_dumpregs(host);
1309                         cmd->error = -EIO;
1310                         tasklet_schedule(&host->finish_tasklet);
1311                         return;
1312                 }
1313                 timeout--;
1314                 mdelay(1);
1315         }
1316
1317         if ((cmd->opcode == MMC_SWITCH) &&
1318                 (((cmd->arg >> 16) & EXT_CSD_SANITIZE_START)
1319                 == EXT_CSD_SANITIZE_START))
1320                 timeout = 100;
1321         else
1322                 timeout = 10;
1323
1324         mod_timer(&host->timer, jiffies + timeout * HZ);
1325
1326         host->cmd = cmd;
1327
1328         sdhci_prepare_data(host, cmd);
1329
1330         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1331
1332         sdhci_set_transfer_mode(host, cmd);
1333
1334         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1335                 pr_err("%s: Unsupported response type!\n",
1336                         mmc_hostname(host->mmc));
1337                 cmd->error = -EINVAL;
1338                 tasklet_schedule(&host->finish_tasklet);
1339                 return;
1340         }
1341
1342         if (!(cmd->flags & MMC_RSP_PRESENT))
1343                 flags = SDHCI_CMD_RESP_NONE;
1344         else if (cmd->flags & MMC_RSP_136)
1345                 flags = SDHCI_CMD_RESP_LONG;
1346         else if (cmd->flags & MMC_RSP_BUSY)
1347                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1348         else
1349                 flags = SDHCI_CMD_RESP_SHORT;
1350
1351         if (cmd->flags & MMC_RSP_CRC)
1352                 flags |= SDHCI_CMD_CRC;
1353         if (cmd->flags & MMC_RSP_OPCODE)
1354                 flags |= SDHCI_CMD_INDEX;
1355
1356         /* CMD19, CMD21 is special in that the Data Present Select should be set */
1357         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1358             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1359                 flags |= SDHCI_CMD_DATA;
1360
1361         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1362 }
1363
1364 static void sdhci_finish_command(struct sdhci_host *host)
1365 {
1366         int i;
1367
1368         BUG_ON(host->cmd == NULL);
1369
1370         if (host->cmd->flags & MMC_RSP_PRESENT) {
1371                 if (host->cmd->flags & MMC_RSP_136) {
1372                         /* CRC is stripped so we need to do some shifting. */
1373                         for (i = 0;i < 4;i++) {
1374                                 host->cmd->resp[i] = sdhci_readl(host,
1375                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1376                                 if (i != 3)
1377                                         host->cmd->resp[i] |=
1378                                                 sdhci_readb(host,
1379                                                 SDHCI_RESPONSE + (3-i)*4-1);
1380                         }
1381                 } else {
1382                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1383                 }
1384         }
1385
1386         host->cmd->error = 0;
1387
1388         /* Finished CMD23, now send actual command. */
1389         if (host->cmd == host->mrq->sbc) {
1390                 host->cmd = NULL;
1391                 sdhci_send_command(host, host->mrq->cmd);
1392         } else {
1393
1394                 /* Processed actual command. */
1395                 if (host->data && host->data_early)
1396                         sdhci_finish_data(host);
1397
1398                 if (!host->cmd->data)
1399                         tasklet_schedule(&host->finish_tasklet);
1400
1401                 host->cmd = NULL;
1402         }
1403 }
1404
1405 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1406 {
1407         u16 ctrl, preset = 0;
1408
1409         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1410
1411         switch (ctrl & SDHCI_CTRL_UHS_MASK) {
1412         case SDHCI_CTRL_UHS_SDR12:
1413                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1414                 break;
1415         case SDHCI_CTRL_UHS_SDR25:
1416                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1417                 break;
1418         case SDHCI_CTRL_UHS_SDR50:
1419                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1420                 break;
1421         case SDHCI_CTRL_UHS_SDR104:
1422                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1423                 break;
1424         case SDHCI_CTRL_UHS_DDR50:
1425                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1426                 break;
1427         default:
1428                 pr_warn("%s: Invalid UHS-I mode selected\n",
1429                         mmc_hostname(host->mmc));
1430                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1431                 break;
1432         }
1433         return preset;
1434 }
1435
1436 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1437 {
1438         int div = 0; /* Initialized for compiler warning */
1439         int real_div = div, clk_mul = 1;
1440         u16 clk = 0;
1441         unsigned long timeout;
1442         u32 caps;
1443
1444         if (clock && clock == host->clock)
1445                 return;
1446
1447         host->mmc->actual_clock = 0;
1448
1449         if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1450                 return;
1451
1452         /*
1453          * If the entire clock control register is updated with zero, some
1454          * controllers might first update clock divisor fields and then update
1455          * the INT_CLK_EN and CARD_CLK_EN fields. Disable card clock first
1456          * to ensure there is no abnormal clock behavior.
1457          */
1458         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1459         clk &= ~SDHCI_CLOCK_CARD_EN;
1460         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1461         clk = 0;
1462         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1463
1464         if (clock == 0)
1465                 goto out;
1466
1467         if (host->version >= SDHCI_SPEC_300) {
1468                 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1469                         SDHCI_CTRL_PRESET_VAL_ENABLE) {
1470                         u16 pre_val;
1471
1472                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1473                         pre_val = sdhci_get_preset_value(host);
1474                         div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1475                                 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1476                         if (host->clk_mul &&
1477                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1478                                 clk = SDHCI_PROG_CLOCK_MODE;
1479                                 real_div = div + 1;
1480                                 clk_mul = host->clk_mul;
1481                         } else {
1482                                 real_div = max_t(int, 1, div << 1);
1483                         }
1484                         goto clock_set;
1485                 }
1486
1487                 /*
1488                  * Check if the Host Controller supports Programmable Clock
1489                  * Mode.
1490                  */
1491                 if (host->clk_mul) {
1492                         for (div = 1; div <= 1024; div++) {
1493                                 if ((host->max_clk * host->clk_mul / div)
1494                                         <= clock)
1495                                         break;
1496                         }
1497                         /*
1498                          * Set Programmable Clock Mode in the Clock
1499                          * Control register.
1500                          */
1501                         clk = SDHCI_PROG_CLOCK_MODE;
1502                         real_div = div;
1503                         clk_mul = host->clk_mul;
1504                         div--;
1505                 } else {
1506                         /* Version 3.00 divisors must be a multiple of 2. */
1507                         if (host->max_clk <= clock) {
1508                                 if (host->mmc->ios.timing ==
1509                                         MMC_TIMING_UHS_DDR50)
1510                                         div = 2;
1511                                 else
1512                                         div = 1;
1513                         } else {
1514                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1515                                      div += 2) {
1516                                         if ((host->max_clk / div) <= clock)
1517                                                 break;
1518                                 }
1519                         }
1520                         real_div = div;
1521                         div >>= 1;
1522                 }
1523         } else {
1524                 /* Version 2.00 divisors must be a power of 2. */
1525                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1526                         if ((host->max_clk / div) <= clock)
1527                                 break;
1528                 }
1529                 real_div = div;
1530                 div >>= 1;
1531         }
1532
1533 clock_set:
1534         if (real_div)
1535                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1536
1537 #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT
1538         if (tegra_platform_is_fpga() && clock > 400000)
1539                 div = 1;
1540 #endif
1541         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1542         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1543                 << SDHCI_DIVIDER_HI_SHIFT;
1544         clk |= SDHCI_CLOCK_INT_EN;
1545         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1546
1547         /*
1548          * For Tegra3 sdmmc controller, internal clock will not be stable bit
1549          * will get set only after some other register write is done. To
1550          * handle, do a dummy reg write to the caps reg if
1551          * SDHCI_QUIRK2_INT_CLK_STABLE_REQ_DUMMY_REG_WRITE is set.
1552          */
1553         if (host->quirks2 & SDHCI_QUIRK2_INT_CLK_STABLE_REQ_DUMMY_REG_WRITE) {
1554                 udelay(5);
1555
1556                 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
1557                 caps |= 1;
1558                 sdhci_writel(host, caps, SDHCI_CAPABILITIES);
1559         }
1560
1561         /* Wait max 20 ms */
1562         timeout = 20;
1563         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1564                 & SDHCI_CLOCK_INT_STABLE)) {
1565                 if (timeout == 0) {
1566                         pr_err("%s: Internal clock never "
1567                                 "stabilised.\n", mmc_hostname(host->mmc));
1568                         sdhci_dumpregs(host);
1569                         return;
1570                 }
1571                 timeout--;
1572                 mdelay(1);
1573         }
1574
1575         clk |= SDHCI_CLOCK_CARD_EN;
1576         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1577
1578 out:
1579         host->clock = clock;
1580 }
1581
1582 static inline void sdhci_update_clock(struct sdhci_host *host)
1583 {
1584         unsigned int clock;
1585
1586         clock = host->clock;
1587         host->clock = 0;
1588         if (host->ops->set_clock)
1589                 host->ops->set_clock(host, clock);
1590         sdhci_set_clock(host, clock);
1591 }
1592
1593 static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1594 {
1595         u8 pwr = 0;
1596
1597         if (power != (unsigned short)-1) {
1598                 switch (1 << power) {
1599                 case MMC_VDD_165_195:
1600                         pwr = SDHCI_POWER_180;
1601                         break;
1602                 case MMC_VDD_29_30:
1603                 case MMC_VDD_30_31:
1604                         pwr = SDHCI_POWER_300;
1605                         break;
1606                 case MMC_VDD_32_33:
1607                 case MMC_VDD_33_34:
1608                         pwr = SDHCI_POWER_330;
1609                         break;
1610                 default:
1611                         BUG();
1612                 }
1613         }
1614
1615         if (host->pwr == pwr)
1616                 return -1;
1617
1618         host->pwr = pwr;
1619
1620         if (pwr == 0) {
1621                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1622                 return 0;
1623         }
1624
1625         /*
1626          * Spec says that we should clear the power reg before setting
1627          * a new value. Some controllers don't seem to like this though.
1628          */
1629         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1630                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1631
1632         /*
1633          * At least the Marvell CaFe chip gets confused if we set the voltage
1634          * and set turn on power at the same time, so set the voltage first.
1635          */
1636         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1637                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1638
1639         pwr |= SDHCI_POWER_ON;
1640
1641         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1642
1643         /*
1644          * Some controllers need an extra 10ms delay of 10ms before they
1645          * can apply clock after applying power
1646          */
1647         if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1648                 mdelay(10);
1649
1650         return power;
1651 }
1652
1653 /*****************************************************************************\
1654  *                                                                           *
1655  * MMC callbacks                                                             *
1656  *                                                                           *
1657 \*****************************************************************************/
1658
1659 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1660 {
1661         struct sdhci_host *host;
1662         int present;
1663         unsigned long flags;
1664         u32 tuning_opcode;
1665
1666         host = mmc_priv(mmc);
1667
1668 #ifdef CONFIG_DEBUG_FS
1669         if (mrq->data)
1670                 update_stat(host, mrq->data->blksz, mrq->data->blocks,
1671                         true, false);
1672 #endif
1673
1674         sdhci_runtime_pm_get(host);
1675
1676         spin_lock_irqsave(&host->lock, flags);
1677
1678         WARN_ON(host->mrq != NULL);
1679
1680 #ifndef SDHCI_USE_LEDS_CLASS
1681         sdhci_activate_led(host);
1682 #endif
1683
1684         /*
1685          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1686          * requests if Auto-CMD12 is enabled.
1687          */
1688         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1689                 if (mrq->stop) {
1690                         mrq->data->stop = NULL;
1691                         mrq->stop = NULL;
1692                 }
1693         }
1694
1695         host->mrq = mrq;
1696
1697         /*
1698          * Firstly check card presence from cd-gpio.  The return could
1699          * be one of the following possibilities:
1700          *     negative: cd-gpio is not available
1701          *     zero: cd-gpio is used, and card is removed
1702          *     one: cd-gpio is used, and card is present
1703          */
1704         present = mmc_gpio_get_cd(host->mmc);
1705         if (present < 0) {
1706                 /* If polling, assume that the card is always present. */
1707                 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1708                         if (host->ops->get_cd)
1709                                 present = host->ops->get_cd(host);
1710                         else
1711                                 present = 1;
1712                 else
1713                         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1714                                         SDHCI_CARD_PRESENT;
1715         }
1716
1717         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1718                 host->mrq->cmd->error = -ENOMEDIUM;
1719                 tasklet_schedule(&host->finish_tasklet);
1720         } else {
1721                 u32 present_state;
1722
1723                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1724                 /*
1725                  * Check if the re-tuning timer has already expired and there
1726                  * is no on-going data transfer. If so, we need to execute
1727                  * tuning procedure before sending command.
1728                  */
1729                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1730                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1731                         if (mmc->card) {
1732                                 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1733                                 tuning_opcode =
1734                                         mmc->card->type == MMC_TYPE_MMC ?
1735                                         MMC_SEND_TUNING_BLOCK_HS200 :
1736                                         MMC_SEND_TUNING_BLOCK;
1737                                 spin_unlock_irqrestore(&host->lock, flags);
1738                                 sdhci_execute_tuning(mmc, tuning_opcode);
1739                                 spin_lock_irqsave(&host->lock, flags);
1740
1741                                 /* Restore original mmc_request structure */
1742                                 host->mrq = mrq;
1743                         }
1744                 }
1745
1746                 /* For a data cmd, check for plat specific preparation */
1747                 spin_unlock_irqrestore(&host->lock, flags);
1748                 if (mrq->data)
1749                         host->ops->platform_get_bus(host);
1750                 spin_lock_irqsave(&host->lock, flags);
1751
1752                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1753                         sdhci_send_command(host, mrq->sbc);
1754                 else
1755                         sdhci_send_command(host, mrq->cmd);
1756         }
1757
1758         mmiowb();
1759         spin_unlock_irqrestore(&host->lock, flags);
1760 }
1761
1762 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1763 {
1764         unsigned long flags;
1765         int vdd_bit = -1;
1766         u8 ctrl;
1767
1768         /* cancel delayed clk gate work */
1769         cancel_delayed_work_sync(&host->delayed_clk_gate_wrk);
1770
1771         /* Do any required preparations prior to setting ios */
1772         if (host->ops->platform_ios_config_enter)
1773                 host->ops->platform_ios_config_enter(host, ios);
1774
1775         spin_lock_irqsave(&host->lock, flags);
1776
1777         if (host->flags & SDHCI_DEVICE_DEAD) {
1778                 spin_unlock_irqrestore(&host->lock, flags);
1779                 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1780                         mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1781                 return;
1782         }
1783
1784         /*
1785          * Reset the chip on each power off.
1786          * Should clear out any weird states.
1787          */
1788         if (ios->power_mode == MMC_POWER_OFF) {
1789                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1790                 sdhci_reinit(host);
1791         }
1792
1793         if (host->version >= SDHCI_SPEC_300 &&
1794                 (ios->power_mode == MMC_POWER_UP))
1795                 sdhci_enable_preset_value(host, false);
1796
1797         if (ios->power_mode == MMC_POWER_OFF)
1798                 vdd_bit = sdhci_set_power(host, -1);
1799         else
1800                 vdd_bit = sdhci_set_power(host, ios->vdd);
1801
1802         if (host->vmmc && vdd_bit != -1) {
1803                 spin_unlock_irqrestore(&host->lock, flags);
1804                 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1805                 spin_lock_irqsave(&host->lock, flags);
1806         }
1807
1808         sdhci_set_clock(host, ios->clock);
1809
1810         if (host->ops->platform_send_init_74_clocks)
1811                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1812
1813         /*
1814          * If your platform has 8-bit width support but is not a v3 controller,
1815          * or if it requires special setup code, you should implement that in
1816          * platform_bus_width().
1817          */
1818         if (host->ops->platform_bus_width) {
1819                 host->ops->platform_bus_width(host, ios->bus_width);
1820         } else {
1821                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1822                 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1823                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1824                         if (host->version >= SDHCI_SPEC_300)
1825                                 ctrl |= SDHCI_CTRL_8BITBUS;
1826                 } else {
1827                         if (host->version >= SDHCI_SPEC_300)
1828                                 ctrl &= ~SDHCI_CTRL_8BITBUS;
1829                         if (ios->bus_width == MMC_BUS_WIDTH_4)
1830                                 ctrl |= SDHCI_CTRL_4BITBUS;
1831                         else
1832                                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1833                 }
1834                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1835         }
1836
1837         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1838
1839         if ((ios->timing == MMC_TIMING_SD_HS ||
1840              ios->timing == MMC_TIMING_MMC_HS)
1841             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1842                 ctrl |= SDHCI_CTRL_HISPD;
1843         else
1844                 ctrl &= ~SDHCI_CTRL_HISPD;
1845
1846         if (host->version >= SDHCI_SPEC_300) {
1847                 u16 clk, ctrl_2;
1848
1849                 /* In case of UHS-I modes, set High Speed Enable */
1850                 if (((ios->timing == MMC_TIMING_MMC_HS200) ||
1851                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
1852                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1853                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1854                     (ios->timing == MMC_TIMING_UHS_SDR25))
1855                     && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1856                         ctrl |= SDHCI_CTRL_HISPD;
1857
1858                 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1859                 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1860                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1861                         /*
1862                          * We only need to set Driver Strength if the
1863                          * preset value enable is not set.
1864                          */
1865                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1866                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1867                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1868                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1869                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1870
1871                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1872                 } else {
1873                         /*
1874                          * According to SDHC Spec v3.00, if the Preset Value
1875                          * Enable in the Host Control 2 register is set, we
1876                          * need to reset SD Clock Enable before changing High
1877                          * Speed Enable to avoid generating clock gliches.
1878                          */
1879
1880                         /* Reset SD Clock Enable */
1881                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1882                         clk &= ~SDHCI_CLOCK_CARD_EN;
1883                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1884
1885                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1886
1887                         /* Re-enable SD Clock */
1888                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1889                         clk |= SDHCI_CLOCK_CARD_EN;
1890                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1891                 }
1892
1893
1894                 /* Reset SD Clock Enable */
1895                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1896                 clk &= ~SDHCI_CLOCK_CARD_EN;
1897                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1898
1899                 if (host->ops->set_uhs_signaling)
1900                         host->ops->set_uhs_signaling(host, ios->timing);
1901                 else {
1902                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1903                         /* Select Bus Speed Mode for host */
1904                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1905                         if (ios->timing == MMC_TIMING_MMC_HS200)
1906                                 ctrl_2 |= SDHCI_CTRL_HS_SDR200;
1907                         else if (ios->timing == MMC_TIMING_UHS_SDR12)
1908                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1909                         else if (ios->timing == MMC_TIMING_UHS_SDR25)
1910                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1911                         else if (ios->timing == MMC_TIMING_UHS_SDR50)
1912                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1913                         else if (ios->timing == MMC_TIMING_UHS_SDR104)
1914                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1915                         else if (ios->timing == MMC_TIMING_UHS_DDR50)
1916                                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1917                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1918                 }
1919
1920                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1921                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1922                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
1923                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
1924                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
1925                                  (ios->timing == MMC_TIMING_UHS_DDR50))) {
1926                         u16 preset;
1927
1928                         sdhci_enable_preset_value(host, true);
1929                         preset = sdhci_get_preset_value(host);
1930                         ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1931                                 >> SDHCI_PRESET_DRV_SHIFT;
1932                 }
1933
1934                 /* Re-enable SD Clock */
1935                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1936                 clk |= SDHCI_CLOCK_CARD_EN;
1937                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1938         } else
1939                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1940
1941         /*
1942          * Some (ENE) controllers go apeshit on some ios operation,
1943          * signalling timeout and CRC errors even on CMD0. Resetting
1944          * it on each ios seems to solve the problem.
1945          */
1946         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1947                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1948
1949         mmiowb();
1950         spin_unlock_irqrestore(&host->lock, flags);
1951
1952         /* Platform specific handling post ios setting */
1953         if (host->ops->platform_ios_config_exit)
1954                 host->ops->platform_ios_config_exit(host, ios);
1955
1956 }
1957
1958 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1959 {
1960         struct sdhci_host *host = mmc_priv(mmc);
1961
1962         sdhci_runtime_pm_get(host);
1963         sdhci_do_set_ios(host, ios);
1964         sdhci_runtime_pm_put(host);
1965 }
1966
1967 static int sdhci_do_get_cd(struct sdhci_host *host)
1968 {
1969         int gpio_cd = mmc_gpio_get_cd(host->mmc);
1970
1971         if (host->flags & SDHCI_DEVICE_DEAD)
1972                 return 0;
1973
1974         /* If polling/nonremovable, assume that the card is always present. */
1975         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1976             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1977                 return 1;
1978
1979         /* Try slot gpio detect */
1980         if (!IS_ERR_VALUE(gpio_cd))
1981                 return !!gpio_cd;
1982
1983         /* Host native card detect */
1984         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1985 }
1986
1987 static int sdhci_get_cd(struct mmc_host *mmc)
1988 {
1989         struct sdhci_host *host = mmc_priv(mmc);
1990         int ret;
1991
1992         sdhci_runtime_pm_get(host);
1993         ret = sdhci_do_get_cd(host);
1994         sdhci_runtime_pm_put(host);
1995         return ret;
1996 }
1997
1998 static int sdhci_check_ro(struct sdhci_host *host)
1999 {
2000         unsigned long flags;
2001         int is_readonly;
2002
2003         spin_lock_irqsave(&host->lock, flags);
2004
2005         if (host->flags & SDHCI_DEVICE_DEAD)
2006                 is_readonly = 0;
2007         else if (host->ops->get_ro)
2008                 is_readonly = host->ops->get_ro(host);
2009         else
2010                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
2011                                 & SDHCI_WRITE_PROTECT);
2012
2013         spin_unlock_irqrestore(&host->lock, flags);
2014
2015         /* This quirk needs to be replaced by a callback-function later */
2016         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
2017                 !is_readonly : is_readonly;
2018 }
2019
2020 #define SAMPLE_COUNT    5
2021
2022 static int sdhci_do_get_ro(struct sdhci_host *host)
2023 {
2024         int i, ro_count;
2025
2026         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
2027                 return sdhci_check_ro(host);
2028
2029         ro_count = 0;
2030         for (i = 0; i < SAMPLE_COUNT; i++) {
2031                 if (sdhci_check_ro(host)) {
2032                         if (++ro_count > SAMPLE_COUNT / 2)
2033                                 return 1;
2034                 }
2035                 msleep(30);
2036         }
2037         return 0;
2038 }
2039
2040 static void sdhci_hw_reset(struct mmc_host *mmc)
2041 {
2042         struct sdhci_host *host = mmc_priv(mmc);
2043
2044         if (host->ops && host->ops->hw_reset)
2045                 host->ops->hw_reset(host);
2046 }
2047
2048 static int sdhci_get_ro(struct mmc_host *mmc)
2049 {
2050         struct sdhci_host *host = mmc_priv(mmc);
2051         int ret;
2052
2053         sdhci_runtime_pm_get(host);
2054         ret = sdhci_do_get_ro(host);
2055         sdhci_runtime_pm_put(host);
2056         return ret;
2057 }
2058
2059 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
2060 {
2061         if (host->flags & SDHCI_DEVICE_DEAD)
2062                 goto out;
2063
2064         if (enable)
2065                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
2066         else
2067                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
2068
2069         /* SDIO IRQ will be enabled as appropriate in runtime resume */
2070         if (host->runtime_suspended)
2071                 goto out;
2072
2073         if (enable)
2074                 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
2075         else
2076                 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
2077 out:
2078         mmiowb();
2079 }
2080
2081 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
2082 {
2083         struct sdhci_host *host = mmc_priv(mmc);
2084         unsigned long flags;
2085
2086         spin_lock_irqsave(&host->lock, flags);
2087         sdhci_enable_sdio_irq_nolock(host, enable);
2088         spin_unlock_irqrestore(&host->lock, flags);
2089 }
2090
2091 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
2092                                                 struct mmc_ios *ios)
2093 {
2094         u16 ctrl;
2095         int ret;
2096
2097         /*
2098          * Signal Voltage Switching is only applicable for Host Controllers
2099          * v3.00 and above.
2100          */
2101         if (host->version < SDHCI_SPEC_300)
2102                 return 0;
2103
2104         if (host->quirks2 & SDHCI_QUIRK2_NON_STD_VOLTAGE_SWITCHING) {
2105                 if (host->ops->switch_signal_voltage)
2106                         return host->ops->switch_signal_voltage(
2107                                 host, ios->signal_voltage);
2108         }
2109
2110         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2111
2112         switch (ios->signal_voltage) {
2113         case MMC_SIGNAL_VOLTAGE_330:
2114                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2115                 ctrl &= ~SDHCI_CTRL_VDD_180;
2116                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2117
2118                 if (host->vqmmc) {
2119                         ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
2120                         if (ret) {
2121                                 pr_warning("%s: Switching to 3.3V signalling voltage "
2122                                                 " failed\n", mmc_hostname(host->mmc));
2123                                 return -EIO;
2124                         }
2125                 }
2126                 /* Wait for 5ms */
2127                 usleep_range(5000, 5500);
2128
2129                 /* 3.3V regulator output should be stable within 5 ms */
2130                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2131                 if (!(ctrl & SDHCI_CTRL_VDD_180))
2132                         return 0;
2133
2134                 pr_warning("%s: 3.3V regulator output did not became stable\n",
2135                                 mmc_hostname(host->mmc));
2136
2137                 return -EAGAIN;
2138         case MMC_SIGNAL_VOLTAGE_180:
2139                 if (host->vqmmc) {
2140                         ret = regulator_set_voltage(host->vqmmc,
2141                                         1700000, 1950000);
2142                         if (ret) {
2143                                 pr_warning("%s: Switching to 1.8V signalling voltage "
2144                                                 " failed\n", mmc_hostname(host->mmc));
2145                                 return -EIO;
2146                         }
2147                 }
2148
2149                 /*
2150                  * Enable 1.8V Signal Enable in the Host Control2
2151                  * register
2152                  */
2153                 ctrl |= SDHCI_CTRL_VDD_180;
2154                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2155
2156                 /* Wait for 5ms */
2157                 usleep_range(5000, 5500);
2158
2159                 /* 1.8V regulator output should be stable within 5 ms */
2160                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2161                 if (ctrl & SDHCI_CTRL_VDD_180)
2162                         return 0;
2163
2164                 pr_warning("%s: 1.8V regulator output did not became stable\n",
2165                                 mmc_hostname(host->mmc));
2166
2167                 return -EAGAIN;
2168         case MMC_SIGNAL_VOLTAGE_120:
2169                 if (host->vqmmc) {
2170                         ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
2171                         if (ret) {
2172                                 pr_warning("%s: Switching to 1.2V signalling voltage "
2173                                                 " failed\n", mmc_hostname(host->mmc));
2174                                 return -EIO;
2175                         }
2176                 }
2177                 return 0;
2178         default:
2179                 /* No signal voltage switch required */
2180                 return 0;
2181         }
2182 }
2183
2184 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
2185         struct mmc_ios *ios)
2186 {
2187         struct sdhci_host *host = mmc_priv(mmc);
2188         int err;
2189
2190         if (host->version < SDHCI_SPEC_300)
2191                 return 0;
2192         sdhci_runtime_pm_get(host);
2193         err = sdhci_do_start_signal_voltage_switch(host, ios);
2194         /* Do any post voltage switch platform specific configuration */
2195         if  (host->ops->switch_signal_voltage_exit)
2196                 host->ops->switch_signal_voltage_exit(host,
2197                         ios->signal_voltage);
2198         sdhci_runtime_pm_put(host);
2199         return err;
2200 }
2201
2202 static int sdhci_card_busy(struct mmc_host *mmc)
2203 {
2204         struct sdhci_host *host = mmc_priv(mmc);
2205         u32 present_state;
2206
2207         sdhci_runtime_pm_get(host);
2208         /* Check whether DAT[3:0] is 0000 */
2209         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2210         sdhci_runtime_pm_put(host);
2211
2212         return !(present_state & SDHCI_DATA_LVL_MASK);
2213 }
2214
2215 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2216 {
2217         struct sdhci_host *host;
2218         u16 ctrl;
2219         u32 ier;
2220         int tuning_loop_counter = MAX_TUNING_LOOP;
2221         unsigned long timeout;
2222         int err = 0;
2223         bool requires_tuning_nonuhs = false;
2224
2225         host = mmc_priv(mmc);
2226
2227         sdhci_runtime_pm_get(host);
2228         disable_irq(host->irq);
2229
2230         if ((host->quirks2 & SDHCI_QUIRK2_NON_STANDARD_TUNING) &&
2231                 host->ops->execute_freq_tuning) {
2232                 err = host->ops->execute_freq_tuning(host, opcode);
2233                 enable_irq(host->irq);
2234                 sdhci_runtime_pm_put(host);
2235                 return err;
2236         }
2237
2238         spin_lock(&host->lock);
2239         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2240
2241         /*
2242          * The Host Controller needs tuning only in case of SDR104 mode
2243          * and for SDR50 mode when Use Tuning for SDR50 is set in the
2244          * Capabilities register.
2245          * If the Host Controller supports the HS200 mode then the
2246          * tuning function has to be executed.
2247          */
2248         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
2249             (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
2250              host->flags & SDHCI_HS200_NEEDS_TUNING))
2251                 requires_tuning_nonuhs = true;
2252
2253         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
2254             requires_tuning_nonuhs)
2255                 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2256         else {
2257                 spin_unlock(&host->lock);
2258                 enable_irq(host->irq);
2259                 sdhci_runtime_pm_put(host);
2260                 return 0;
2261         }
2262
2263         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2264
2265         /*
2266          * As per the Host Controller spec v3.00, tuning command
2267          * generates Buffer Read Ready interrupt, so enable that.
2268          *
2269          * Note: The spec clearly says that when tuning sequence
2270          * is being performed, the controller does not generate
2271          * interrupts other than Buffer Read Ready interrupt. But
2272          * to make sure we don't hit a controller bug, we _only_
2273          * enable Buffer Read Ready interrupt here.
2274          */
2275         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
2276         sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
2277
2278         /*
2279          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
2280          * of loops reaches 40 times or a timeout of 150ms occurs.
2281          */
2282         timeout = 150;
2283         do {
2284                 struct mmc_command cmd = {0};
2285                 struct mmc_request mrq = {NULL};
2286
2287                 if (!tuning_loop_counter && !timeout)
2288                         break;
2289
2290                 cmd.opcode = opcode;
2291                 cmd.arg = 0;
2292                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2293                 cmd.retries = 0;
2294                 cmd.data = NULL;
2295                 cmd.error = 0;
2296
2297                 mrq.cmd = &cmd;
2298                 host->mrq = &mrq;
2299
2300                 /*
2301                  * In response to CMD19, the card sends 64 bytes of tuning
2302                  * block to the Host Controller. So we set the block size
2303                  * to 64 here.
2304                  * In response to CMD21, the card sends 128 bytes of tuning
2305                  * block for MMC_BUS_WIDTH_8 and 64 bytes for MMC_BUS_WIDTH_4
2306                  * to the Host Controller. So we set the block size to 64 here.
2307                  */
2308                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
2309                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2310                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
2311                                              SDHCI_BLOCK_SIZE);
2312                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
2313                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2314                                              SDHCI_BLOCK_SIZE);
2315                 } else {
2316                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2317                                      SDHCI_BLOCK_SIZE);
2318                 }
2319
2320                 /*
2321                  * The tuning block is sent by the card to the host controller.
2322                  * So we set the TRNS_READ bit in the Transfer Mode register.
2323                  * This also takes care of setting DMA Enable and Multi Block
2324                  * Select in the same register to 0.
2325                  */
2326                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2327
2328                 sdhci_send_command(host, &cmd);
2329
2330                 host->cmd = NULL;
2331                 host->mrq = NULL;
2332
2333                 spin_unlock(&host->lock);
2334                 enable_irq(host->irq);
2335
2336                 /* Wait for Buffer Read Ready interrupt */
2337                 wait_event_interruptible_timeout(host->buf_ready_int,
2338                                         (host->tuning_done == 1),
2339                                         msecs_to_jiffies(50));
2340                 disable_irq(host->irq);
2341                 spin_lock(&host->lock);
2342
2343                 if (!host->tuning_done) {
2344                         pr_info(DRIVER_NAME ": Timeout waiting for "
2345                                 "Buffer Read Ready interrupt during tuning "
2346                                 "procedure, falling back to fixed sampling "
2347                                 "clock\n");
2348                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2349                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2350                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2351                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2352
2353                         err = -EIO;
2354                         goto out;
2355                 }
2356
2357                 host->tuning_done = 0;
2358
2359                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2360                 tuning_loop_counter--;
2361                 timeout--;
2362                 mdelay(1);
2363         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2364
2365         /*
2366          * The Host Driver has exhausted the maximum number of loops allowed,
2367          * so use fixed sampling frequency.
2368          */
2369         if (!tuning_loop_counter || !timeout) {
2370                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2371                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2372         } else {
2373                 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2374                         pr_info(DRIVER_NAME ": Tuning procedure"
2375                                 " failed, falling back to fixed sampling"
2376                                 " clock\n");
2377                         err = -EIO;
2378                 }
2379         }
2380
2381 out:
2382         /*
2383          * If this is the very first time we are here, we start the retuning
2384          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
2385          * flag won't be set, we check this condition before actually starting
2386          * the timer.
2387          */
2388         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2389             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
2390                 host->flags |= SDHCI_USING_RETUNING_TIMER;
2391                 mod_timer(&host->tuning_timer, jiffies +
2392                         host->tuning_count * HZ);
2393                 /* Tuning mode 1 limits the maximum data length to 4MB */
2394                 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2395         } else {
2396                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2397                 /* Reload the new initial value for timer */
2398                 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2399                         mod_timer(&host->tuning_timer, jiffies +
2400                                 host->tuning_count * HZ);
2401         }
2402
2403         /*
2404          * In case tuning fails, host controllers which support re-tuning can
2405          * try tuning again at a later time, when the re-tuning timer expires.
2406          * So for these controllers, we return 0. Since there might be other
2407          * controllers who do not have this capability, we return error for
2408          * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2409          * a retuning timer to do the retuning for the card.
2410          */
2411         if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2412                 err = 0;
2413
2414         sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
2415         spin_unlock(&host->lock);
2416         enable_irq(host->irq);
2417         sdhci_runtime_pm_put(host);
2418
2419         return err;
2420 }
2421
2422
2423 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2424 {
2425         u16 ctrl;
2426
2427         /* Host Controller v3.00 defines preset value registers */
2428         if (host->version < SDHCI_SPEC_300)
2429                 return;
2430
2431         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2432
2433         /*
2434          * We only enable or disable Preset Value if they are not already
2435          * enabled or disabled respectively. Otherwise, we bail out.
2436          */
2437         if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2438                 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2439                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2440                 host->flags |= SDHCI_PV_ENABLED;
2441         } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2442                 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2443                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2444                 host->flags &= ~SDHCI_PV_ENABLED;
2445         }
2446 }
2447
2448 static void sdhci_card_event(struct mmc_host *mmc)
2449 {
2450         struct sdhci_host *host = mmc_priv(mmc);
2451         unsigned long flags;
2452
2453         spin_lock_irqsave(&host->lock, flags);
2454
2455         /* Check host->mrq first in case we are runtime suspended */
2456         if (host->mrq &&
2457             !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
2458                 pr_err("%s: Card removed during transfer!\n",
2459                         mmc_hostname(host->mmc));
2460                 pr_err("%s: Resetting controller.\n",
2461                         mmc_hostname(host->mmc));
2462
2463                 sdhci_reset(host, SDHCI_RESET_CMD);
2464                 sdhci_reset(host, SDHCI_RESET_DATA);
2465
2466                 host->mrq->cmd->error = -ENOMEDIUM;
2467                 tasklet_schedule(&host->finish_tasklet);
2468         }
2469
2470         spin_unlock_irqrestore(&host->lock, flags);
2471 }
2472
2473 int sdhci_enable(struct mmc_host *mmc)
2474 {
2475         struct sdhci_host *host = mmc_priv(mmc);
2476
2477         if (!mmc->card || !(mmc->caps2 & MMC_CAP2_CLOCK_GATING))
2478                 return 0;
2479
2480         /* cancel delayed clk gate work */
2481         cancel_delayed_work_sync(&host->delayed_clk_gate_wrk);
2482
2483         sysedp_set_state(host->sysedpc, 1);
2484
2485         if (mmc->ios.clock) {
2486                 if (host->ops->set_clock)
2487                         host->ops->set_clock(host, mmc->ios.clock);
2488                 sdhci_set_clock(host, mmc->ios.clock);
2489         }
2490
2491         return 0;
2492 }
2493
2494 static void mmc_host_clk_gate(struct sdhci_host *host)
2495 {
2496         sdhci_set_clock(host, 0);
2497         if (host->ops->set_clock)
2498                 host->ops->set_clock(host, 0);
2499
2500         sysedp_set_state(host->sysedpc, 0);
2501
2502         return;
2503 }
2504
2505 void delayed_clk_gate_cb(struct work_struct *work)
2506 {
2507         struct sdhci_host *host = container_of(work, struct sdhci_host,
2508                                               delayed_clk_gate_wrk.work);
2509
2510         /* power off check */
2511         if (host->mmc->ios.power_mode == MMC_POWER_OFF)
2512                 goto end;
2513
2514         mmc_host_clk_gate(host);
2515 end:
2516         return;
2517 }
2518 EXPORT_SYMBOL_GPL(delayed_clk_gate_cb);
2519
2520 int sdhci_disable(struct mmc_host *mmc)
2521 {
2522         struct sdhci_host *host = mmc_priv(mmc);
2523
2524         if (!mmc->card || !(mmc->caps2 & MMC_CAP2_CLOCK_GATING))
2525                 return 0;
2526
2527         if (IS_DELAYED_CLK_GATE(host)) {
2528                 if (host->is_clk_on) {
2529                         if (IS_SDIO_CARD(host))
2530                                 host->clk_gate_tmout_ticks =
2531                                         SDIO_CLK_GATING_TICK_TMOUT;
2532                         else if (IS_EMMC_CARD(host))
2533                                 host->clk_gate_tmout_ticks =
2534                                         EMMC_CLK_GATING_TICK_TMOUT;
2535                         if (host->clk_gate_tmout_ticks > 0)
2536                                 schedule_delayed_work(
2537                                         &host->delayed_clk_gate_wrk,
2538                                         host->clk_gate_tmout_ticks);
2539                 }
2540                 return 0;
2541         }
2542
2543         mmc_host_clk_gate(host);
2544
2545         return 0;
2546 }
2547
2548 #ifdef CONFIG_MMC_FREQ_SCALING
2549 /*
2550  * Wrapper functions to call any platform specific implementation for
2551  * supporting dynamic frequency scaling for SD/MMC devices.
2552  */
2553 static int sdhci_gov_get_target(struct mmc_host *mmc, unsigned long *freq)
2554 {
2555         struct sdhci_host *host = mmc_priv(mmc);
2556
2557         if (host->ops->dfs_gov_get_target_freq)
2558                 *freq = host->ops->dfs_gov_get_target_freq(host,
2559                         mmc->devfreq_stats);
2560
2561         return 0;
2562 }
2563
2564 static int sdhci_gov_init(struct mmc_host *mmc)
2565 {
2566         struct sdhci_host *host = mmc_priv(mmc);
2567
2568         if (host->ops->dfs_gov_init)
2569                 return host->ops->dfs_gov_init(host);
2570
2571         return 0;
2572 }
2573
2574 static void sdhci_gov_exit(struct mmc_host *mmc)
2575 {
2576         struct sdhci_host *host = mmc_priv(mmc);
2577
2578         if (host->ops->dfs_gov_exit)
2579                 host->ops->dfs_gov_exit(host);
2580 }
2581 #endif
2582
2583 static int sdhci_select_drive_strength(struct mmc_host *mmc,
2584                                        unsigned int max_dtr,
2585                                        int host_drv,
2586                                        int card_drv)
2587 {
2588         struct sdhci_host *host = mmc_priv(mmc);
2589         unsigned char   drv_type;
2590
2591         /* return default strength if no handler in driver */
2592         if (!host->ops->get_drive_strength)
2593                 return MMC_SET_DRIVER_TYPE_B;
2594
2595         drv_type = host->ops->get_drive_strength(host, max_dtr,
2596                         host_drv, card_drv);
2597
2598         if (drv_type > MMC_SET_DRIVER_TYPE_D) {
2599                 pr_err("%s: Error on getting drive strength. Got drv_type %d\n"
2600                         , mmc_hostname(host->mmc), drv_type);
2601                 return MMC_SET_DRIVER_TYPE_B;
2602         }
2603
2604         return drv_type;
2605 }
2606
2607 static const struct mmc_host_ops sdhci_ops = {
2608         .request        = sdhci_request,
2609         .set_ios        = sdhci_set_ios,
2610         .get_cd         = sdhci_get_cd,
2611         .get_ro         = sdhci_get_ro,
2612         .hw_reset       = sdhci_hw_reset,
2613         .enable         = sdhci_enable,
2614         .disable        = sdhci_disable,
2615         .enable_sdio_irq = sdhci_enable_sdio_irq,
2616         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2617         .execute_tuning                 = sdhci_execute_tuning,
2618         .card_event                     = sdhci_card_event,
2619         .card_busy      = sdhci_card_busy,
2620 #ifdef CONFIG_MMC_FREQ_SCALING
2621         .dfs_governor_init              = sdhci_gov_init,
2622         .dfs_governor_exit              = sdhci_gov_exit,
2623         .dfs_governor_get_target        = sdhci_gov_get_target,
2624 #endif
2625         .select_drive_strength          = sdhci_select_drive_strength,
2626 };
2627
2628 /*****************************************************************************\
2629  *                                                                           *
2630  * Tasklets                                                                  *
2631  *                                                                           *
2632 \*****************************************************************************/
2633
2634 static void sdhci_tasklet_card(unsigned long param)
2635 {
2636         struct sdhci_host *host = (struct sdhci_host*)param;
2637
2638         sdhci_card_event(host->mmc);
2639
2640         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2641 }
2642
2643 static void sdhci_tasklet_finish(unsigned long param)
2644 {
2645         struct sdhci_host *host;
2646         unsigned long flags;
2647         struct mmc_request *mrq;
2648
2649         host = (struct sdhci_host*)param;
2650
2651         spin_lock_irqsave(&host->lock, flags);
2652
2653         /*
2654          * If this tasklet gets rescheduled while running, it will
2655          * be run again afterwards but without any active request.
2656          */
2657         if (!host->mrq) {
2658                 spin_unlock_irqrestore(&host->lock, flags);
2659                 return;
2660         }
2661
2662         del_timer(&host->timer);
2663
2664         mrq = host->mrq;
2665
2666         /*
2667          * The controller needs a reset of internal state machines
2668          * upon error conditions.
2669          */
2670         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2671             ((mrq->cmd && mrq->cmd->error) ||
2672                  (mrq->data && (mrq->data->error ||
2673                   (mrq->data->stop && mrq->data->stop->error))) ||
2674                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2675
2676                 /* Some controllers need this kick or reset won't work here */
2677                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2678                         /* This is to force an update */
2679                         sdhci_update_clock(host);
2680
2681                 /* Spec says we should do both at the same time, but Ricoh
2682                    controllers do not like that. */
2683                 sdhci_reset(host, SDHCI_RESET_CMD);
2684                 sdhci_reset(host, SDHCI_RESET_DATA);
2685         }
2686
2687         host->mrq = NULL;
2688         host->cmd = NULL;
2689         host->data = NULL;
2690
2691 #ifndef SDHCI_USE_LEDS_CLASS
2692         sdhci_deactivate_led(host);
2693 #endif
2694
2695         mmiowb();
2696         spin_unlock_irqrestore(&host->lock, flags);
2697
2698         mmc_request_done(host->mmc, mrq);
2699         sdhci_runtime_pm_put(host);
2700 }
2701
2702 static void sdhci_timeout_timer(unsigned long data)
2703 {
2704         struct sdhci_host *host;
2705         unsigned long flags;
2706
2707         host = (struct sdhci_host*)data;
2708
2709         spin_lock_irqsave(&host->lock, flags);
2710
2711         if (host->mrq) {
2712                 pr_err("%s: Timeout waiting for hardware "
2713                         "interrupt.\n", mmc_hostname(host->mmc));
2714                 sdhci_dumpregs(host);
2715
2716                 if (host->data) {
2717                         host->data->error = -ETIMEDOUT;
2718                         sdhci_finish_data(host);
2719                 } else {
2720                         if (host->cmd)
2721                                 host->cmd->error = -ETIMEDOUT;
2722                         else
2723                                 host->mrq->cmd->error = -ETIMEDOUT;
2724
2725                         tasklet_schedule(&host->finish_tasklet);
2726                 }
2727         }
2728
2729         mmiowb();
2730         spin_unlock_irqrestore(&host->lock, flags);
2731 }
2732
2733 static void sdhci_tuning_timer(unsigned long data)
2734 {
2735         struct sdhci_host *host;
2736         unsigned long flags;
2737
2738         host = (struct sdhci_host *)data;
2739
2740         spin_lock_irqsave(&host->lock, flags);
2741
2742         host->flags |= SDHCI_NEEDS_RETUNING;
2743
2744         spin_unlock_irqrestore(&host->lock, flags);
2745 }
2746
2747 /*****************************************************************************\
2748  *                                                                           *
2749  * Interrupt handling                                                        *
2750  *                                                                           *
2751 \*****************************************************************************/
2752
2753 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2754 {
2755         BUG_ON(intmask == 0);
2756
2757         if (!host->cmd) {
2758                 pr_err("%s: Got command interrupt 0x%08x even "
2759                         "though no command operation was in progress.\n",
2760                         mmc_hostname(host->mmc), (unsigned)intmask);
2761                 sdhci_dumpregs(host);
2762                 return;
2763         }
2764
2765         if (intmask & SDHCI_INT_TIMEOUT) {
2766                 host->cmd->error = -ETIMEDOUT;
2767         } else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2768                         SDHCI_INT_INDEX)) {
2769                 host->cmd->error = -EILSEQ;
2770                 sdhci_dumpregs(host);
2771                 pr_err("%s: Command CRC or END bit error, intmask: %x\n",
2772                                 mmc_hostname(host->mmc), intmask);
2773         }
2774
2775         if (host->cmd->error) {
2776                 tasklet_schedule(&host->finish_tasklet);
2777                 return;
2778         }
2779
2780         /*
2781          * The host can send and interrupt when the busy state has
2782          * ended, allowing us to wait without wasting CPU cycles.
2783          * Unfortunately this is overloaded on the "data complete"
2784          * interrupt, so we need to take some care when handling
2785          * it.
2786          *
2787          * Note: The 1.0 specification is a bit ambiguous about this
2788          *       feature so there might be some problems with older
2789          *       controllers.
2790          */
2791         if (host->cmd->flags & MMC_RSP_BUSY) {
2792                 if (host->cmd->data)
2793                         DBG("Cannot wait for busy signal when also "
2794                                 "doing a data transfer");
2795                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2796                         return;
2797
2798                 /* The controller does not support the end-of-busy IRQ,
2799                  * fall through and take the SDHCI_INT_RESPONSE */
2800         }
2801
2802         if (intmask & SDHCI_INT_RESPONSE)
2803                 sdhci_finish_command(host);
2804 }
2805
2806 #ifdef CONFIG_MMC_DEBUG
2807 static void sdhci_show_adma_error(struct sdhci_host *host)
2808 {
2809         const char *name = mmc_hostname(host->mmc);
2810         u8 *desc = host->adma_desc;
2811         __le32 *dma;
2812         __le16 *len;
2813         u8 attr;
2814
2815         sdhci_dumpregs(host);
2816
2817         while (true) {
2818                 dma = (__le32 *)(desc + 4);
2819                 len = (__le16 *)(desc + 2);
2820                 attr = *desc;
2821
2822                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2823                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2824
2825                 desc += 8;
2826
2827                 if (attr & 2)
2828                         break;
2829         }
2830 }
2831 #else
2832 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2833 #endif
2834
2835 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2836 {
2837         u32 command;
2838         BUG_ON(intmask == 0);
2839
2840         /* CMD19, CMD21 generates _only_ Buffer Read Ready interrupt */
2841         if (intmask & SDHCI_INT_DATA_AVAIL) {
2842                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2843                 if (command == MMC_SEND_TUNING_BLOCK ||
2844                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2845                         host->tuning_done = 1;
2846                         wake_up(&host->buf_ready_int);
2847                         return;
2848                 }
2849         }
2850
2851         if (!host->data) {
2852                 /*
2853                  * The "data complete" interrupt is also used to
2854                  * indicate that a busy state has ended. See comment
2855                  * above in sdhci_cmd_irq().
2856                  */
2857                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2858                         if (intmask & SDHCI_INT_DATA_END) {
2859                                 sdhci_finish_command(host);
2860                                 return;
2861                         }
2862                 }
2863
2864                 pr_err("%s: Got data interrupt 0x%08x even "
2865                         "though no data operation was in progress.\n",
2866                         mmc_hostname(host->mmc), (unsigned)intmask);
2867                 sdhci_dumpregs(host);
2868
2869                 return;
2870         }
2871
2872         if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2873                 host->data->error = -ETIMEDOUT;
2874                 pr_err("%s: Data Timeout error, intmask: %x\n",
2875                                 mmc_hostname(host->mmc), intmask);
2876                 sdhci_dumpregs(host);
2877         } else if (intmask & SDHCI_INT_DATA_END_BIT) {
2878                 host->data->error = -EILSEQ;
2879                 pr_err("%s: Data END Bit error, intmask: %x\n",
2880                                 mmc_hostname(host->mmc), intmask);
2881         } else if ((intmask & SDHCI_INT_DATA_CRC) &&
2882                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2883                         != MMC_BUS_TEST_R) {
2884                 host->data->error = -EILSEQ;
2885                 pr_err("%s: Data CRC error, intmask: %x\n",
2886                                 mmc_hostname(host->mmc), intmask);
2887                 sdhci_dumpregs(host);
2888         } else if (intmask & SDHCI_INT_ADMA_ERROR) {
2889                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2890                 sdhci_dumpregs(host);
2891                 sdhci_show_adma_error(host);
2892                 host->data->error = -EIO;
2893                 if (host->ops->adma_workaround)
2894                         host->ops->adma_workaround(host, intmask);
2895         }
2896
2897         if (host->data->error)
2898                 sdhci_finish_data(host);
2899         else {
2900                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2901                         sdhci_transfer_pio(host);
2902
2903                 /*
2904                  * We currently don't do anything fancy with DMA
2905                  * boundaries, but as we can't disable the feature
2906                  * we need to at least restart the transfer.
2907                  *
2908                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2909                  * should return a valid address to continue from, but as
2910                  * some controllers are faulty, don't trust them.
2911                  */
2912                 if (intmask & SDHCI_INT_DMA_END) {
2913                         u32 dmastart, dmanow;
2914                         dmastart = sg_dma_address(host->data->sg);
2915                         dmanow = dmastart + host->data->bytes_xfered;
2916                         /*
2917                          * Force update to the next DMA block boundary.
2918                          */
2919                         dmanow = (dmanow &
2920                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2921                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2922                         host->data->bytes_xfered = dmanow - dmastart;
2923                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2924                                 " next 0x%08x\n",
2925                                 mmc_hostname(host->mmc), dmastart,
2926                                 host->data->bytes_xfered, dmanow);
2927                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2928                 }
2929
2930                 if (intmask & SDHCI_INT_DATA_END) {
2931                         if (host->cmd)
2932                                 /*
2933                                  * Data managed to finish before the
2934                                  * command completed. Make sure we do
2935                                  * things in the proper order.
2936                                  */
2937                                 host->data_early = 1;
2938                         else
2939                                 sdhci_finish_data(host);
2940                 }
2941         }
2942 }
2943
2944 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2945 {
2946         irqreturn_t result;
2947         struct sdhci_host *host = dev_id;
2948         u32 intmask, unexpected = 0;
2949         int cardint = 0, max_loops = 16;
2950
2951         spin_lock(&host->lock);
2952
2953         if (host->runtime_suspended) {
2954                 spin_unlock(&host->lock);
2955                 pr_warning("%s: got irq while runtime suspended\n",
2956                        mmc_hostname(host->mmc));
2957                 return IRQ_HANDLED;
2958         }
2959
2960         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2961
2962         if (!intmask || intmask == 0xffffffff) {
2963                 result = IRQ_NONE;
2964                 goto out;
2965         }
2966
2967 again:
2968         DBG("*** %s got interrupt: 0x%08x\n",
2969                 mmc_hostname(host->mmc), intmask);
2970
2971         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2972                 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2973                               SDHCI_CARD_PRESENT;
2974
2975                 /*
2976                  * There is a observation on i.mx esdhc.  INSERT bit will be
2977                  * immediately set again when it gets cleared, if a card is
2978                  * inserted.  We have to mask the irq to prevent interrupt
2979                  * storm which will freeze the system.  And the REMOVE gets
2980                  * the same situation.
2981                  *
2982                  * More testing are needed here to ensure it works for other
2983                  * platforms though.
2984                  */
2985                 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2986                                                 SDHCI_INT_CARD_REMOVE);
2987                 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2988                                                   SDHCI_INT_CARD_INSERT);
2989
2990                 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2991                              SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2992                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2993                 tasklet_schedule(&host->card_tasklet);
2994         }
2995
2996         if (intmask & SDHCI_INT_CMD_MASK) {
2997                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2998                         SDHCI_INT_STATUS);
2999                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
3000         }
3001
3002         if (intmask & SDHCI_INT_DATA_MASK) {
3003                 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
3004                         SDHCI_INT_STATUS);
3005                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
3006         }
3007
3008         if ((intmask & SDHCI_INT_DATA_MASK) || (intmask & SDHCI_INT_CMD_MASK))
3009                 if (host->ops->sd_error_stats)
3010                         host->ops->sd_error_stats(host, intmask);
3011
3012         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
3013
3014         intmask &= ~SDHCI_INT_ERROR;
3015
3016         if (intmask & SDHCI_INT_BUS_POWER) {
3017                 pr_err("%s: Card is consuming too much power!\n",
3018                         mmc_hostname(host->mmc));
3019                 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
3020         }
3021
3022         intmask &= ~SDHCI_INT_BUS_POWER;
3023
3024         if (intmask & SDHCI_INT_CARD_INT)
3025                 cardint = 1;
3026
3027         intmask &= ~SDHCI_INT_CARD_INT;
3028
3029         if (intmask) {
3030                 unexpected |= intmask;
3031                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3032         }
3033
3034         result = IRQ_HANDLED;
3035
3036         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3037         if (intmask && --max_loops)
3038                 goto again;
3039 out:
3040         spin_unlock(&host->lock);
3041
3042         if (unexpected) {
3043                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3044                            mmc_hostname(host->mmc), unexpected);
3045                 sdhci_dumpregs(host);
3046         }
3047         /*
3048          * We have to delay this as it calls back into the driver.
3049          */
3050         if (cardint)
3051                 mmc_signal_sdio_irq(host->mmc);
3052
3053         return result;
3054 }
3055
3056 /*****************************************************************************\
3057  *                                                                           *
3058  * Suspend/resume                                                            *
3059  *                                                                           *
3060 \*****************************************************************************/
3061
3062 #ifdef CONFIG_PM
3063 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
3064 {
3065         u8 val;
3066         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3067                         | SDHCI_WAKE_ON_INT;
3068
3069         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3070         val |= mask ;
3071         /* Avoid fake wake up */
3072         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
3073                 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
3074         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3075 }
3076 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
3077
3078 void sdhci_disable_irq_wakeups(struct sdhci_host *host)
3079 {
3080         u8 val;
3081         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3082                         | SDHCI_WAKE_ON_INT;
3083
3084         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3085         val &= ~mask;
3086         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3087 }
3088 EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
3089
3090 int sdhci_suspend_host(struct sdhci_host *host)
3091 {
3092         int ret;
3093         struct mmc_host *mmc = host->mmc;
3094
3095         if (host->ops->platform_suspend)
3096                 host->ops->platform_suspend(host);
3097
3098         sdhci_disable_card_detection(host);
3099
3100         /* Disable tuning since we are suspending */
3101         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
3102                 del_timer_sync(&host->tuning_timer);
3103                 host->flags &= ~SDHCI_NEEDS_RETUNING;
3104         }
3105
3106         /*
3107          * If eMMC cards are put in sleep state, Vccq can be disabled
3108          * but Vcc would still be powered on. In resume, we only restore
3109          * the controller context. So, set MMC_PM_KEEP_POWER flag.
3110          */
3111         if (mmc_card_can_sleep(mmc) && !(mmc->caps2 & MMC_CAP2_NO_SLEEP_CMD))
3112                 mmc->pm_flags = MMC_PM_KEEP_POWER;
3113
3114         ret = mmc_suspend_host(host->mmc);
3115         if (ret) {
3116                 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
3117                         host->flags |= SDHCI_NEEDS_RETUNING;
3118                         mod_timer(&host->tuning_timer, jiffies +
3119                                         host->tuning_count * HZ);
3120                 }
3121
3122                 sdhci_enable_card_detection(host);
3123
3124                 return ret;
3125         }
3126
3127         /*
3128          * If host clock is disabled but the register access requires host
3129          * clock, then enable the clock, mask the interrupts and disable
3130          * the clock.
3131          */
3132         if (host->quirks2 & SDHCI_QUIRK2_REG_ACCESS_REQ_HOST_CLK)
3133                 if (!host->clock && host->ops->set_clock)
3134                         host->ops->set_clock(host, max(mmc->ios.clock, mmc->f_min));
3135
3136         if (mmc->pm_flags & MMC_PM_KEEP_POWER)
3137                 host->card_int_set = sdhci_readl(host, SDHCI_INT_ENABLE) &
3138                         SDHCI_INT_CARD_INT;
3139
3140         /* cancel delayed clk gate work */
3141         cancel_delayed_work_sync(&host->delayed_clk_gate_wrk);
3142
3143         if (!device_may_wakeup(mmc_dev(host->mmc))) {
3144                 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
3145
3146                 if (host->quirks2 & SDHCI_QUIRK2_REG_ACCESS_REQ_HOST_CLK)
3147                         if (!host->clock && host->ops->set_clock)
3148                                 host->ops->set_clock(host, 0);
3149
3150                 if (host->irq)
3151                         disable_irq(host->irq);
3152         } else {
3153                 sdhci_enable_irq_wakeups(host);
3154                 enable_irq_wake(host->irq);
3155
3156                 if (host->quirks2 & SDHCI_QUIRK2_REG_ACCESS_REQ_HOST_CLK)
3157                         if (!host->clock && host->ops->set_clock)
3158                                 host->ops->set_clock(host, 0);
3159         }
3160
3161         return ret;
3162 }
3163
3164 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
3165
3166 int sdhci_resume_host(struct sdhci_host *host)
3167 {
3168         int ret;
3169         struct mmc_host *mmc = host->mmc;
3170
3171         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3172                 if (host->ops->enable_dma)
3173                         host->ops->enable_dma(host);
3174         }
3175
3176         if (!device_may_wakeup(mmc_dev(host->mmc))) {
3177                 if (host->irq)
3178                         enable_irq(host->irq);
3179         } else {
3180                 sdhci_disable_irq_wakeups(host);
3181                 disable_irq_wake(host->irq);
3182         }
3183
3184         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
3185             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3186                 /* Card keeps power but host controller does not */
3187                 sdhci_init(host, 0);
3188                 host->pwr = 0;
3189                 host->clock = 0;
3190                 sdhci_do_set_ios(host, &host->mmc->ios);
3191         } else {
3192                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
3193                 mmiowb();
3194         }
3195
3196         ret = mmc_resume_host(host->mmc);
3197         /* Enable card interrupt as it is overwritten in sdhci_init */
3198         if ((mmc->caps & MMC_CAP_SDIO_IRQ) &&
3199                 (mmc->pm_flags & MMC_PM_KEEP_POWER))
3200                         if (host->card_int_set)
3201                                 mmc->ops->enable_sdio_irq(mmc, true);
3202
3203         sdhci_enable_card_detection(host);
3204
3205         if (host->ops->platform_resume)
3206                 host->ops->platform_resume(host);
3207
3208         /* Set the re-tuning expiration flag */
3209         if (host->flags & SDHCI_USING_RETUNING_TIMER)
3210                 host->flags |= SDHCI_NEEDS_RETUNING;
3211
3212         return ret;
3213 }
3214
3215 EXPORT_SYMBOL_GPL(sdhci_resume_host);
3216 #endif /* CONFIG_PM */
3217
3218 #ifdef CONFIG_PM_RUNTIME
3219
3220 static int sdhci_runtime_pm_get(struct sdhci_host *host)
3221 {
3222         return pm_runtime_get_sync(host->mmc->parent);
3223 }
3224
3225 static int sdhci_runtime_pm_put(struct sdhci_host *host)
3226 {
3227         pm_runtime_mark_last_busy(host->mmc->parent);
3228         return pm_runtime_put_autosuspend(host->mmc->parent);
3229 }
3230
3231 int sdhci_runtime_suspend_host(struct sdhci_host *host)
3232 {
3233         unsigned long flags;
3234         int ret = 0;
3235
3236         /* Disable tuning since we are suspending */
3237         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
3238                 del_timer_sync(&host->tuning_timer);
3239                 host->flags &= ~SDHCI_NEEDS_RETUNING;
3240         }
3241
3242         spin_lock_irqsave(&host->lock, flags);
3243         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
3244         spin_unlock_irqrestore(&host->lock, flags);
3245
3246         synchronize_irq(host->irq);
3247
3248         spin_lock_irqsave(&host->lock, flags);
3249         host->runtime_suspended = true;
3250         spin_unlock_irqrestore(&host->lock, flags);
3251
3252         return ret;
3253 }
3254 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3255
3256 int sdhci_runtime_resume_host(struct sdhci_host *host)
3257 {
3258         unsigned long flags;
3259         int ret = 0, host_flags = host->flags;
3260
3261         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3262                 if (host->ops->enable_dma)
3263                         host->ops->enable_dma(host);
3264         }
3265
3266         sdhci_init(host, 0);
3267
3268         /* Force clock and power re-program */
3269         host->pwr = 0;
3270         host->clock = 0;
3271         sdhci_do_set_ios(host, &host->mmc->ios);
3272
3273         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
3274         /* Do any post voltage switch platform specific configuration */
3275         if  (host->ops->switch_signal_voltage_exit)
3276                 host->ops->switch_signal_voltage_exit(host,
3277                         host->mmc->ios.signal_voltage);
3278         if ((host_flags & SDHCI_PV_ENABLED) &&
3279                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3280                 spin_lock_irqsave(&host->lock, flags);
3281                 sdhci_enable_preset_value(host, true);
3282                 spin_unlock_irqrestore(&host->lock, flags);
3283         }
3284
3285         /* Set the re-tuning expiration flag */
3286         if (host->flags & SDHCI_USING_RETUNING_TIMER)
3287                 host->flags |= SDHCI_NEEDS_RETUNING;
3288
3289         spin_lock_irqsave(&host->lock, flags);
3290
3291         host->runtime_suspended = false;
3292
3293         /* Enable SDIO IRQ */
3294         if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
3295                 sdhci_enable_sdio_irq_nolock(host, true);
3296
3297         /* Enable Card Detection */
3298         sdhci_enable_card_detection(host);
3299
3300         spin_unlock_irqrestore(&host->lock, flags);
3301
3302         return ret;
3303 }
3304 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3305
3306 #endif
3307
3308 /*****************************************************************************\
3309  *                                                                           *
3310  * Device allocation/registration                                            *
3311  *                                                                           *
3312 \*****************************************************************************/
3313
3314 struct sdhci_host *sdhci_alloc_host(struct device *dev,
3315         size_t priv_size)
3316 {
3317         struct mmc_host *mmc;
3318         struct sdhci_host *host;
3319
3320         WARN_ON(dev == NULL);
3321
3322         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3323         if (!mmc)
3324                 return ERR_PTR(-ENOMEM);
3325
3326         host = mmc_priv(mmc);
3327         host->mmc = mmc;
3328
3329         return host;
3330 }
3331
3332 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3333
3334 #ifdef CONFIG_DEBUG_FS
3335 static int show_sdhci_perf_stats(struct seq_file *s, void *data)
3336 {
3337         struct sdhci_host *host = s->private;
3338         int i;
3339         u32 avg_perf2;
3340         u32 last_perf_in_class;
3341         struct data_stat_entry *stat = NULL;
3342         char buf[250];
3343
3344         seq_printf(s, "SDHCI(%s): perf statistics stat_size=%d\n",
3345                 mmc_hostname(host->mmc),
3346                 host->sdhci_data_stat.stat_size
3347                 );
3348         if (host->sdhci_data_stat.stat_size) {
3349                 seq_printf(s, "SDHCI(%s): perf statistics:\n",
3350                         mmc_hostname(host->mmc));
3351                 seq_puts(s,
3352                 "Note: Performance figures in kilo bits per sec(kbps)\n");
3353                 seq_puts(s,
3354                 "S.No.    Block       Num blks/        Total                Total          Last            Last usec          Avg kbps        Last kbps           Min kbps   Max kbps\n");
3355                 seq_puts(s,
3356                 "         Size        transfer         Bytes                Time(usec)     Bytes           Duration           Perf            Perf                Perf       Perf\n");
3357         }
3358         for (i = 0; i < host->sdhci_data_stat.stat_size; i++) {
3359                 if (!stat)
3360                         stat = host->sdhci_data_stat.head;
3361                 else
3362                         stat = stat->next;
3363                 get_kbps_from_size_n_usec_64bit(
3364                         ((stat->total_bytes << 3) * 1000),
3365                         stat->total_usecs, &avg_perf2);
3366                 get_kbps_from_size_n_usec_32bit(
3367                         (((u32)stat->current_transferred_bytes << 3) * 1000),
3368                         stat->duration_usecs,
3369                         &last_perf_in_class);
3370                 snprintf(buf, 250,
3371                         "%2d    %4d      %8d    %16lld            %8d    %8d            %8d           %8d         %8d         %8d    %8d\n",
3372                         (i + 1),
3373                         stat->stat_blk_size,
3374                         stat->stat_blks_per_transfer,
3375                         stat->total_bytes,
3376                         stat->total_usecs,
3377                         stat->current_transferred_bytes,
3378                         stat->duration_usecs,
3379                         avg_perf2,
3380                         last_perf_in_class,
3381                         stat->min_kbps,
3382                         stat->max_kbps
3383                         );
3384                 seq_puts(s, buf);
3385         }
3386
3387         return 0;
3388 }
3389
3390 static int sdhci_perf_stats_dump(struct inode *inode, struct file *file)
3391 {
3392         return single_open(file, show_sdhci_perf_stats, inode->i_private);
3393 }
3394
3395 static const struct file_operations flush_sdhci_perf_stats_fops = {
3396         .open           = sdhci_perf_stats_dump,
3397         .read           = seq_read,
3398         .llseek         = seq_lseek,
3399         .release        = single_release,
3400 };
3401
3402 static int restart_sdhci_perf_stats(struct seq_file *s, void *data)
3403 {
3404         struct sdhci_host *host = s->private;
3405
3406         free_stats_nodes(host);
3407         return 0;
3408 }
3409
3410 static int sdhci_perf_stats_restart(struct inode *inode, struct file *file)
3411 {
3412         return single_open(file, restart_sdhci_perf_stats, inode->i_private);
3413 }
3414
3415 static const struct file_operations reset_sdhci_perf_stats_fops = {
3416         .open           = sdhci_perf_stats_restart,
3417         .read           = seq_read,
3418         .llseek         = seq_lseek,
3419         .release        = single_release,
3420 };
3421
3422 static void sdhci_debugfs_init(struct sdhci_host *host)
3423 {
3424         struct dentry *root = host->debugfs_root;
3425
3426         /*
3427          * debugfs nodes earlier were created from sdhci-tegra,
3428          * In this change root debugfs node is created first-come-first-serve
3429          */
3430         if (!root) {
3431                 root = debugfs_create_dir(dev_name(mmc_dev(host->mmc)), NULL);
3432                 if (IS_ERR_OR_NULL(root))
3433                         goto err_root;
3434                 host->debugfs_root = root;
3435         }
3436
3437         if (!debugfs_create_u32("enable_sdhci_perf_stats", S_IRUGO | S_IWUSR,
3438                 root, (u32 *)&host->enable_sdhci_perf_stats))
3439                 goto err_root;
3440
3441         if (!debugfs_create_file("reset_sdhci_perf_stats", S_IRUGO,
3442                 root, host, &reset_sdhci_perf_stats_fops))
3443                 goto err_root;
3444
3445         if (!debugfs_create_file("sdhci_perf_stats", S_IRUGO,
3446                 root, host, &flush_sdhci_perf_stats_fops))
3447                 goto err_root;
3448
3449         if (!debugfs_create_u32("sdhci_perf_no_data_transfer_count", S_IRUGO,
3450                 root, (u32 *)&host->no_data_transfer_count))
3451                 goto err_root;
3452
3453         return;
3454
3455 err_root:
3456         debugfs_remove_recursive(root);
3457         host->debugfs_root = NULL;
3458
3459         return;
3460 }
3461 #endif
3462
3463 int sdhci_add_host(struct sdhci_host *host)
3464 {
3465         struct mmc_host *mmc;
3466         u32 caps[2] = {0, 0};
3467         u32 max_current_caps;
3468         unsigned int ocr_avail;
3469         int ret;
3470
3471         WARN_ON(host == NULL);
3472         if (host == NULL)
3473                 return -EINVAL;
3474
3475         mmc = host->mmc;
3476
3477         if (debug_quirks)
3478                 host->quirks = debug_quirks;
3479         if (debug_quirks2)
3480                 host->quirks2 = debug_quirks2;
3481
3482         sdhci_reset(host, SDHCI_RESET_ALL);
3483
3484         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
3485         host->version = (host->version & SDHCI_SPEC_VER_MASK)
3486                                 >> SDHCI_SPEC_VER_SHIFT;
3487         if (host->version > SDHCI_SPEC_400) {
3488                 pr_err("%s: Unknown controller version (%d). "
3489                         "You may experience problems.\n", mmc_hostname(mmc),
3490                         host->version);
3491         }
3492
3493         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
3494                 sdhci_readl(host, SDHCI_CAPABILITIES);
3495
3496         if (host->version >= SDHCI_SPEC_300)
3497                 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
3498                         host->caps1 :
3499                         sdhci_readl(host, SDHCI_CAPABILITIES_1);
3500
3501         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
3502                 host->flags |= SDHCI_USE_SDMA;
3503         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
3504                 DBG("Controller doesn't have SDMA capability\n");
3505         else
3506                 host->flags |= SDHCI_USE_SDMA;
3507
3508         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
3509                 (host->flags & SDHCI_USE_SDMA)) {
3510                 DBG("Disabling DMA as it is marked broken\n");
3511                 host->flags &= ~SDHCI_USE_SDMA;
3512         }
3513
3514         if ((host->version >= SDHCI_SPEC_200) &&
3515                 (caps[0] & SDHCI_CAN_DO_ADMA2))
3516                 host->flags |= SDHCI_USE_ADMA;
3517
3518         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
3519                 (host->flags & SDHCI_USE_ADMA)) {
3520                 DBG("Disabling ADMA as it is marked broken\n");
3521                 host->flags &= ~SDHCI_USE_ADMA;
3522         }
3523
3524         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3525                 if (host->ops->enable_dma) {
3526                         if (host->ops->enable_dma(host)) {
3527                                 pr_warning("%s: No suitable DMA "
3528                                         "available. Falling back to PIO.\n",
3529                                         mmc_hostname(mmc));
3530                                 host->flags &=
3531                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3532                         }
3533                 }
3534         }
3535
3536         if (host->flags & SDHCI_USE_ADMA) {
3537                 /*
3538                  * We need to allocate descriptors for all sg entries
3539                  * (128) and potentially one alignment transfer for
3540                  * each of those entries. Simply allocating 128 bits
3541                  * for each entry
3542                  */
3543                 if (mmc_dev(host->mmc)->dma_mask &&
3544                                 mmc_dev(host->mmc)->coherent_dma_mask) {
3545                         host->adma_desc = dma_alloc_coherent(
3546                                         mmc_dev(host->mmc), (128 * 2 + 1) * 8,
3547                                         &host->adma_addr, GFP_KERNEL);
3548                         if (!host->adma_desc)
3549                                 goto err_dma_alloc;
3550
3551                         host->align_buffer = dma_alloc_coherent(
3552                                         mmc_dev(host->mmc), 128 * 8,
3553                                         &host->align_addr, GFP_KERNEL);
3554                         if (!host->align_buffer) {
3555                                 dma_free_coherent(mmc_dev(host->mmc),
3556                                                 (128 * 2 + 1) * 8,
3557                                                 host->adma_desc,
3558                                                 host->adma_addr);
3559                                 host->adma_desc = NULL;
3560                                 goto err_dma_alloc;
3561                         }
3562
3563                         host->use_dma_alloc = true;
3564
3565                         BUG_ON(host->adma_addr & 0x3);
3566                         BUG_ON(host->align_addr & 0x3);
3567                         goto out_dma_alloc;
3568                 }
3569 err_dma_alloc:
3570                 host->adma_desc = kmalloc((128 * 2 + 1) * 8, GFP_KERNEL);
3571                 host->align_buffer = kmalloc(128 * 8, GFP_KERNEL);
3572                 if (!host->adma_desc || !host->align_buffer) {
3573                         kfree(host->adma_desc);
3574                         kfree(host->align_buffer);
3575                         pr_warning("%s: Unable to allocate ADMA "
3576                                 "buffers. Falling back to standard DMA.\n",
3577                                 mmc_hostname(mmc));
3578                         host->flags &= ~SDHCI_USE_ADMA;
3579                 }
3580         }
3581 out_dma_alloc:
3582
3583         /*
3584          * If we use DMA, then it's up to the caller to set the DMA
3585          * mask, but PIO does not need the hw shim so we set a new
3586          * mask here in that case.
3587          */
3588         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3589                 host->dma_mask = DMA_BIT_MASK(64);
3590                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
3591         }
3592
3593         if (host->version >= SDHCI_SPEC_300)
3594                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
3595                         >> SDHCI_CLOCK_BASE_SHIFT;
3596         else
3597                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
3598                         >> SDHCI_CLOCK_BASE_SHIFT;
3599
3600         host->max_clk *= 1000000;
3601         if (host->max_clk == 0 || host->quirks &
3602                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3603                 if (!host->ops->get_max_clock) {
3604                         pr_err("%s: Hardware doesn't specify base clock "
3605                                "frequency.\n", mmc_hostname(mmc));
3606                         return -ENODEV;
3607                 }
3608                 host->max_clk = host->ops->get_max_clock(host);
3609         }
3610
3611         /*
3612          * In case of Host Controller v3.00, find out whether clock
3613          * multiplier is supported.
3614          */
3615         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3616                         SDHCI_CLOCK_MUL_SHIFT;
3617
3618         /*
3619          * In case the value in Clock Multiplier is 0, then programmable
3620          * clock mode is not supported, otherwise the actual clock
3621          * multiplier is one more than the value of Clock Multiplier
3622          * in the Capabilities Register.
3623          */
3624         if (host->clk_mul)
3625                 host->clk_mul += 1;
3626
3627         /*
3628          * Set host parameters.
3629          */
3630         mmc->ops = &sdhci_ops;
3631         mmc->f_max = host->max_clk;
3632         if (host->ops->get_min_clock)
3633                 mmc->f_min = host->ops->get_min_clock(host);
3634         else if (host->version >= SDHCI_SPEC_300) {
3635                 if (host->clk_mul) {
3636                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3637                         mmc->f_max = host->max_clk * host->clk_mul;
3638                 } else
3639                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3640         } else
3641                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3642
3643         host->timeout_clk =
3644                 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
3645         if (host->timeout_clk == 0) {
3646                 if (host->ops->get_timeout_clock) {
3647                         host->timeout_clk = host->ops->get_timeout_clock(host);
3648                 } else if (!(host->quirks &
3649                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3650                         pr_err("%s: Hardware doesn't specify timeout clock "
3651                                "frequency.\n", mmc_hostname(mmc));
3652                         return -ENODEV;
3653                 }
3654         }
3655         if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3656                 host->timeout_clk *= 1000;
3657
3658         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
3659                 host->timeout_clk = mmc->f_max / 1000;
3660
3661         if (!(host->quirks2 & SDHCI_QUIRK2_NO_CALC_MAX_DISCARD_TO))
3662                 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
3663
3664         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3665                 host->flags |= SDHCI_AUTO_CMD12;
3666
3667         /* Auto-CMD23 stuff only works in ADMA or PIO. */
3668         if ((host->version >= SDHCI_SPEC_300) &&
3669             ((host->flags & SDHCI_USE_ADMA) ||
3670              !(host->flags & SDHCI_USE_SDMA))) {
3671                 host->flags |= SDHCI_AUTO_CMD23;
3672                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3673         } else {
3674                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3675         }
3676
3677         /*
3678          * A controller may support 8-bit width, but the board itself
3679          * might not have the pins brought out.  Boards that support
3680          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3681          * their platform code before calling sdhci_add_host(), and we
3682          * won't assume 8-bit width for hosts without that CAP.
3683          */
3684         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3685                 mmc->caps |= MMC_CAP_4_BIT_DATA;
3686
3687         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3688                 mmc->caps &= ~MMC_CAP_CMD23;
3689
3690         if (caps[0] & SDHCI_CAN_DO_HISPD)
3691                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3692
3693         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3694             !(host->mmc->caps & MMC_CAP_NONREMOVABLE) && !(host->ops->get_cd))
3695                 mmc->caps |= MMC_CAP_NEEDS_POLL;
3696
3697         /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3698         host->vqmmc = regulator_get(mmc_dev(mmc), "vqmmc");
3699         if (IS_ERR_OR_NULL(host->vqmmc)) {
3700                 if (PTR_ERR(host->vqmmc) < 0) {
3701                         pr_info("%s: no vqmmc regulator found\n",
3702                                 mmc_hostname(mmc));
3703                         host->vqmmc = NULL;
3704                 }
3705         } else {
3706                 ret = regulator_enable(host->vqmmc);
3707                 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
3708                         1950000))
3709                         caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3710                                         SDHCI_SUPPORT_SDR50 |
3711                                         SDHCI_SUPPORT_DDR50);
3712                 if (ret) {
3713                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3714                                 mmc_hostname(mmc), ret);
3715                         host->vqmmc = NULL;
3716                 }
3717         }
3718
3719         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3720                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3721                        SDHCI_SUPPORT_DDR50);
3722
3723         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3724         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3725                        SDHCI_SUPPORT_DDR50))
3726                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3727
3728         /* SDR104 supports also implies SDR50 support */
3729         if (caps[1] & SDHCI_SUPPORT_SDR104)
3730                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3731         else if (caps[1] & SDHCI_SUPPORT_SDR50)
3732                 mmc->caps |= MMC_CAP_UHS_SDR50;
3733
3734         if (caps[1] & SDHCI_SUPPORT_DDR50)
3735                 mmc->caps |= MMC_CAP_UHS_DDR50;
3736
3737         /* Does the host need tuning for SDR50? */
3738         if (caps[1] & SDHCI_USE_SDR50_TUNING)
3739                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3740
3741         /* Does the host need tuning for HS200? */
3742         if (mmc->caps2 & MMC_CAP2_HS200)
3743                 host->flags |= SDHCI_HS200_NEEDS_TUNING;
3744
3745         /* Driver Type(s) (A, C, D) supported by the host */
3746         if (caps[1] & SDHCI_DRIVER_TYPE_A)
3747                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3748         if (caps[1] & SDHCI_DRIVER_TYPE_C)
3749                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3750         if (caps[1] & SDHCI_DRIVER_TYPE_D)
3751                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3752
3753         /* Initial value for re-tuning timer count */
3754         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3755                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3756         /*
3757          * If the re-tuning timer count value is 0xF, the timer count
3758          * information should be obtained in a non-standard way.
3759          */
3760         if (host->tuning_count == 0xF) {
3761                 if (host->ops->get_tuning_counter) {
3762                         host->tuning_count =
3763                                 host->ops->get_tuning_counter(host);
3764                 } else {
3765                         host->tuning_count = 0;
3766                 }
3767         }
3768
3769         /*
3770          * In case Re-tuning Timer is not disabled, the actual value of
3771          * re-tuning timer will be 2 ^ (n - 1).
3772          */
3773         if (host->tuning_count)
3774                 host->tuning_count = 1 << (host->tuning_count - 1);
3775
3776         /* Re-tuning mode supported by the Host Controller */
3777         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3778                              SDHCI_RETUNING_MODE_SHIFT;
3779
3780         ocr_avail = 0;
3781
3782         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
3783         if (IS_ERR_OR_NULL(host->vmmc)) {
3784                 if (PTR_ERR(host->vmmc) < 0) {
3785                         pr_info("%s: no vmmc regulator found\n",
3786                                 mmc_hostname(mmc));
3787                         host->vmmc = NULL;
3788                 }
3789         }
3790
3791 #ifdef CONFIG_REGULATOR
3792         /*
3793          * Voltage range check makes sense only if regulator reports
3794          * any voltage value.
3795          */
3796         if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
3797                 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
3798                         3600000);
3799                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
3800                         caps[0] &= ~SDHCI_CAN_VDD_330;
3801                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
3802                         caps[0] &= ~SDHCI_CAN_VDD_300;
3803                 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
3804                         1950000);
3805                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
3806                         caps[0] &= ~SDHCI_CAN_VDD_180;
3807         }
3808 #endif /* CONFIG_REGULATOR */
3809
3810         /*
3811          * According to SD Host Controller spec v3.00, if the Host System
3812          * can afford more than 150mA, Host Driver should set XPC to 1. Also
3813          * the value is meaningful only if Voltage Support in the Capabilities
3814          * register is set. The actual current value is 4 times the register
3815          * value.
3816          */
3817         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3818         if (!max_current_caps && host->vmmc) {
3819                 u32 curr = regulator_get_current_limit(host->vmmc);
3820                 if (curr > 0) {
3821
3822                         /* convert to SDHCI_MAX_CURRENT format */
3823                         curr = curr/1000;  /* convert to mA */
3824                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3825
3826                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3827                         max_current_caps =
3828                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3829                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3830                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3831                 }
3832         }
3833
3834         if (caps[0] & SDHCI_CAN_VDD_330) {
3835                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3836
3837                 mmc->max_current_330 = ((max_current_caps &
3838                                    SDHCI_MAX_CURRENT_330_MASK) >>
3839                                    SDHCI_MAX_CURRENT_330_SHIFT) *
3840                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3841         }
3842         if (caps[0] & SDHCI_CAN_VDD_300) {
3843                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3844
3845                 mmc->max_current_300 = ((max_current_caps &
3846                                    SDHCI_MAX_CURRENT_300_MASK) >>
3847                                    SDHCI_MAX_CURRENT_300_SHIFT) *
3848                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3849         }
3850         if (caps[0] & SDHCI_CAN_VDD_180) {
3851                 ocr_avail |= MMC_VDD_165_195;
3852
3853                 mmc->max_current_180 = ((max_current_caps &
3854                                    SDHCI_MAX_CURRENT_180_MASK) >>
3855                                    SDHCI_MAX_CURRENT_180_SHIFT) *
3856                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3857         }
3858
3859         mmc->ocr_avail = ocr_avail;
3860         mmc->ocr_avail_sdio = ocr_avail;
3861         if (host->ocr_avail_sdio)
3862                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3863         mmc->ocr_avail_sd = ocr_avail;
3864         if (host->ocr_avail_sd)
3865                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3866         else /* normal SD controllers don't support 1.8V */
3867                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3868         mmc->ocr_avail_mmc = ocr_avail;
3869         if (host->ocr_avail_mmc)
3870                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3871
3872         if (mmc->ocr_avail == 0) {
3873                 pr_err("%s: Hardware doesn't report any "
3874                         "support voltages.\n", mmc_hostname(mmc));
3875                 return -ENODEV;
3876         }
3877
3878         spin_lock_init(&host->lock);
3879
3880         /*
3881          * Maximum number of segments. Depends on if the hardware
3882          * can do scatter/gather or not.
3883          */
3884         if (host->flags & SDHCI_USE_ADMA)
3885                 mmc->max_segs = 128;
3886         else if (host->flags & SDHCI_USE_SDMA)
3887                 mmc->max_segs = 1;
3888         else /* PIO */
3889                 mmc->max_segs = 128;
3890
3891         /*
3892          * Maximum number of sectors in one transfer. Limited by DMA boundary
3893          * size (512KiB).
3894          */
3895         mmc->max_req_size = 524288;
3896
3897         /*
3898          * Maximum segment size. Could be one segment with the maximum number
3899          * of bytes. When doing hardware scatter/gather, each entry cannot
3900          * be larger than 64 KiB though.
3901          */
3902         if (host->flags & SDHCI_USE_ADMA) {
3903                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3904                         mmc->max_seg_size = 65535;
3905                 else
3906                         mmc->max_seg_size = 65536;
3907         } else {
3908                 mmc->max_seg_size = mmc->max_req_size;
3909         }
3910
3911         /*
3912          * Maximum block size. This varies from controller to controller and
3913          * is specified in the capabilities register.
3914          */
3915         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3916                 mmc->max_blk_size = 2;
3917         } else {
3918                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3919                                 SDHCI_MAX_BLOCK_SHIFT;
3920                 if (mmc->max_blk_size >= 3) {
3921                         pr_info("%s: Invalid maximum block size, "
3922                                 "assuming 512 bytes\n", mmc_hostname(mmc));
3923                         mmc->max_blk_size = 0;
3924                 }
3925         }
3926
3927         mmc->max_blk_size = 512 << mmc->max_blk_size;
3928
3929         /*
3930          * Maximum block count.
3931          */
3932         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3933
3934         /*
3935          * Init tasklets.
3936          */
3937         tasklet_init(&host->card_tasklet,
3938                 sdhci_tasklet_card, (unsigned long)host);
3939         tasklet_init(&host->finish_tasklet,
3940                 sdhci_tasklet_finish, (unsigned long)host);
3941
3942         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3943
3944         if (host->version >= SDHCI_SPEC_300) {
3945                 init_waitqueue_head(&host->buf_ready_int);
3946
3947                 /* Initialize re-tuning timer */
3948                 init_timer(&host->tuning_timer);
3949                 host->tuning_timer.data = (unsigned long)host;
3950                 host->tuning_timer.function = sdhci_tuning_timer;
3951         }
3952
3953         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
3954                 mmc_hostname(mmc), host);
3955         if (ret) {
3956                 pr_err("%s: Failed to request IRQ %d: %d\n",
3957                        mmc_hostname(mmc), host->irq, ret);
3958                 goto untasklet;
3959         }
3960
3961         sdhci_init(host, 0);
3962
3963         host->sysedpc = sysedp_create_consumer(dev_name(mmc_dev(mmc)),
3964                                                dev_name(mmc_dev(mmc)));
3965
3966 #ifdef CONFIG_MMC_DEBUG
3967         sdhci_dumpregs(host);
3968 #endif
3969
3970 #ifdef SDHCI_USE_LEDS_CLASS
3971         snprintf(host->led_name, sizeof(host->led_name),
3972                 "%s::", mmc_hostname(mmc));
3973         host->led.name = host->led_name;
3974         host->led.brightness = LED_OFF;
3975         host->led.default_trigger = mmc_hostname(mmc);
3976         host->led.brightness_set = sdhci_led_control;
3977
3978         ret = led_classdev_register(mmc_dev(mmc), &host->led);
3979         if (ret) {
3980                 pr_err("%s: Failed to register LED device: %d\n",
3981                        mmc_hostname(mmc), ret);
3982                 goto reset;
3983         }
3984 #endif
3985
3986         mmiowb();
3987
3988         mmc_add_host(mmc);
3989
3990         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3991                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3992                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3993                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3994
3995         sdhci_enable_card_detection(host);
3996 #ifdef CONFIG_DEBUG_FS
3997         /* Add debugfs nodes */
3998         sdhci_debugfs_init(host);
3999 #endif
4000
4001         return 0;
4002
4003 #ifdef SDHCI_USE_LEDS_CLASS
4004 reset:
4005         sdhci_reset(host, SDHCI_RESET_ALL);
4006         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
4007         free_irq(host->irq, host);
4008 #endif
4009 untasklet:
4010         tasklet_kill(&host->card_tasklet);
4011         tasklet_kill(&host->finish_tasklet);
4012
4013         return ret;
4014 }
4015
4016 EXPORT_SYMBOL_GPL(sdhci_add_host);
4017
4018 void sdhci_remove_host(struct sdhci_host *host, int dead)
4019 {
4020         unsigned long flags;
4021
4022         if (dead) {
4023                 spin_lock_irqsave(&host->lock, flags);
4024
4025                 host->flags |= SDHCI_DEVICE_DEAD;
4026
4027                 if (host->mrq) {
4028                         pr_err("%s: Controller removed during "
4029                                 " transfer!\n", mmc_hostname(host->mmc));
4030
4031                         host->mrq->cmd->error = -ENOMEDIUM;
4032                         tasklet_schedule(&host->finish_tasklet);
4033                 }
4034
4035                 spin_unlock_irqrestore(&host->lock, flags);
4036         }
4037
4038         sdhci_disable_card_detection(host);
4039
4040         mmc_remove_host(host->mmc);
4041
4042 #ifdef SDHCI_USE_LEDS_CLASS
4043         led_classdev_unregister(&host->led);
4044 #endif
4045
4046         if (!dead)
4047                 sdhci_reset(host, SDHCI_RESET_ALL);
4048
4049         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
4050         free_irq(host->irq, host);
4051
4052         del_timer_sync(&host->timer);
4053
4054         tasklet_kill(&host->card_tasklet);
4055         tasklet_kill(&host->finish_tasklet);
4056
4057         if (host->vmmc) {
4058                 regulator_disable(host->vmmc);
4059                 regulator_put(host->vmmc);
4060         }
4061
4062         if (host->vqmmc) {
4063                 regulator_disable(host->vqmmc);
4064                 regulator_put(host->vqmmc);
4065         }
4066
4067         if (host->use_dma_alloc) {
4068                 dma_free_coherent(mmc_dev(host->mmc), (128 * 2 + 1) * 8,
4069                                 host->adma_desc, host->adma_addr);
4070                 dma_free_coherent(mmc_dev(host->mmc), 128 * 8,
4071                                 host->align_buffer, host->align_addr);
4072         } else {
4073                 kfree(host->adma_desc);
4074                 kfree(host->align_buffer);
4075         }
4076
4077         host->adma_desc = NULL;
4078         host->align_buffer = NULL;
4079
4080         sysedp_free_consumer(host->sysedpc);
4081         host->sysedpc = NULL;
4082 }
4083
4084 EXPORT_SYMBOL_GPL(sdhci_remove_host);
4085
4086 void sdhci_free_host(struct sdhci_host *host)
4087 {
4088         mmc_free_host(host->mmc);
4089 }
4090
4091 EXPORT_SYMBOL_GPL(sdhci_free_host);
4092
4093 /*****************************************************************************\
4094  *                                                                           *
4095  * Driver init/exit                                                          *
4096  *                                                                           *
4097 \*****************************************************************************/
4098
4099 static int __init sdhci_drv_init(void)
4100 {
4101         pr_info(DRIVER_NAME
4102                 ": Secure Digital Host Controller Interface driver\n");
4103         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4104
4105         return 0;
4106 }
4107
4108 static void __exit sdhci_drv_exit(void)
4109 {
4110 }
4111
4112 module_init(sdhci_drv_init);
4113 module_exit(sdhci_drv_exit);
4114
4115 module_param(debug_quirks, uint, 0444);
4116 module_param(debug_quirks2, uint, 0444);
4117
4118 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4119 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4120 MODULE_LICENSE("GPL");
4121
4122 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4123 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");