-+// SCI Control Register 1 (SCCR1) $FFFC0A
-+
-+// 8 4 2 1 - 8 4 2 1 - 8 4 2 1 - 8 4 2 1
-+// ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
-+// | | | | | | | | | | | | | | | |
-+// | | | | | | | | | | | | | | | +----- 0 send a break
-+// | | | | | | | | | | | | | | +------- 1 rcvr wakeup mode
-+// | | | | | | | | | | | | | +--------- 2 rcvr enable
-+// | | | | | | | | | | | | +----------- 3 xmtr enable
-+// | | | | | | | | | | | |
-+// | | | | | | | | | | | +--------------- 4 idle line intr enable
-+// | | | | | | | | | | +----------------- 5 rcvr intr enable
-+// | | | | | | | | | +------------------- 6 xmit complete intr enable
-+// | | | | | | | | +--------------------- 7 xmtr intr enable
-+// | | | | | | | |
-+// | | | | | | | +------------------------- 8 wakeup on address mark
-+// | | | | | | +--------------------------- 9 mode 1=9 bits, 0=8 bits
-+// | | | | | +----------------------------- 10 parity enable 1=on, 0=off
-+// | | | | +------------------------------- 11 parity type 1=odd, 0=even
-+// | | | |
-+// | | | +----------------------------------- 12 idle line select
-+// | | +------------------------------------- 13 wired-or mode
-+// | +--------------------------------------- 14 loop mode
-+// +----------------------------------------- 15 unused
-+
-+// 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 reset value
-+
-+#define SCI_SEND_BREAK 0x0001 // 0000-0000-0000-0001
-+#define SCI_RCVR_WAKEUP 0x0002 // 0000-0000-0000-0010
-+#define SCI_ENABLE_RCVR 0x0004 // 0000-0000-0000-0100
-+#define SCI_ENABLE_XMTR 0x0008 // 0000-0000-0000-1000
-+
-+#define SCI_DISABLE_RCVR 0xFFFB // 1111-1111-1111-1011
-+#define SCI_DISABLE_XMTR 0xFFF7 // 1111-1111-1111-0111
-+
-+#define SCI_ENABLE_INT_IDLE 0x0010 // 0000-0000-0001-0000
-+#define SCI_ENABLE_INT_RX 0x0020 // 0000-0000-0010-0000
-+#define SCI_ENABLE_INT_TX_DONE 0x0040 // 0000-0000-0100-0000
-+#define SCI_ENABLE_INT_TX 0x0080 // 0000-0000-1000-0000
-+
-+#define SCI_DISABLE_INT_ALL 0xFF00 // 1111-1111-0000-0000 ???
-+
-+#define SCI_DISABLE_INT_RX 0xFFDF // 1111-1111-1101-1111
-+#define SCI_CLEAR_RX_INT 0xFFBF // 1111-1111-1011-1111
-+#define SCI_DISABLE_INT_TX 0xFF7F // 1111-1111-0111-1111
-+#define SCI_CLEAR_TDRE 0xFEFF // 1111-1110-1111-1111
-+
-+#define SCI_RCVR_WAKE_ON_MARK 0x0100 // 0000-0001-0000-0000
-+#define SCI_9_DATA_BITS 0x0200 // 0000-0010-0000-0000
-+#define SCI_PARITY_ENABLE 0x0400 // 0000-0100-0000-0000
-+#define SCI_PARITY_ODD 0x0800 // 0000-1000-0000-0000
-+
-+#define SCI_RCVR_WAKE_ON_IDLE 0xFEFF // 1111-1110-1111-1111
-+#define SCI_8_DATA_BITS 0xFDFF // 1111-1101-1111-1111
-+#define SCI_PARITY_DISABLE 0xFBFF // 1111-1011-1111-1111
-+#define SCI_PARITY_EVEN 0xF7FF // 1111-0111-1111-1111
-+
-+#define SCI_PARITY_NONE 0xF3FF // 1111-0011-1111-1111
-+
-+#define SCI_IDLE_LINE_LONG 0x1000 // 0001-0000-0000-0000
-+#define SCI_TXD_OPEN_DRAIN 0x2000 // 0010-0000-0000-0000
-+#define SCI_LOOPBACK_MODE 0x4000 // 0100-0000-0000-0000
-+#define SCI_SCCR1_UNUSED 0x8000 // 1000-0000-0000-0000
++/* SCI Control Register 1 (SCCR1) $FFFC0A
++
++ 8 4 2 1 - 8 4 2 1 - 8 4 2 1 - 8 4 2 1
++ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
++ | | | | | | | | | | | | | | | |
++ | | | | | | | | | | | | | | | +----- 0 send a break
++ | | | | | | | | | | | | | | +------- 1 rcvr wakeup mode
++ | | | | | | | | | | | | | +--------- 2 rcvr enable
++ | | | | | | | | | | | | +----------- 3 xmtr enable
++ | | | | | | | | | | | |
++ | | | | | | | | | | | +--------------- 4 idle line intr enable
++ | | | | | | | | | | +----------------- 5 rcvr intr enable
++ | | | | | | | | | +------------------- 6 xmit complete intr enable
++ | | | | | | | | +--------------------- 7 xmtr intr enable
++ | | | | | | | |
++ | | | | | | | +------------------------- 8 wakeup on address mark
++ | | | | | | +--------------------------- 9 mode 1=9 bits, 0=8 bits
++ | | | | | +----------------------------- 10 parity enable 1=on, 0=off
++ | | | | +------------------------------- 11 parity type 1=odd, 0=even
++ | | | |
++ | | | +----------------------------------- 12 idle line select
++ | | +------------------------------------- 13 wired-or mode
++ | +--------------------------------------- 14 loop mode
++ +----------------------------------------- 15 unused
++
++ 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 reset value
++*/
++
++#define SCI_SEND_BREAK 0x0001 /* 0000-0000-0000-0001 */
++#define SCI_RCVR_WAKEUP 0x0002 /* 0000-0000-0000-0010 */
++#define SCI_ENABLE_RCVR 0x0004 /* 0000-0000-0000-0100 */
++#define SCI_ENABLE_XMTR 0x0008 /* 0000-0000-0000-1000 */
++
++#define SCI_DISABLE_RCVR 0xFFFB /* 1111-1111-1111-1011 */
++#define SCI_DISABLE_XMTR 0xFFF7 /* 1111-1111-1111-0111 */
++
++#define SCI_ENABLE_INT_IDLE 0x0010 /* 0000-0000-0001-0000 */
++#define SCI_ENABLE_INT_RX 0x0020 /* 0000-0000-0010-0000 */
++#define SCI_ENABLE_INT_TX_DONE 0x0040 /* 0000-0000-0100-0000 */
++#define SCI_ENABLE_INT_TX 0x0080 /* 0000-0000-1000-0000 */
++
++#define SCI_DISABLE_INT_ALL 0xFF00 /* 1111-1111-0000-0000 ??? */
++
++#define SCI_DISABLE_INT_RX 0xFFDF /* 1111-1111-1101-1111 */
++#define SCI_CLEAR_RX_INT 0xFFBF /* 1111-1111-1011-1111 */
++#define SCI_DISABLE_INT_TX 0xFF7F /* 1111-1111-0111-1111 */
++#define SCI_CLEAR_TDRE 0xFEFF /* 1111-1110-1111-1111 */
++
++#define SCI_RCVR_WAKE_ON_MARK 0x0100 /* 0000-0001-0000-0000 */
++#define SCI_9_DATA_BITS 0x0200 /* 0000-0010-0000-0000 */
++#define SCI_PARITY_ENABLE 0x0400 /* 0000-0100-0000-0000 */
++#define SCI_PARITY_ODD 0x0800 /* 0000-1000-0000-0000 */
++
++#define SCI_RCVR_WAKE_ON_IDLE 0xFEFF /* 1111-1110-1111-1111 */
++#define SCI_8_DATA_BITS 0xFDFF /* 1111-1101-1111-1111 */
++#define SCI_PARITY_DISABLE 0xFBFF /* 1111-1011-1111-1111 */
++#define SCI_PARITY_EVEN 0xF7FF /* 1111-0111-1111-1111 */
++
++#define SCI_PARITY_NONE 0xF3FF /* 1111-0011-1111-1111 */
++
++#define SCI_IDLE_LINE_LONG 0x1000 /* 0001-0000-0000-0000 */
++#define SCI_TXD_OPEN_DRAIN 0x2000 /* 0010-0000-0000-0000 */
++#define SCI_LOOPBACK_MODE 0x4000 /* 0100-0000-0000-0000 */
++#define SCI_SCCR1_UNUSED 0x8000 /* 1000-0000-0000-0000 */