rtems-patches/current/rtems-update-ss555-to-ec555-cpld-remove.patch

   1 ---
   2  c/src/lib/libbsp/powerpc/ec555/include/bsp.h    |   31 ------------------------
   3  c/src/lib/libbsp/powerpc/ec555/startup/iss555.c |    5 +++
   4  c/src/lib/libbsp/powerpc/ec555/startup/linkcmds |    8 ------
   5  3 files changed, 5 insertions(+), 39 deletions(-)
   6
   7 Index: rtems-4.9.3/c/src/lib/libbsp/powerpc/ec555/include/bsp.h
   8 ===================================================================
   9 --- rtems-4.9.3.orig/c/src/lib/libbsp/powerpc/ec555/include/bsp.h       2007-12-11 16:46:51.000000000 +0100
  10 +++ rtems-4.9.3/c/src/lib/libbsp/powerpc/ec555/include/bsp.h    2009-11-29 01:52:21.559557050 +0100
  11 @@ -44,37 +44,6 @@
  12  #define BSP_CRYSTAL_HZ          4000000        /* crystal frequency, Hz */
  13  #define BSP_CLOCK_HZ   40000000        /* CPU clock frequency, Hz
  14
  15 -/*
  16 - * I/O definitions
  17 - *
  18 - * The SS555 board includes a CPLD to control on-board features and
  19 - * off-board devices.
  20 - */
  21 -typedef struct cpld_ {
  22 -  uint8_t      cs3a[32];               /* Chip select 3A */
  23 -  uint8_t      pad0[0x200000 - 0x000020];
  24 -
  25 -  uint8_t      cs3b[32];               /* Chip select 3B */
  26 -  uint8_t      pad2[0x400000 - 0x200020];
  27 -
  28 -  uint8_t      cs3c[32];               /* Chip select 3C */
  29 -  uint8_t      pad4[0x600000 - 0x400020];
  30 -
  31 -  uint8_t      cs3d[32];               /* Chip select 3D */
  32 -  uint8_t      pad6[0x800000 - 0x600020];
  33 -
  34 -  uint8_t      serial_ints;    /* Enable/disable serial interrupts */
  35 -  uint8_t      serial_resets;  /* Enable/disable serial resets */
  36 -  uint8_t      serial_ack;     /* Acknowledge serial transfers */
  37 -  uint8_t      pad8[0xA00000 - 0x800003];
  38 -
  39 -  uint8_t      iflash_writess; /* Enable/disable internal-flash writes */
  40 -  uint8_t      nflash_writess; /* Enable/disable NAND-flash writes */
  41 -  uint8_t      padA[0xC00000 - 0xA00002];
  42 -} cpld_t;
  43 -
  44 -extern volatile cpld_t cpld;              /* defined in linkcmds */
  45 -
  46  /* miscellaneous stuff assumed to exist */
  47
  48  /*
  49 Index: rtems-4.9.3/c/src/lib/libbsp/powerpc/ec555/startup/iss555.c
  50 ===================================================================
  51 --- rtems-4.9.3.orig/c/src/lib/libbsp/powerpc/ec555/startup/iss555.c    2009-11-29 01:38:37.616586852 +0100
  52 +++ rtems-4.9.3/c/src/lib/libbsp/powerpc/ec555/startup/iss555.c 2009-11-29 01:52:21.559557050 +0100
  53 @@ -96,6 +96,8 @@
  54     */
  55    extern char int_ram_top[];           /* top of internal ram */
  56
  57 +#if 0
  58 +
  59    usiu.memc[0]._or =
  60        USIU_MEMC_OR_512K                        /* bank size */
  61      | USIU_MEMC_OR_SCY(0)              /* wait states in first beat of burst */
  62 @@ -127,6 +129,9 @@
  63      | USIU_MEMC_BR_BI                  /* inhibit bursting */
  64      | USIU_MEMC_BR_V;                  /* base register valid */
  65
  66 +
  67 +#endif
  68 +
  69    /*
  70     * Disable show cycles and serialization so that burst accesses will work
  71     * properly.  A different value, such as 0x0, may be more appropriate for
  72 Index: rtems-4.9.3/c/src/lib/libbsp/powerpc/ec555/startup/linkcmds
  73 ===================================================================
  74 --- rtems-4.9.3.orig/c/src/lib/libbsp/powerpc/ec555/startup/linkcmds    2008-03-04 00:07:19.000000000 +0100
  75 +++ rtems-4.9.3/c/src/lib/libbsp/powerpc/ec555/startup/linkcmds 2009-11-29 01:52:21.559557050 +0100
  76 @@ -268,14 +268,6 @@
  77      sram = .;
  78    }
  79
  80 -  /*
  81 -   * SS555 external devices managed by on-board CPLD
  82 -   */
  83 -  .cpld 0xFF000000:            /* SS555 external CPLD devices */
  84 -  {
  85 -    cpld = .;
  86 -  }
  87 -
  88
  89    /* Stabs debugging sections.  */
  90    .stab 0 : { *(.stab) }