2 c/src/lib/libbsp/m68k/mo376/clock/ckinit.c | 2
3 c/src/lib/libbsp/m68k/mo376/include/bsp.h | 26 +
4 c/src/lib/libbsp/m68k/mo376/include/mo376.h | 27 -
5 c/src/lib/libbsp/m68k/mo376/misc/gdbinit68 | 395 ++++++++++++++++++++++-
6 c/src/lib/libbsp/m68k/mo376/spurious/spinit.c | 10
7 c/src/lib/libbsp/m68k/mo376/startup/linkcmds | 10
8 c/src/lib/libbsp/m68k/mo376/startup/linkcmds_ROM | 17
9 c/src/lib/libbsp/m68k/mo376/startup/start_c.c | 6
10 make/custom/mo376.cfg | 10
11 9 files changed, 455 insertions(+), 48 deletions(-)
13 Index: rtems-4.9.3/c/src/lib/libbsp/m68k/mo376/include/bsp.h
14 ===================================================================
15 --- rtems-4.9.3.orig/c/src/lib/libbsp/m68k/mo376/include/bsp.h 2009-11-29 01:23:46.804588750 +0100
16 +++ rtems-4.9.3/c/src/lib/libbsp/m68k/mo376/include/bsp.h 2009-11-29 01:36:40.412590325 +0100
20 - * This include file contains all mrm board IO definitions.
21 + * This include file contains all mo376 board IO definitions.
23 * COPYRIGHT (c) 1989-1999.
24 * On-Line Applications Research Corporation (OAR).
26 /* #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2 */
29 + * Network driver configuration
31 +struct rtems_bsdnet_ifconfig;
32 +extern int cs8900_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching);
33 +#define RTEMS_BSP_NETWORK_DRIVER_NAME "cs8900"
34 +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH cs8900_driver_attach
36 +/* CS8900 ethernet interface definitions */
38 +#define CS8900_DEVICES (1)
39 +#define CS8900_IO_BASE (0x0300)
40 +#define CS8900_MEMORY_BASE (0x1000)
41 +#define CS8900_DATA_BUS_SWAPPED
42 +#define CS8900_IO_MODE
43 +#define CS8900_RX_QUEUE_SIZE (50)
45 +#define ETHERNET_BASE (0xf8a000)
46 +#define ETHERNET_IRQ_LEVEL (2)
47 +#define ETHERNET_IRQ_PRIORITY (2)
48 +#define ETHERNET_IRQ_VECTOR (26)
49 +/* #define ETHERNET_IRQ_VECTOR (AUTOVEC_VECTOR + ETHERNET_IRQ_LEVEL) */
50 +#define ETHERNET_MAC_ADDRESS {0x00,0x00,0xc0,0x2c,0x54,0xa4}
53 * Simple spin delay in microsecond units for device drivers.
54 * This is very dependent on the clock speed of the target.
56 Index: rtems-4.9.3/c/src/lib/libbsp/m68k/mo376/clock/ckinit.c
57 ===================================================================
58 --- rtems-4.9.3.orig/c/src/lib/libbsp/m68k/mo376/clock/ckinit.c 2009-11-29 01:23:46.808556503 +0100
59 +++ rtems-4.9.3/c/src/lib/libbsp/m68k/mo376/clock/ckinit.c 2009-11-29 01:36:40.412590325 +0100
61 Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 );
63 /* enable 1mS interrupts */
64 - *PITR = (unsigned short int)( SAM(0x09,0,PITM) );/* load counter */
65 + *PITR = (unsigned short int)( SAM(0x08,0,PITM) );/* load counter */
66 *PICR = (unsigned short int) /* enable interrupt */
67 ( SAM(ISRL_PIT,8,PIRQL) | SAM(CLOCK_VECTOR,0,PIV) );
69 Index: rtems-4.9.3/c/src/lib/libbsp/m68k/mo376/misc/gdbinit68
70 ===================================================================
71 --- rtems-4.9.3.orig/c/src/lib/libbsp/m68k/mo376/misc/gdbinit68 2009-11-29 01:11:56.471556761 +0100
72 +++ rtems-4.9.3/c/src/lib/libbsp/m68k/mo376/misc/gdbinit68 2009-11-29 01:36:40.412590325 +0100
75 # $Id: gdbinit68,v 1.1 2001/05/25 16:28:46 joel Exp $
77 -echo Setting up the environment for mrm debuging.\n
78 +echo Setting up the environment for mo376 debuging.\n
80 -target bdm /dev/bdmcpu320
82 +# invoke by "source run376.gdb"
93 +#target bdm /dev/m683xx-bdm/icd0
94 +#target bdm /dev/icd_bdm0
95 +#target bdm /dev/pd_bdm0
98 +#target bdm bdm-cpu32-icd1
102 +#target remote /dev/ttyS1
104 +# automatic resed of board before "run" command execution
105 +# depends on correct "cpu32init" file in current ditectory
108 +# confirmation of dangerous operations (kill, run, ..)
111 +#===========================================================
112 +# sets chipselects and configuration
114 +echo bdm_hw_init ...\n
128 +# system configuration
130 +# 0xFFFA00 - SIMCR - SIM Configuration Register
131 +# 15 14 13 12 11 10 9 8 7 6 5 4 3 0
132 +# EXOFF FRZSW FRZBM 0 SLVEN 0 SHEN SUPV MM 0 0 IARB
133 +# 0 0 0 0 DATA11 0 0 0 1 1 0 0 1 1 1 1
134 +# set *(short *)0xfffa00=0x42cf
135 +set *(short *)0xfffa00=0x40cf
137 +# 0xFFFA21 - SYPCR - System Protection Control Register
139 +# SWE SWP SWT HME BME BMT
140 +# 1 MODCLK 0 0 0 0 0 0
141 +set *(char *)0xfffa21=0x06
143 +# 0xYFFA27 - SWSR - Software Service Register
144 +# write 0x55 0xAA for watchdog
146 +# 0xFFFA04 - SYNCR Clock Synthesizer Control Register
147 +# 15 14 13 8 7 6 5 4 3 2 1 0
148 +# W X Y EDIV 0 0 SLIMP SLOCK RSTEN STSIM STEXT
149 +# 0 0 1 1 1 1 1 1 0 0 0 U U 0 0 0
150 +#set *(short *)0xfffa04=0xd408
151 +# set 21 MHz system clock for ref 4 MHz
153 +# $YFFA17 - PEPAR - Port E Pin Assignment Register
155 +# PEPA7 PEPA6 PEPA5 PEPA4 PEPA3 PEPA2 PEPA1 PEPA0
156 +# SIZ1 SIZ0 AS DS RMC AVEC DSACK1 DSACK0
157 +# 1 .. control signal, 0 .. port F
158 +# after reset determined by DATA8
159 +set *(char*)0xfffa17=0xf4
161 +# 0xFFFA1F - PFPAR - Port F Pin Assignment Register
163 +# PFPA7 PFPA6 PFPA5 PFPA4 PFPA3 PFPA2 PFPA1 PFPA0
164 +# INT7 INT6 INT5 INT4 INT3 INT2 INT1 MODCLK
165 +# 1 .. control signal, 0 .. port F
166 +# after reset determined by DATA9
167 +set *(char*)0xfffa1f=0
169 +# Setup internal RAM
171 +# setup STANBY RAM at 0x8000
173 +set *(short *)0xFFFB40=0x8000
175 +set *(int *)0xFFFB44=0xFFD000
177 +set *(short *)0xFFFB40=0
179 +# setup TPU RAM at 0x8000
181 +set *(short *)0xFFFB00=0x8000
183 +set *(short *)0xFFFB04=0xFFE000>>8
185 +set *(short *)0xFFFB00=0
187 +# 0xYFFA44 - CSPAR0 - Chip Select Pin Assignment Register 0
188 +# 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
189 +# 0 0 CSPA0[6] CSPA0[5] CSPA0[4] CSPA0[3] CSPA0[2] CSPA0[1] CSBOOT
190 +# 0 0 DATA2 1 DATA2 1 DATA2 1 DATA1 1 DATA1 1 DATA1 1 1 DATA0
191 +# CS5 CS4 CS3 CS2 CS1 CS0 CSBOOT
192 +# FC2 PC2 FC1 PC1 FC0 PC0 BGACK BG BR
194 +# 00 Discrete Output
195 +# 01 Alternate Function
196 +# 10 Chip Select (8-Bit Port)
197 +# 11 Chip Select (16-Bit Port)
199 +set *(short *)0xfffa44=0x3bff
200 +# CS4 8-bit rest 16-bit
203 +# 0xFFFA46 - CSPAR1 - Chip Select Pin Assignment Register 1
204 +# 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
205 +# 0 0 0 0 0 0 CSPA1[4] CSPA1[3] CSPA1[2] CSPA1[1] CSPA1[0]
206 +# 0 0 0 0 0 0 DATA7 1 DATA76 1 DATA75 1 DATA74 1 DATA73 1
207 +# CS10 CS9 CS8 CS7 CS6
208 +# A23 ECLK A22 PC6 A21 PC5 A20 PC4 A19 PC3
210 +set *(short *)0xfffa46=0x03a9
211 +# CS7,CS8,CS9 8-bit CS10 16-bit and A19
214 +# Chip selects configuration
216 +# 0xFFFA48 - CSBARBT - Chip-Select Base Address Register Boot ROM
217 +# 0xFFFA4C..0xFFFA74 - CSBAR[10:0] - Chip-Select Base Address Registers
218 +# 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
219 +# A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 BLKSZ
220 +# reset 0x0003 for CSBARBT and 0x0000 for CSBAR[10:0]
222 +# BLKSZ Size Address Lines Compared
223 +# 000 2k ADDR[23:11]
224 +# 001 8k ADDR[23:13]
225 +# 010 16k ADDR[23:14]
226 +# 011 64k ADDR[23:16]
227 +# 100 128k ADDR[23:17]
228 +# 101 256k ADDR[23:18]
229 +# 110 512k ADDR[23:19]
230 +# 111 1M ADDR[23:20]
233 +# 0xFFFA4A - CSORBT - Chip-Select Option Register Boot ROM
234 +# 0xFFFA4E..0xFFFA76 - CSOR[10:0] - Chip-Select Option Registers
235 +# 15 14 13 12 11 10 9 6 5 4 3 1 0
236 +# MODE BYTE R/W STRB DSACK SPACE IPL AVEC
237 +# 0 1 1 1 1 0 1 1 0 1 1 1 0 0 0 0 - for CSORBT
239 +# BYTE 00 Disable, 01 Lower Byte, 10 Upper Byte, 11 Both Bytes
240 +# R/W 00 Reserved,01 Read Only, 10 Write Only, 11 Read/Write
241 +# SPACE 00 CPU, 01 User, 10 Supervisor, 11 Supervisor/User
243 +set *(short *)0xfffa48=(0x800000>>8)&0xfff8 | 7
244 +set *(short *)0xfffa4a=(0<<15)|(3<<13)|(3<<11)|(0<<10)|(0<<6)|(3<<4)
245 +# BOOT ROM 0x800000 1MB RW UL
247 +set *(short *)0xfffa4c=(0x900000>>8)&0xfff8 | 7
248 +set *(short *)0xfffa4e=(0<<15)|(3<<13)|(3<<11)|(0<<10)|(0<<6)|(3<<4)
249 +# CS0 ROM 0x900000 1MB RW UL
251 +#set *(long *)0xfffa50=0x0003303e
252 +# CS1 RAM 0x000000 64k WR L
254 +set *(short *)0xfffa54=(0x000000>>8)&0xfff8 | 7
255 +set *(short *)0xfffa56=(0<<15)|(3<<13)|(3<<11)|(0<<10)|(0<<6)|(3<<4)
256 +# CS2 RAM 0x000000 1MB RW UL - Main RAM first 1MB
258 +#set *(short *)0xfffa58=(0x100000>>8)&0xfff8 | 7
259 +#set *(short *)0xfffa5A=(0<<15)|(3<<13)|(3<<11)|(0<<10)|(0<<6)|(3<<4)
260 +# CS3 RAM 0x100000 1MB RW UL - Main RAM second 1MB
262 +set *(short *)0xfffa5c=(0xf00000>>8)&0xfff8 | 6
263 +set *(short *)0xfffa5e=(0<<15)|(3<<13)|(3<<11)|(1<<10)|(2<<6)|(3<<4)
264 +# CS4 PER 0xf00000 512kB RW UL - CMOS RAM, RTC, other devices
266 +#set *(long *)0xfffa60=0xffe8783f
269 +#set *(long *)0xfffa64=0x100438f0
270 +# CS6 R/R 0x100000 128k RW L
272 +set *(short *)0xfffa68=(0xf87000>>8)&0xfff8 | 0
273 +set *(short *)0xfffa6a=(0<<15)|(3<<13)|(3<<11)|(1<<10)|(1<<6)|(3<<4)
274 +# CS7 PER 0xf87000 2k RW UL - MO_PWR
276 +set *(short *)0xfffa6c=(0xf88000>>8)&0xfff8 | 0
277 +set *(short *)0xfffa6e=(0<<15)|(3<<13)|(3<<11)|(1<<10)|(1<<6)|(3<<4)
278 +# CS8 PER 0xf88000 2k RO UL - IRC
280 +set *(short *)0xfffa70=(0xf89000>>8)&0xfff8 | 0
281 +set *(short *)0xfffa72=(0<<15)|(3<<13)|(3<<11)|(1<<10)|(3<<6)|(3<<4)
282 +# CS9 PER 0xf89000 2k WR UL - KBD
284 +#set *(long *)0xfffa74=0x01035030
285 +# CS10 RAM 0x010000 64k WR U
290 +#set *(long *)0xfffa58=0x02036870
291 +# CS3 RAM 0x020000 64k RO UL
293 +#set *(long *)0xfffa64=0x02033030
294 +# CS6 RAM 0x020000 64k WR L
296 +#set *(long *)0xfffa68=0x02035030
297 +# CS7 RAM 0x020000 64k WR U
302 +# SR=PS Status Register
303 +# 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0
304 +# T1 T0 S 0 0 IP___ 0 0 0 X N Z V C
305 +# 0 0 1 0 0 1 1 1 0 0 0 U U U U U
310 +#===========================================================
312 +# sets well defined values into VBR
315 + set $vbr_val=(unsigned)$vbr
317 + set *(unsigned*)($vbr_val+$vec_num*4)=($vec_num*16)+0xf0000
322 +# Test writability of RAM location
323 +define bdm_test_ram_acc
326 + set $ram_addr=(unsigned int)$arg0
327 + set $old_ram_val0=*(int*)$ram_addr
328 + set $old_ram_val1=*(int*)($ram_addr+4)
329 + set *(int*)($ram_addr+3)=0xff234567
330 + set *(int*)$ram_addr=0x12345678
331 + if *(int*)$ram_addr!=0x12345678
332 + printf "Error1 %08X\n",*(int*)$ram_addr
334 + set *(char*)$ram_addr=0xab
335 + if *(int*)$ram_addr!=0xab345678
336 + printf "Error2 %08X\n",*(int*)$ram_addr
338 + set *(char*)($ram_addr+1)=0xcd
339 + if *(int*)$ram_addr!=0xabcd5678
340 + printf "Error3 %08X\n",*(int*)$ram_addr
342 + set *(char*)($ram_addr+3)=0x01
343 + if *(int*)$ram_addr!=0xabcd5601
344 + printf "Error4 %08X\n",*(int*)$ram_addr
346 + set *(char*)($ram_addr+2)=0xef
347 + if *(int*)$ram_addr!=0xabcdef01
348 + printf "Error5 %08X\n",*(int*)$ram_addr
350 + if *(int*)$ram_addr!=0xabcdef01
351 + printf "Error5 %08X\n",*(int*)$ram_addr
353 + if *(int*)($ram_addr+1)!=0xcdef0123
354 + printf "Error6 %08X\n",*(int*)$ram_addr
356 + if *(int*)($ram_addr+2)!=0xef012345
357 + printf "Error7 %08X\n",*(int*)$ram_addr
359 + if *(int*)($ram_addr+2)!=0xef012345
360 + printf "Error8 %08X\n",*(int*)$ram_addr
362 + if *(int*)($ram_addr+3)!=0x01234567
363 + printf "Error9 %08X\n",*(int*)$ram_addr
365 + set *(int*)$ram_addr=$old_ram_val0
366 + set *(int*)($ram_addr+4)=$old_ram_val1
369 +# Read flash identification
370 +define bdm_read_flash_id
371 + set $flash_base=(int)$arg0&~0xffff
372 + output /x $flash_base
374 + set *(char*)($flash_base+0x555*2+1)=0xf0
375 + set *(char*)($flash_base+0x555*2+1)=0xaa
376 + set *(char*)($flash_base+0x2aa*2+1)=0x55
377 + set *(char*)($flash_base+0x555*2+1)=0x90
378 + p /x *(char*)($flash_base+0x00*2+1)
379 + set *(char*)($flash_base+0x555*2+1)=0xf0
380 + set *(char*)($flash_base+0x555*2+1)=0xaa
381 + set *(char*)($flash_base+0x2aa*2+1)=0x55
382 + set *(char*)($flash_base+0x555*2+1)=0x90
383 + p /x *(char*)($flash_base+0x01*2+1)
386 +define bdm_read_flash1_id
387 + bdm_read_flash_id 0x800000
390 +define bdm_read_flash2_id
391 + bdm_read_flash_id 0x900000
394 +define bdm_test_flash_write
395 + set $flash_base=(int)$arg0 & ~0xffff
396 + output /x $flash_base
398 + set *(char*)($flash_base+0x555*2+1)=0xf0
399 + set *(char*)($flash_base+0x555*2+1)=0xaa
400 + set *(char*)($flash_base+0x2aa*2+1)=0x55
401 + set *(char*)($flash_base+0x555*2+1)=0xA0
402 + set *(char*)($arg0)=$arg1
405 +define bdm_test_pwm0
407 + #BIUMCR - BIU Module Configuration Register $YFF400
408 + set *(short*)0xfff400=*(short*)0xfff400&~0x8000
409 + #CPCR - CPSM Control Register $YFF408
410 + set *(short*)0xfff408=*(short*)0xfff408|8
411 + #PWM5SIC - PWM5 Status/Interrupt/Control Register $YFF428
412 + set *(short*)0xfff428=0x18
413 + #PWM5A1 - PWM5 Period Register $YFF42A
414 + set *(short*)0xfff42a=512
415 + #PWM5B1 - PWM5 Pulse Width Register $YFF42C
416 + set *(short*)0xfff42c=0
419 + set *(short*)0xf87000=0
423 + set *(char*)0xf87000=1
426 + set *(char*)0xf87000=2
427 + set $pwm_val=-($arg0)
431 + set *(short*)0xfff208=0x8000
433 + set *(short*)0xfff206=~0x8000
435 + #PWM5B1 - PWM5 Pulse Width Register $YFF42C
436 + set *(short*)0xfff42c=$pwm_val
440 +define bdm_test_usd_irc
441 + set $usd_irc_d=0xf88000
442 + set $usd_irc_c=0xf88001
445 + set *(unsigned char*)0xf88020=0
447 + set *(unsigned char*)$usd_irc_c=0x38
449 + set *(unsigned char*)$usd_irc_c=0x49
451 + set *(unsigned char*)$usd_irc_c=0x61
452 + # RLD - Reset BP, BT CT CPT S
453 + set *(unsigned char*)$usd_irc_c=0x05
455 + set *(unsigned char*)$usd_irc_d=0x02
456 + # RLD - Reset BP, PR0 -> PSC
457 + set *(unsigned char*)$usd_irc_c=0x1B
459 + # RLD - Reset BP, CNTR -> OL
460 + set *(unsigned char*)$usd_irc_c=0x11
462 + set $usd_irc_val=((int)(*(unsigned char*)$usd_irc_d))
463 + set $usd_irc_val+=((int)(*(unsigned char*)$usd_irc_d))<<8
464 + set $usd_irc_val+=((int)(*(unsigned char*)$usd_irc_d))<<16
465 + print /x $usd_irc_val
479 Index: rtems-4.9.3/c/src/lib/libbsp/m68k/mo376/include/mo376.h
480 ===================================================================
481 --- rtems-4.9.3.orig/c/src/lib/libbsp/m68k/mo376/include/mo376.h 2009-11-29 01:23:46.816556473 +0100
482 +++ rtems-4.9.3/c/src/lib/libbsp/m68k/mo376/include/mo376.h 2009-11-29 01:36:40.416589786 +0100
484 #define EFI_INT1 25 /* CTS interrupt */
487 -/* System Clock definitions */
488 -#define XTAL 32768.0 /* crystal frequency in Hz */
489 +#define SIM_PFPAR (SIM_CRB + 0x1f)
492 -/* Default MRM clock rate (8.388688 MHz) set by CPU32: */
493 -#define MRM_W 0 /* system clock parameters */
497 +/* System Clock definitions */
498 +#define XTAL 4000000.0 /* crystal frequency in Hz */
502 -#define MRM_W 1 /* system clock parameters */
509 +/* Default MO376 clock rate (21.000 MHz) set by CPU32: */
510 #define MRM_W 1 /* system clock parameters */
516 -#define SYS_CLOCK (XTAL*4.0*(MRM_Y+1)*(1 << (2*MRM_W+MRM_X)))
518 +/*#define SYS_CLOCK (XTAL*4.0*(MRM_Y+1)*(1 << (2*MRM_W+MRM_X)))*/
520 +#define SYS_CLOCK (XTAL/32.0*(MRM_Y+1)*(1 << (2*MRM_W+MRM_X)))
521 #define SCI_BAUD 19200 /* RS232 Baud Rate */
523 /* macros/functions */
524 Index: rtems-4.9.3/c/src/lib/libbsp/m68k/mo376/startup/linkcmds_ROM
525 ===================================================================
526 --- rtems-4.9.3.orig/c/src/lib/libbsp/m68k/mo376/startup/linkcmds_ROM 2008-03-04 00:06:30.000000000 +0100
527 +++ rtems-4.9.3/c/src/lib/libbsp/m68k/mo376/startup/linkcmds_ROM 2009-11-29 01:36:40.416589786 +0100
532 -STARTUP(except_vect_332_ROM.o)
533 +/* Not needed, mo376 uses initialization by mo_flashbb */
534 +/* STARTUP(except_vect_332_ROM.o) */
542 - rom : ORIGIN = 0x90000, LENGTH = 0x70000
543 - ram : ORIGIN = 0x03000, LENGTH = 0x7d000
544 + ram : ORIGIN = 0x001000, LENGTH = 0x0ff000
545 + rom : ORIGIN = 0x808000, LENGTH = 0x0f8000
548 -_RamBase = DEFINED(_RamBase) ? _RamBase : 0x003000;
549 -_RamSize = DEFINED(_RamSize) ? _RamSize : 0x7d000;
550 +_RamBase = DEFINED(_RamBase) ? _RamBase : 0x001000;
551 +_RamSize = DEFINED(_RamSize) ? _RamSize : 0x0ff000;
552 _RamEnd = _RamBase + _RamSize;
554 -__end_of_ram = 0x080000;
555 +__end_of_ram = 0x100000;
556 _copy_data_from_rom = 1;
557 -_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x10000;
558 -_StackSize = DEFINED(_StackSize) ? _StackSize : 0x2000;
559 +_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x40000;
560 +_StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
564 Index: rtems-4.9.3/c/src/lib/libbsp/m68k/mo376/spurious/spinit.c
565 ===================================================================
566 --- rtems-4.9.3.orig/c/src/lib/libbsp/m68k/mo376/spurious/spinit.c 2009-11-29 01:11:56.479557220 +0100
567 +++ rtems-4.9.3/c/src/lib/libbsp/m68k/mo376/spurious/spinit.c 2009-11-29 01:36:40.416589786 +0100
569 rtems_vector_number vector
576 const char * const VectDescrip[] = {
577 _Spurious_Error_[0], _Spurious_Error_[0], _Spurious_Error_[1],
578 _Spurious_Error_[2], _Spurious_Error_[3], _Spurious_Error_[4],
580 _Spurious_Error_[27], _Spurious_Error_[28]};
583 - /*asm volatile ( "movea.l %%sp,%0 " : "=a" (sp) : "0" (sp) ); */
584 + asm volatile ( "movea.l %%sp,%0 " : "=a" (sp) : "0" (sp) );
586 _CPU_ISR_Set_level( 7 );
590 RAW_PUTS("\n\rRTEMS: Spurious interrupt: ");
591 RAW_PUTS((char *)VectDescrip[( (vector>64) ? 64 : vector )]);
592 RAW_PUTS("\n\rRTEMS: Vector: ");
603 /* These vectors used by CPU32bug - don't overwrite them. */
608 (void) set_vector( Spurious_Isr, vector, 1 );
609 Index: rtems-4.9.3/c/src/lib/libbsp/m68k/mo376/startup/linkcmds
610 ===================================================================
611 --- rtems-4.9.3.orig/c/src/lib/libbsp/m68k/mo376/startup/linkcmds 2008-03-04 00:06:30.000000000 +0100
612 +++ rtems-4.9.3/c/src/lib/libbsp/m68k/mo376/startup/linkcmds 2009-11-29 01:36:40.416589786 +0100
615 * Declare some sizes.
617 -_RamBase = DEFINED(_RamBase) ? _RamBase : 0x10000;
618 -_RamSize = DEFINED(_RamSize) ? _RamSize : 0x70000;
619 +_RamBase = DEFINED(_RamBase) ? _RamBase : 0x001000;
620 +_RamSize = DEFINED(_RamSize) ? _RamSize : 0x0ff000;
621 _RamEnd = _RamBase + _RamSize;
622 -_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x10000;
623 -_StackSize = DEFINED(_StackSize) ? _StackSize : 0x2000;
624 +_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x40000;
625 +_StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
629 - ram : ORIGIN = 0x10000, LENGTH = 0x70000
630 + ram : ORIGIN = 0x001000, LENGTH = 0x0ff000
633 _copy_data_from_rom = 0;
634 Index: rtems-4.9.3/make/custom/mo376.cfg
635 ===================================================================
636 --- rtems-4.9.3.orig/make/custom/mo376.cfg 2009-11-29 01:25:58.227563597 +0100
637 +++ rtems-4.9.3/make/custom/mo376.cfg 2009-11-29 01:36:40.416589786 +0100
639 # and (hopefully) optimize for it.
640 CPU_CFLAGS = -mcpu=cpu32
642 -# optimize flag: typically -O2
643 -CFLAGS_OPTIMIZE_V = -O2 -g -fomit-frame-pointer
644 +# Debugging flags: If we debug with optimization on, single-stepping
645 +# sometimes looks a little odd, but there won't be any surprises later.
646 +CFLAGS_DEBUG_V += -O2 -ggdb
647 +CXXFLAGS_DEBUG_V += -O2 -ggdb
649 +# optimize flag: typically -0, could use -O4 or -fast, -O4 is ok for RTEMS
650 +CFLAGS_OPTIMIZE_V=-O2 -fomit-frame-pointer -ggdb
651 +CXXFLAGS_OPTIMIZE_V=-O2 -ggdb
653 ifeq ($(MRM_IN_ROM),yes)
654 # Build a rommable image - move the .data section after the .text section
655 Index: rtems-4.9.3/c/src/lib/libbsp/m68k/mo376/startup/start_c.c
656 ===================================================================
657 --- rtems-4.9.3.orig/c/src/lib/libbsp/m68k/mo376/startup/start_c.c 2009-11-29 01:23:46.812556872 +0100
658 +++ rtems-4.9.3/c/src/lib/libbsp/m68k/mo376/startup/start_c.c 2009-11-29 01:36:40.432570032 +0100
661 /* Port E and F Data Direction Register */
662 /* see section 9 of the SIM Reference Manual */
663 - *DDRE = (unsigned char) 0xff;
664 - *DDRF = (unsigned char) 0xfd;
665 + *DDRE = (unsigned char) 0x01;
666 + *DDRF = (unsigned char) 0x00;
668 /* Port E and F Pin Assignment Register */
669 /* see section 9 of the SIM Reference Manual */
670 - *PEPAR = (unsigned char) 0;
671 + *PEPAR = (unsigned char) 0xf4;
672 *PFPAR = (unsigned char) 0;
674 /* end of SIM initalization code */