1 From 16f2999ca37ec28c95f469beb095b0d794bab505 Mon Sep 17 00:00:00 2001
2 Message-Id: <16f2999ca37ec28c95f469beb095b0d794bab505.1460800109.git.ppisa@pikron.com>
3 In-Reply-To: <fa0cd7f188055c9ee2daac4f933cfa023e369dea.1460800109.git.ppisa@pikron.com>
4 References: <fa0cd7f188055c9ee2daac4f933cfa023e369dea.1460800109.git.ppisa@pikron.com>
5 From: ppisa <ppisa@pikron.com>
6 Date: Sun, 9 Nov 2008 10:51:34 +0100
7 Subject: [PATCH 3/4] rtems-m9328-pimx1-syncmclk
8 To: rtems-devel@rtems.org
11 c/src/lib/libbsp/arm/csb336/startup/bspstart.c | 2 ++
12 1 file changed, 2 insertions(+)
14 diff --git a/c/src/lib/libbsp/arm/csb336/startup/bspstart.c b/c/src/lib/libbsp/arm/csb336/startup/bspstart.c
15 index 0a134ba..21f452b 100644
16 --- a/c/src/lib/libbsp/arm/csb336/startup/bspstart.c
17 +++ b/c/src/lib/libbsp/arm/csb336/startup/bspstart.c
20 static void bsp_start_default( void )
22 +#ifdef CONFIG_MC9328MX_ASYNCMCLK
25 /* Set the MCU prescaler to divide by 1 */
26 @@ -46,6 +47,7 @@ static void bsp_start_default( void )
28 /* Set the CPU to asynchrous clock mode, so it uses its fastest clock */
29 mmu_set_cpu_async_mode();
30 +#endif /*CONFIG_MC9328MX_ASYNCMCLK*/
32 /* disable interrupts */
33 MC9328MXL_AITC_INTENABLEL = 0;