From baf316809842948954e41be48dcffbee28067d8d Mon Sep 17 00:00:00 2001 From: Rostislav Lisovy Date: Fri, 26 Oct 2012 17:14:48 +0200 Subject: [PATCH] i2c: Halcogen generated source codes --- CommandStoring.dil | 18 +- CommandStoring.hcg | 6 +- include/sys_vim.h | 1 + source/i2c.c | 618 ++++++++++++++++++++++++++++++++++++++++++ source/notification.c | 9 + source/sys_startup.c | 2 +- 6 files changed, 642 insertions(+), 12 deletions(-) create mode 100644 source/i2c.c diff --git a/CommandStoring.dil b/CommandStoring.dil index 724822e..dbccef8 100644 --- a/CommandStoring.dil +++ b/CommandStoring.dil @@ -517,7 +517,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_PRAGMA_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_PRAGMA_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI5_DP_PBISTCHECK_ENA.VALUE=0x00000100 @@ -1179,7 +1179,7 @@ DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.CORE_VFP_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.SAFETY_INIT_VIM1_DP_PBISTCHECK_ENA.VALUE=0x00000200 DRIVER.SYSTEM.VAR.SAFETY_INIT_FMCBUS2_SELFCHECK_ENA.VALUE=1 -DRIVER.SYSTEM.VAR.I2C_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.I2C_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.ECLK_OSCILLATOR_FREQ.VALUE=16.000 DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_TRIM.VALUE=100.00 DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_MAPPING.VALUE=9 @@ -5802,25 +5802,25 @@ DRIVER.DMM.VAR.DMM_PORT_BIT3_PULL.VALUE=0 DRIVER.DMM.VAR.DMM_PORT_BIT0_DIR.VALUE=1 DRIVER.DMM.VAR.DMM_PORT_BIT18_PDR.VALUE=0 DRIVER.DMM.VAR.DMM_PORT_BIT6_DOUT.VALUE=0 -DRIVER.I2C.VAR.I2C_PORT_BIT0_DIR.VALUE=0 +DRIVER.I2C.VAR.I2C_PORT_BIT0_DIR.VALUE=1 DRIVER.I2C.VAR.I2C_STOPBITS.VALUE=2 -DRIVER.I2C.VAR.I2C_PORT_BIT1_DIR.VALUE=0 +DRIVER.I2C.VAR.I2C_PORT_BIT1_DIR.VALUE=1 DRIVER.I2C.VAR.I2C_ICXRDYINTLVL.VALUE=0 DRIVER.I2C.VAR.I2C_BASE_PORT.VALUE=0xFFF7D44C -DRIVER.I2C.VAR.I2C_DATACOUNT.VALUE=8 +DRIVER.I2C.VAR.I2C_DATACOUNT.VALUE=3 DRIVER.I2C.VAR.I2C_ADDRMODE.VALUE=7BIT_AMODE DRIVER.I2C.VAR.I2C_PORT_BIT0_FUN.VALUE=0 DRIVER.I2C.VAR.I2C_PORT_BIT0_PDR.VALUE=0 DRIVER.I2C.VAR.I2C_BC_VALUE.VALUE=0x0003 DRIVER.I2C.VAR.I2C_PORT_BIT1_FUN.VALUE=0 DRIVER.I2C.VAR.I2C_RM_ENA.VALUE=0 -DRIVER.I2C.VAR.I2C_BC.VALUE=2_BIT +DRIVER.I2C.VAR.I2C_BC.VALUE=8_BIT DRIVER.I2C.VAR.I2C_PORT_BIT1_PDR.VALUE=0 DRIVER.I2C.VAR.I2C_TXRX_VALUE.VALUE=0 DRIVER.I2C.VAR.I2C_SCDLVL.VALUE=0 DRIVER.I2C.VAR.I2C_PORT_BIT0_PSL.VALUE=1 DRIVER.I2C.VAR.I2C_STPCND.VALUE=1 -DRIVER.I2C.VAR.I2C_ALINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C_ALINTENA.VALUE=1 DRIVER.I2C.VAR.I2C_PRESCALE.VALUE=9 DRIVER.I2C.VAR.I2C_PORT_BIT1_PSL.VALUE=1 DRIVER.I2C.VAR.I2C_TXRX.VALUE=TRANSMITTER @@ -5838,7 +5838,7 @@ DRIVER.I2C.VAR.I2C_AASLVL.VALUE=0 DRIVER.I2C.VAR.I2C_ICCL.VALUE=35 DRIVER.I2C.VAR.I2C_AAS.VALUE=0 DRIVER.I2C.VAR.I2C_ADDRMODE_VALUE.VALUE=0x0001 -DRIVER.I2C.VAR.I2C_ICRRDYINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C_ICRRDYINTENA.VALUE=1 DRIVER.I2C.VAR.I2C_FDF.VALUE=0 DRIVER.I2C.VAR.I2C_ARDYINTLVL.VALUE=0 DRIVER.I2C.VAR.I2C_PARITYENA.VALUE=0 @@ -5850,7 +5850,7 @@ DRIVER.I2C.VAR.I2C_PORT_BIT1_PULL.VALUE=2 DRIVER.I2C.VAR.I2C_ICRRDYINTLVL.VALUE=0 DRIVER.I2C.VAR.I2C_STACND.VALUE=1 DRIVER.I2C.VAR.I2C_PORT_BIT1_PULDIS.VALUE=0 -DRIVER.I2C.VAR.I2C_ICXRDYINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C_ICXRDYINTENA.VALUE=1 DRIVER.I2C.VAR.I2C_NACKINTLVL.VALUE=0 DRIVER.I2C.VAR.I2C_EVENPARITY.VALUE=0 DRIVER.I2C.VAR.I2C_BAUDRATE.VALUE=100 diff --git a/CommandStoring.hcg b/CommandStoring.hcg index c96883c..d03cc36 100644 --- a/CommandStoring.hcg +++ b/CommandStoring.hcg @@ -251,7 +251,9 @@ i2c.h - + + i2c.c + emac.h @@ -496,7 +498,7 @@ include\i2c.h - + source\i2c.c diff --git a/include/sys_vim.h b/include/sys_vim.h index 719e642..f7f64d7 100644 --- a/include/sys_vim.h +++ b/include/sys_vim.h @@ -59,6 +59,7 @@ extern void spi4HighLevelInterrupt(void); extern void adc2Group1Interrupt(void); extern void spi4LowLevelInterrupt(void); extern void sciHighLevelInterrupt(void); +extern void i2cInterrupt(void); extern void EMACCore0RxIsr(void); extern void EMACCore0TxIsr(void); diff --git a/source/i2c.c b/source/i2c.c new file mode 100644 index 0000000..2a444b8 --- /dev/null +++ b/source/i2c.c @@ -0,0 +1,618 @@ +/** @file i2c.c +* @brief I2C Driver Implementation File +* @date 10.March.2012 +* @version 03.01.00 +* +*/ + +/* (c) Texas Instruments 2009-2012, All rights reserved. */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "i2c.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @struct g_I2CTransfer +* @brief Interrupt mode globals +* +*/ +struct g_i2cTransfer +{ + uint32_t mode; + uint32_t length; + uint8_t *data; +} g_i2cTransfer[2]; + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/** @fn void i2cInit(void) +* @brief Initializes the i2c Driver +* +* This function initializes the i2c module. +*/ +void i2cInit(void) +{ +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + + /** @b intialize @b I2C */ + + /** - i2c out of reset */ + i2cREG1->MDR = (1 << 5); + + /** - set i2c mode */ + i2cREG1->MDR = (0 << 15) /* nack mode */ + | (0 << 14) /* free running */ + | 0 /* start condtion - master mode only */ + | (1 <<11) /* stop condtion */ + | (1 <<10) /* Master/Slave mode */ + | (I2C_TRANSMITTER) /* Transmitter/receiver */ + | (I2C_7BIT_AMODE) /* xpanded address */ + | (0 << 7) /* repeat mode */ + | (0 << 6) /* digital loopback */ + | (0 << 4) /* start byte - master only */ + | (0) /* free data format */ + | I2C_8_BIT; /* bit count */ + + + /** - set i2c extended mode */ + i2cREG1->EMDR = (0 << 25); + + /** - set i2c data count */ + i2cREG1->CNT = 3; + + /** - disable all interrupts */ + i2cREG1->IMR = 0x00U; + + /** - set prescale */ + i2cREG1->PSC = 9; + + /** - set clock rate */ + i2cREG1->CLKH = 35; + i2cREG1->CLKL = 35; + + /** - set i2c pins functional mode */ + i2cREG1->FUN = (0 ); + + /** - set i2c pins default output value */ + i2cREG1->DOUT = (0 << 1) /* sda pin */ + | (0); /* scl pin */ + + /** - set i2c pins output direction */ + i2cREG1->DIR = (1 << 1) /* sda pin */ + | (1); /* scl pin */ + + /** - set i2c pins open drain enable */ + i2cREG1->ODR = (0 << 1) /* sda pin */ + | (0); /* scl pin */ + + /** - set i2c pins pullup/pulldown enable */ + i2cREG1->PD = (0 << 1) /* sda pin */ + | (0); /* scl pin */ + + /** - set i2c pins pullup/pulldown select */ + i2cREG1->PSL = (1 << 1) /* sda pin */ + | (1); /* scl pin */ + + /** - set interrupt enable */ + i2cREG1->IMR = (0 << 6) /* Address as slave interrupt */ + | (0 << 5) /* Stop Condition detect interrupt */ + | (1 << 4) /* Transmit data ready interrupt */ + | (1 << 3) /* Receive data ready interrupt */ + | (0 << 2) /* Register Access ready interrupt */ + | (0 << 1) /* No Acknowledgement interrupt */ + | (1); /* Arbitration Lost interrupt */ + + i2cREG1->MDR |= I2C_RESET_OUT; /* i2c out of reset */ + + /** - inialise global transfer variables */ + g_i2cTransfer[0].mode = 1 << 8; + g_i2cTransfer[0].length = 0; + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + +} + +/** @fn void i2cSetOwnAdd(i2cBASE_t *i2c, uint32_t oadd) +* @brief Set I2C Own Address +* @param[in] oadd - I2C Own address (7-bit or 10 -bit address) +* @param[in] i2c - i2c module base address +* Set the Own address of the I2C module. +*/ +void i2cSetOwnAdd(i2cBASE_t *i2c, uint32_t oadd) +{ + i2cREG1->OAR = oadd; /* set own address */ +} + +/** @fn void i2cSetSlaveAdd(i2cBASE_t *i2c, uint32_t sadd) +* @brief Set Port Direction +* @param[in] sadd - I2C Slave address +* @param[in] i2c - i2c module base address +* Set the Slave address to communicate which is must in Master mode. +*/ +void i2cSetSlaveAdd(i2cBASE_t *i2c, uint32_t sadd) +{ + i2cREG1->SAR = sadd; /* set slave address */ +} + +/** @fn void i2cSetBaudrate(i2cBASE_t *i2c, uint32_t baud) +* @brief Change baudrate at runtime. +* @param[in] i2c - i2c module base address +* @param[in] baud - baudrate in KHz +* +* Change the i2c baudrate at runtime. +*/ +void i2cSetBaudrate(i2cBASE_t *i2c, uint32_t baud) +{ + uint32_t prescale; + uint32_t d; + uint32_t ck; + double vclk = 80.000 * 1000000.0; + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ + prescale = (uint32_t) ((vclk /8000000) - 1); + + if(prescale>=2) + { + d = 5; + } + else + { + d = prescale ? 6 : 7; + } + + ck = ((vclk)/(2*baud*1000*(prescale+1)))-d; + + i2cREG1->PSC = prescale; + i2cREG1->CLKH = ck; + i2cREG1->CLKL = ck; + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + +} + +/** @fn void i2cSetStart(i2cBASE_t *i2c) +* @brief Set i2c start condition +* @param[in] i2c - i2c module base address +* Set i2c to generate a start bit (Only in Master mode) +*/ +void i2cSetStart(i2cBASE_t *i2c) +{ +/* USER CODE BEGIN (7) */ +/* USER CODE END */ + + i2cREG1->MDR |= I2C_START_COND; /* set start condition */ + +/* USER CODE BEGIN (8) */ +/* USER CODE END */ +} + +/** @fn void i2cSetStop(i2cBASE_t *i2c) +* @brief Set i2c stop condition +* @param[in] i2c - i2c module base address +* Set i2c to generate a stop bit (Only in Master mode) +*/ +void i2cSetStop(i2cBASE_t *i2c) +{ +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + + i2cREG1->MDR |= I2C_STOP_COND; /* generate stop condition */ + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ +} + +/** @fn void i2cSetCount(i2cBASE_t *i2c,uint32_t cnt) +* @brief Set i2c data count +* @param[in] i2c - i2c module base address +* @param[in] cnt - data count +* Set i2c count to a transfer value after which the stop condition needs to be generated. +* (Only in Master Mode) +*/ +void i2cSetCount(i2cBASE_t *i2c ,uint32_t cnt) +{ +/* USER CODE BEGIN (11) */ +/* USER CODE END */ + + i2cREG1->CNT = cnt; /* set i2c count */ + +/* USER CODE BEGIN (12) */ +/* USER CODE END */ +} + +/** @fn uint32_t i2cIsTxReady(i2cBASE_t *i2c) +* @brief Check if Tx buffer empty +* @param[in] i2c - i2c module base address +* +* @return The TX ready flag +* +* Checks to see if the Tx buffer ready flag is set, returns +* 0 is flags not set otherwise will return the Tx flag itself. +*/ +uint32_t i2cIsTxReady(i2cBASE_t *i2c) +{ +/* USER CODE BEGIN (13) */ +/* USER CODE END */ + + return i2cREG1->STR & I2C_TX_INT; + +/* USER CODE BEGIN (14) */ +/* USER CODE END */ +} + +/** @fn void i2cSendByte(i2cBASE_t *i2c, uint8_t byte) +* @brief Send Byte +* @param[in] i2c - i2c module base address +* @param[in] byte - byte to transfer +* +* Sends a single byte in polling mode, will wait in the +* routine until the transmit buffer is empty before sending +* the byte. Use i2cIsTxReady to check for Tx buffer empty +* before calling i2cSendByte to avoid waiting. +*/ +void i2cSendByte(i2cBASE_t *i2c, uint8_t byte) +{ +/* USER CODE BEGIN (15) */ +/* USER CODE END */ + + while ((i2cREG1->STR & I2C_TX_INT) == 0) { /* wait */ }; + i2cREG1->DXR = byte; + +/* USER CODE BEGIN (16) */ +/* USER CODE END */ +} + +/** @fn void i2cSend(i2cBASE_t *i2c, uint32_t length, uint8_t *data) +* @brief Send Data +* @param[in] i2c - i2c module base address +* @param[in] length - number of data words to transfer +* @param[in] data - pointer to data to send +* +* Send a block of data pointed to by 'data' and 'length' bytes +* long. If interrupts have been enabled the data is sent using +* interrupt mode, otherwise polling mode is used. In interrupt +* mode transmition of the first byte is started and the routine +* returns imediatly, i2cSend must not be called again until the +* transfer is complete, when the i2cNotification callback will +* be called. In polling mode, i2cSend will not return until +* the transfer is complete. +* +* @note if data word is less than 8 bits, then the data must be left +* aligned in the data byte. +*/ +void i2cSend(i2cBASE_t *i2c, uint32_t length, uint8_t *data) +{ + uint32_t index = i2c == i2cREG1 ? 0 : 1; + +/* USER CODE BEGIN (17) */ +/* USER CODE END */ + + if ((g_i2cTransfer[index].mode & I2C_TX_INT) != 0) + { + /* we are in interrupt mode */ + + g_i2cTransfer[index].length = length; + g_i2cTransfer[index].data = data; + + /* start transmit by sending first byte */ + i2cREG1->DXR = *g_i2cTransfer[index].data++; + i2cREG1->IMR = I2C_TX_INT; + } + else + { + /* send the data */ + while (length-- > 0) + { + while ((i2cREG1->STR & I2C_TX_INT) == 0) { /* wait */ }; + i2cREG1->DXR = *data++; + } + } +/* USER CODE BEGIN (18) */ +/* USER CODE END */ +} + +/** @fn uint32_t i2cIsRxReady(i2cBASE_t *i2c) +* @brief Check if Rx buffer full +* @param[in] i2c - i2c module base address +* +* @return The Rx ready flag +* +* Checks to see if the Rx buffer full flag is set, returns +* 0 is flags not set otherwise will return the Rx flag itself. +*/ +uint32_t i2cIsRxReady(i2cBASE_t *i2c) +{ +/* USER CODE BEGIN (19) */ +/* USER CODE END */ + + return i2cREG1->STR & I2C_RX_INT; + +/* USER CODE BEGIN (20) */ +/* USER CODE END */ +} + + +/** @fn uint32_t i2cRxError(i2cBASE_t *i2c) +* @brief Return Rx Error flags +* @param[in] i2c - i2c module base address +* +* @return The Rx error flags +* +* Returns the Rx framing, overun and parity errors flags, +* also clears the error flags before returning. +*/ +uint32_t i2cRxError(i2cBASE_t *i2c) +{ + uint32_t status = i2cREG1->STR & (I2C_AL_INT | I2C_NACK_INT); + +/* USER CODE BEGIN (21) */ +/* USER CODE END */ + + i2cREG1->STR = I2C_AL_INT | I2C_NACK_INT; + +/* USER CODE BEGIN (22) */ +/* USER CODE END */ + + return status; + +} + +/** @fn void i2cClearSCD(i2cBASE_t *i2c) +* @brief Clears the Stop condition detect flags. +* @param[in] i2c - i2c module base address +* +* This sunction is called to clear the Stop condition detect(SCD) flag +*/ +void i2cClearSCD(i2cBASE_t *i2c) +{ +/* USER CODE BEGIN (23) */ +/* USER CODE END */ + + i2cREG1->STR = I2C_SCD_INT; + +/* USER CODE BEGIN (24) */ +/* USER CODE END */ +} + +/** @fn uint32_t i2cReceiveByte(i2cBASE_t *i2c) +* @brief Receive Byte +* @param[in] i2c - i2c module base address +* +* @return Received byte +* +* Recieves a single byte in polling mode. If there is +* not a byte in the receive buffer the routine will wait +* until one is received. Use i2cIsRxReady to check to +* see if the buffer is full to avoid waiting. +*/ +uint32_t i2cReceiveByte(i2cBASE_t *i2c) +{ + while ((i2cREG1->STR & I2C_RX_INT) == 0) { /* wait */ }; + +/* USER CODE BEGIN (25) */ +/* USER CODE END */ + + return i2cREG1->DRR; +} + +/** @fn void i2cReceive(i2cBASE_t *i2c, uint32_t length, uint8_t *data) +* @brief Receive Data +* @param[in] i2c - i2c module base address +* @param[in] length - number of data words to transfer +* @param[in] data - pointer to data buffer +* +* Receive a block of 'length' bytes long and place it into the +* data buffer pointed to by 'data'. If interrupts have been +* enabled the data is received using interrupt mode, otherwise +* polling mode is used. In interrupt mode receive is setup and +* the routine returns imediatly, i2cReceive must not be called +* again until the transfer is complete, when the i2cNotification +* callback will be called. In polling mode, i2cReceive will not +* return until the transfer is complete. +*/ +void i2cReceive(i2cBASE_t *i2c, uint32_t length, uint8_t *data) +{ + +/* USER CODE BEGIN (26) */ +/* USER CODE END */ + if ((i2cREG1->IMR & I2C_RX_INT) != 0) + { + /* we are in interrupt mode */ + uint32_t index = i2c == i2cREG1 ? 0 : 1; + + /* clear error flags */ + i2cREG1->STR = I2C_AL_INT | I2C_NACK_INT; + + g_i2cTransfer[index].length = length; + g_i2cTransfer[index].data = data; + } + else + { + while (length-- > 0) + { + while ((i2cREG1->STR & I2C_RX_INT) == 0) { /* wait */ }; + *data++ = i2cREG1->DRR; + } + } + +/* USER CODE BEGIN (27) */ +/* USER CODE END */ +} + +/** @fn void i2cEnableLoopback(i2cBASE_t *i2c) +* @brief Enable Loopback mode for self test +* @param[in] i2c - i2c module base address +* +* This function enables the Loopback mode for self test. +*/ +void i2cEnableLoopback(i2cBASE_t *i2c) +{ +/* USER CODE BEGIN (28) */ +/* USER CODE END */ + + /* enable digital loopback */ + i2cREG1->MDR |= (1 << 6); + +/* USER CODE BEGIN (29) */ +/* USER CODE END */ +} + +/** @fn void i2cDisableLoopback(i2cBASE_t *i2c) +* @brief Enable Loopback mode for self test +* @param[in] i2c - i2c module base address +* +* This function disable the Loopback mode. +*/ +void i2cDisableLoopback(i2cBASE_t *i2c) +{ +/* USER CODE BEGIN (30) */ +/* USER CODE END */ + + /* Disable Loopback Mode */ + i2cREG1->MDR &= 0xFFFFFFBF; + +/* USER CODE BEGIN (31) */ +/* USER CODE END */ +} + +/** @fn i2cEnableNotification(i2cBASE_t *i2c, uint32_t flags) +* @brief Enable interrupts +* @param[in] i2c - i2c module base address +* @param[in] flags - Interrupts to be enabled, can be ored value of: +* i2c_FE_INT - framming error, +* i2c_OE_INT - overrun error, +* i2c_PE_INT - parity error, +* i2c_RX_INT - receive buffer ready, +* i2c_TX_INT - transmit buffer ready, +* i2c_WAKE_INT - wakeup, +* i2c_BREAK_INT - break detect +*/ +void i2cEnableNotification(i2cBASE_t *i2c, uint32_t flags) +{ + uint32_t index = i2c == i2cREG1 ? 0 : 1; + +/* USER CODE BEGIN (32) */ +/* USER CODE END */ + + g_i2cTransfer[index].mode |= (flags & I2C_TX_INT); + i2cREG1->IMR = (flags & ~I2C_TX_INT); +} + +/** @fn i2cDisableNotification(i2cBASE_t *i2c, uint32_t flags) +* @brief Disable interrupts +* @param[in] i2c - i2c module base address +* @param[in] flags - Interrupts to be disabled, can be ored value of: +* i2c_FE_INT - framming error, +* i2c_OE_INT - overrun error, +* i2c_PE_INT - parity error, +* i2c_RX_INT - receive buffer ready, +* i2c_TX_INT - transmit buffer ready, +* i2c_WAKE_INT - wakeup, +* i2c_BREAK_INT - break detect +*/ +void i2cDisableNotification(i2cBASE_t *i2c, uint32_t flags) +{ + uint32_t index = i2c == i2cREG1 ? 0 : 1; + +/* USER CODE BEGIN (33) */ +/* USER CODE END */ + + g_i2cTransfer[index].mode &= ~(flags & I2C_TX_INT); + i2cREG1->IMR = (flags & ~I2C_TX_INT); +} + +/** @fn void i2cInterrupt(void) +* @brief Interrupt for I2C +*/ +#pragma INTERRUPT(i2cInterrupt, IRQ) + +void i2cInterrupt(void) +{ + uint32_t vec = (i2cREG1->IVR & 0x00000007); + +/* USER CODE BEGIN (34) */ +/* USER CODE END */ + + switch (vec) + { + case 1: +/* USER CODE BEGIN (35) */ +/* USER CODE END */ + i2cNotification(i2cREG1, I2C_AL_INT); + break; + case 2: +/* USER CODE BEGIN (36) */ +/* USER CODE END */ + i2cNotification(i2cREG1, I2C_NACK_INT); + break; + case 3: +/* USER CODE BEGIN (37) */ +/* USER CODE END */ + i2cNotification(i2cREG1, I2C_ARDY_INT); + break; + case 4: +/* USER CODE BEGIN (38) */ +/* USER CODE END */ + /* receive */ + { uint32_t byte = i2cREG1->DRR; + + if (g_i2cTransfer[0].length > 0) + { + *g_i2cTransfer[0].data++ = byte; + g_i2cTransfer[0].length--; + if (g_i2cTransfer[0].length == 0) + { + i2cNotification(i2cREG1, I2C_RX_INT); + } + } + } + break; + case 5: +/* USER CODE BEGIN (39) */ +/* USER CODE END */ + /* transmit */ + if (--g_i2cTransfer[0].length > 0) + { + i2cREG1->DXR = *g_i2cTransfer[0].data++; + } + else + { + i2cREG1->STR = I2C_TX_INT; + i2cNotification(i2cREG1, I2C_TX_INT); + } + break; + + + case 6: +/* USER CODE BEGIN (40) */ +/* USER CODE END */ + /* transmit */ + i2cNotification(i2cREG1, I2C_SCD_INT); + break; + + case 7: +/* USER CODE BEGIN (41) */ +/* USER CODE END */ + i2cNotification(i2cREG1, I2C_AAS_INT); + break; + + default: +/* USER CODE BEGIN (42) */ +/* USER CODE END */ + /* phantom interrupt, clear flags and return */ + i2cREG1->STR = 0x000007FF; + break; + } +/* USER CODE BEGIN (43) */ +/* USER CODE END */ +} + + diff --git a/source/notification.c b/source/notification.c index 5f23ae7..222d6ae 100644 --- a/source/notification.c +++ b/source/notification.c @@ -20,6 +20,7 @@ #include "mibspi.h" #include "sci.h" #include "het.h" +#include "i2c.h" /* USER CODE BEGIN (0) */ #include "FreeRTOS.h" #include "os_semphr.h" @@ -166,6 +167,14 @@ void gioNotification(int bit) /* USER CODE BEGIN (20) */ /* USER CODE END */ +void i2cNotification(i2cBASE_t *i2c, uint32_t flags) +{ +/* enter user code and remove the while loop... */ + while(1); +/* USER CODE BEGIN (21) */ +/* USER CODE END */ + +} void linNotification(linBASE_t *lin, uint32_t flags) { /* USER CODE BEGIN (23) */ diff --git a/source/sys_startup.c b/source/sys_startup.c index a490237..c620e82 100644 --- a/source/sys_startup.c +++ b/source/sys_startup.c @@ -152,7 +152,7 @@ static const t_isrFuncPTR s_vim_init[] = &phantomInterrupt, &sciHighLevelInterrupt, &phantomInterrupt, // 65 - &phantomInterrupt, + &i2cInterrupt, &phantomInterrupt, &phantomInterrupt, &phantomInterrupt, -- 2.39.2