Update library

[pes-rpp/rpp-test-sw.git] / rpp-test-sw / commands / cmd_vbat.c

diff --git a/rpp-test-sw/commands/cmd_vbat.c b/rpp-test-sw/commands/cmd_vbat.c
index e575a043e1665942cc99e9060b175be74e4285ab..98dfa8b9cb1c9ba8b026e3ca8269fe6d6204a3eb 100644 (file)
--- a/rpp-test-sw/commands/cmd_vbat.c
+++ b/rpp-test-sw/commands/cmd_vbat.c
@@ -24,7 +24,7 @@
 #ifndef DOCGEN
 
 #include "rpp/rpp.h"
-#include "hal/hal.h"
+#include "drv/digital_io_def.h"
 
 #define VBATPWM_PERIOD 400
 
@@ -51,25 +51,35 @@ int vbat1_pwm()
        volatile uint8_t val = 1;
        int i, j;
        int pulse_cnt = 100;
-       uint32_t desc;
 
-       desc = PIN_DSC_VBAT1EN;
-       hal_gpio_pin_set_value(desc, 0);
-       hal_gpio_pin_direction_output(desc, 0);
+       if (rpp_gio_set_output(DIO_PIN_NAME_VBAT1EN, 0) == FAILURE) {
+               return -CMDERR_BADDIO;
+       }
+
        vTaskDelay(10/portTICK_RATE_MS+2);
        _disable_IRQ();
        while ((pwm = *(ppwm++)))
                for (i = 0; i < pulse_cnt; i++) {
-                       hal_gpio_pin_set_value(desc, 1);
+                       if (rpp_gio_set_val(DIO_PIN_NAME_VBAT1EN, 1) == FAILURE) {
+                               return -CMDERR_BADDIO;
+                       }
                        for (j = 0; j < pwm; j++)
                                ;
-                       hal_gpio_pin_set_value(desc, 0);
+                       if (rpp_gio_set_val(DIO_PIN_NAME_VBAT1EN, 0) == FAILURE) {
+                               return -CMDERR_BADDIO;
+                       }
                        for (j = 0; j < VBATPWM_PERIOD - pwm; j++)
                                ;
                }
-       hal_gpio_pin_set_value(desc, 1);
+       if (rpp_gio_set_val(DIO_PIN_NAME_VBAT1EN, 1) == FAILURE) {
+               return -CMDERR_BADDIO;
+       }
        _enable_IRQ();
-       return hal_gpio_pin_get_value(desc);
+       int32_t ret = rpp_gio_get_val(DIO_PIN_NAME_VBAT1EN);
+       if (ret == FAILURE) {
+               return -CMDERR_BADDIO;
+       }
+       return ret;
 }
 
 /**
@@ -84,8 +94,13 @@ int cmd_do_power_on(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
 {
        int ret = 0;
 
-       hal_gpio_pin_set_value(PIN_DSC_VBATEN, 1);
-       ret = hal_gpio_pin_get_value(PIN_DSC_VBATEN);
+       if (rpp_gio_set_val(DIO_PIN_NAME_VBATEN, 1) == FAILURE) {
+               return -CMDERR_BADDIO;
+       }
+       ret = rpp_gio_get_val(DIO_PIN_NAME_VBATEN);
+       if (ret == FAILURE) {
+               return -CMDERR_BADDIO;
+       }
        ret |= vbat1_pwm() << 1;
        return cmd_opchar_replong(cmd_io, param, ret, 0, 0);
 }
@@ -100,12 +115,24 @@ int cmd_do_power_on(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
  */
 int cmd_do_power_off(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
 {
-       int ret = 0;
+       int ret, ret2 = 0;
+
+       if (rpp_gio_set_val(DIO_PIN_NAME_VBAT1EN, 0) == FAILURE) {
+               return -CMDERR_BADDIO;
+       }
+       ret = rpp_gio_get_val(DIO_PIN_NAME_VBAT1EN);
+       if (ret == FAILURE) {
+               return -CMDERR_BADDIO;
+       }
+       if (rpp_gio_set_val(DIO_PIN_NAME_VBATEN, 0) == FAILURE) {
+               return -CMDERR_BADDIO;
+       }
+       ret = rpp_gio_get_val(DIO_PIN_NAME_VBATEN);
+       if (ret == FAILURE) {
+               return -CMDERR_BADDIO;
+       }
 
-       hal_gpio_pin_set_value(PIN_DSC_VBAT1EN, 0);
-       ret = hal_gpio_pin_get_value(PIN_DSC_VBAT1EN);
-       hal_gpio_pin_set_value(PIN_DSC_VBATEN, 0);
-       ret |= hal_gpio_pin_get_value(PIN_DSC_VBATEN) << 1;
+       ret |= ret2 << 1;
        return cmd_opchar_replong(cmd_io, param, ret, 0, 0);
 }