1 ;-------------------------------------------------------------------------------
4 ; (c) Texas Instruments 2009-2012, All rights reserved.
10 ;-------------------------------------------------------------------------------
11 ; Initialize CPU Registers
13 .def _coreInitRegisters_
20 ; After reset, the CPU is in the Supervisor mode (M = 10011)
37 ; Switch to FIQ mode (M = 10001)
47 ; Switch to IRQ mode (M = 10010)
52 ; Switch to Abort mode (M = 10111)
57 ; Switch to Undefined Instruction Mode (M = 11011)
62 ; Switch back to Supervisor Mode (M = 10011)
66 mrc p15, #0x00, r2, c1, c0, #0x02
68 mcr p15, #0x00, r2, c1, c0, #0x02
101 ;-------------------------------------------------------------------------------
102 ; Initialize Stack Pointers
104 .def _coreInitStackPointer_
107 _coreInitStackPointer_
123 userSp .word 0x08000000+0x00001000
124 svcSp .word 0x08000000+0x00001000+0x00000100
125 fiqSp .word 0x08000000+0x00001000+0x00000100+0x00000100
126 irqSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100
127 abortSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100
128 undefSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100+0x00000100
132 ;-------------------------------------------------------------------------------
145 ;-------------------------------------------------------------------------------
146 ; Take CPU to IDLE state
162 ;-------------------------------------------------------------------------------
170 mrc p15, #0x00, r0, c1, c0, #0x02
171 orr r0, r0, #0xF00000
172 mcr p15, #0x00, r0, c1, c0, #0x02
179 ;-------------------------------------------------------------------------------
180 ; Enable Event Bus Export
182 .def _coreEnableEventBusExport_
185 _coreEnableEventBusExport_
188 mrc p15, #0x00, r0, c9, c12, #0x00
190 mcr p15, #0x00, r0, c9, c12, #0x00
197 ;-------------------------------------------------------------------------------
198 ; Disable Event Bus Export
200 .def _coreDisableEventBusExport_
203 _coreDisableEventBusExport_
206 mrc p15, #0x00, r0, c9, c12, #0x00
208 mcr p15, #0x00, r0, c9, c12, #0x00
215 ;-------------------------------------------------------------------------------
216 ; Enable RAM ECC Support
218 .def _coreEnableRamEcc_
224 mrc p15, #0x00, r0, c1, c0, #0x01
225 orr r0, r0, #0x0C000000
226 mcr p15, #0x00, r0, c1, c0, #0x01
233 ;-------------------------------------------------------------------------------
234 ; Disable RAM ECC Support
236 .def _coreDisableRamEcc_
242 mrc p15, #0x00, r0, c1, c0, #0x01
243 bic r0, r0, #0x0C000000
244 mcr p15, #0x00, r0, c1, c0, #0x01
251 ;-------------------------------------------------------------------------------
252 ; Enable Flash ECC Support
254 .def _coreEnableFlashEcc_
260 mrc p15, #0x00, r0, c1, c0, #0x01
261 orr r0, r0, #0x02000000
263 mcr p15, #0x00, r0, c1, c0, #0x01
270 ;-------------------------------------------------------------------------------
271 ; Disable Flash ECC Support
273 .def _coreDisableFlashEcc_
276 _coreDisableFlashEcc_
279 mrc p15, #0x00, r0, c1, c0, #0x01
280 bic r0, r0, #0x02000000
281 mcr p15, #0x00, r0, c1, c0, #0x01
288 ;-------------------------------------------------------------------------------
289 ; Enable Offset via Vic controller
291 .def _coreEnableIrqVicOffset_
294 _coreEnableIrqVicOffset_
297 mrc p15, #0, r0, c1, c0, #0
298 orr r0, r0, #0x01000000
299 mcr p15, #0, r0, c1, c0, #0
306 ;-------------------------------------------------------------------------------
307 ; Get data fault status register
309 .def _coreGetDataFault_
314 mrc p15, #0, r0, c5, c0, #0
320 ;-------------------------------------------------------------------------------
321 ; Clear data fault status register
323 .def _coreClearDataFault_
330 mcr p15, #0, r0, c5, c0, #0
337 ;-------------------------------------------------------------------------------
338 ; Get instruction fault status register
340 .def _coreGetInstructionFault_
343 _coreGetInstructionFault_
345 mrc p15, #0, r0, c5, c0, #1
351 ;-------------------------------------------------------------------------------
352 ; Clear instruction fault status register
354 .def _coreClearInstructionFault_
357 _coreClearInstructionFault_
361 mcr p15, #0, r0, c5, c0, #1
368 ;-------------------------------------------------------------------------------
369 ; Get data fault address register
371 .def _coreGetDataFaultAddress_
374 _coreGetDataFaultAddress_
376 mrc p15, #0, r0, c6, c0, #0
382 ;-------------------------------------------------------------------------------
383 ; Clear data fault address register
385 .def _coreClearDataFaultAddress_
388 _coreClearDataFaultAddress_
392 mcr p15, #0, r0, c6, c0, #0
399 ;-------------------------------------------------------------------------------
400 ; Get instruction fault address register
402 .def _coreGetInstructionFaultAddress_
405 _coreGetInstructionFaultAddress_
407 mrc p15, #0, r0, c6, c0, #2
413 ;-------------------------------------------------------------------------------
414 ; Clear instruction fault address register
416 .def _coreClearInstructionFaultAddress_
419 _coreClearInstructionFaultAddress_
423 mcr p15, #0, r0, c6, c0, #2
430 ;-------------------------------------------------------------------------------
431 ; Get auxiliary data fault status register
433 .def _coreGetAuxiliaryDataFault_
436 _coreGetAuxiliaryDataFault_
438 mrc p15, #0, r0, c5, c1, #0
444 ;-------------------------------------------------------------------------------
445 ; Clear auxiliary data fault status register
447 .def _coreClearAuxiliaryDataFault_
450 _coreClearAuxiliaryDataFault_
454 mcr p15, #0, r0, c5, c1, #0
461 ;-------------------------------------------------------------------------------
462 ; Get auxiliary instruction fault status register
464 .def _coreGetAuxiliaryInstructionFault_
467 _coreGetAuxiliaryInstructionFault_
469 mrc p15, #0, r0, c5, c1, #1
474 ;-------------------------------------------------------------------------------
475 ; Clear auxiliary instruction fault status register
477 .def _coreClearAuxiliaryInstructionFault_
480 _coreClearAuxiliaryInstructionFault_
484 mrc p15, #0, r0, c5, c1, #1
490 ;-------------------------------------------------------------------------------
491 ; Disable interrupts - R4 IRQ & FIQ
493 .def _disable_interrupt_
503 ;-------------------------------------------------------------------------------
504 ; Disable FIQ interrupt
506 .def _disable_FIQ_interrupt_
509 _disable_FIQ_interrupt_
516 ;-------------------------------------------------------------------------------
517 ; Disable FIQ interrupt
519 .def _disable_IRQ_interrupt_
522 _disable_IRQ_interrupt_
529 ;-------------------------------------------------------------------------------
530 ; Enable interrupts - R4 IRQ & FIQ
532 .def _enable_interrupt_
543 ;-------------------------------------------------------------------------------
544 ; Clear ESM CCM errorss
546 .def _esmCcmErrorsClear_
552 ldr r0, ESMSR1_REG ; load the ESMSR1 status register address
553 ldr r2, ESMSR1_ERR_CLR
554 str r2, [r0] ; clear the ESMSR1 register
556 ldr r0, ESMSR2_REG ; load the ESMSR2 status register address
557 ldr r2, ESMSR2_ERR_CLR
558 str r2, [r0] ; clear the ESMSR2 register
560 ldr r0, ESMSSR2_REG ; load the ESMSSR2 status register address
561 ldr r2, ESMSSR2_ERR_CLR
562 str r2, [r0] ; clear the ESMSSR2 register
564 ldr r0, ESMKEY_REG ; load the ESMKEY register address
565 mov r2, #0x5 ; load R2 with 0x5
566 str r2, [r0] ; clear the ESMKEY register
568 ldr r0, VIM_INTREQ ; load the INTREQ register address
570 str r2, [r0] ; clear the INTREQ register
571 ldr r0, CCMR4_STAT_REG ; load the CCMR4 status register address
572 ldr r2, CCMR4_ERR_CLR
573 str r2, [r0] ; clear the CCMR4 status register
577 ESMSR1_REG .word 0xFFFFF518
578 ESMSR2_REG .word 0xFFFFF51C
579 ESMSR3_REG .word 0xFFFFF520
580 ESMKEY_REG .word 0xFFFFF538
581 ESMSSR2_REG .word 0xFFFFF53C
582 CCMR4_STAT_REG .word 0xFFFFF600
583 ERR_CLR_WRD .word 0xFFFFFFFF
584 CCMR4_ERR_CLR .word 0x00010000
585 ESMSR1_ERR_CLR .word 0x80000000
586 ESMSR2_ERR_CLR .word 0x00000004
587 ESMSSR2_ERR_CLR .word 0x00000004
588 VIM_INT_CLR .word 0x00000001
589 VIM_INTREQ .word 0xFFFFFE20
594 ;-------------------------------------------------------------------------------
595 ; C++ construct table pointers
597 .def __TI_PINIT_Base, __TI_PINIT_Limit
598 .weak SHT$$INIT_ARRAY$$Base, SHT$$INIT_ARRAY$$Limit
600 __TI_PINIT_Base .long SHT$$INIT_ARRAY$$Base
601 __TI_PINIT_Limit .long SHT$$INIT_ARRAY$$Limit
605 ;-------------------------------------------------------------------------------