2 * @brief emif Driver Implementation File
3 * @date 15.January.2012
8 /* (c) Texas Instruments 2009-2012, All rights reserved. */
11 #include "sys/system.h"
12 #include "sys/ti_drv_emif.h"
14 /** @fn void emif_SDRAMInit()
15 * @brief Initializes the emif Driver for SDRAM
17 * This function initializes the emif driver for SDRAM (SDRAM initialization function).
27 * configure for SDRAM 64MB IS45S16320
29 * 4 banks, 1024 rows and 8192 columns
30 * 2 bits , 10 bits and 13 bits
34 * self refresh exit time 67 ns
37 saveif = _disable_IRQ();
40 * From UM 4.3.3 Control of Special Multiplexed Options
41 * Any application that requires the EMIF functionality
42 * must set GPREG1[31]. This allows these 8 EMIF module
43 * outputs to be driven on to the assigned balls.
46 systemREG1->GPREG1 |= 0x80000000;
48 emifREG->SDTIMR = ((9-1) << 27)| /* TRF_C REFR to REFR*/
49 ((3-1) << 24)| /* T_RP PRE to ACTIV or REFR */
51 ((3-1) << 20)| /* T_RCD ACTIV to RD/WR */
53 ((2-1) << 16)| /* T_WR WRITE to PRE */
54 ((6-1) << 12)| /* T_RAS ACTIV to PRE */
55 ((9-1) << 8)| /* T_RC ACTIV to ACTIV */
57 ((2-1) << 4)| /* T_RRD ACTIV to ACTIV other bank */
60 /* configure refresh rate*/
61 emifREG->SDSRETR = (5+3-1);
63 /* 80e6 * 16e-3 / 8192 => less or equal to 156 */
66 /** -general clearing of register
67 * -for NM for setting 16 bit data bus
69 * -BIT11_9CLOCK to allow the cl field to be written
70 * -selecting the banks
71 * -setting the pagesize
73 emifREG->SDCR = (0 << 31)| /* SR self refresh mode */
74 (0 << 30)| /* PD power down */
75 (0 << 29)| /* PDWR refresh in PD */
76 (1 << 14)| /* NM narrow mode */
77 (3 << 9)| /* CAS latency */
78 (1 << 8)| /* CAS latency lock */
79 (2 << 4)| /* IBANK .. 4 banks */
80 (2 << 0); /* PAGESIZE .. 10 bit / 1024ele */
81 /* wait for a read to happen*/
82 buffer = *(volatile uint32_t *)PTR;
86 _restore_interrupts(saveif);