From ff699be13840a9e037a35e82b986315231ecc76a Mon Sep 17 00:00:00 2001 From: Michal Horn Date: Thu, 27 Aug 2015 17:43:04 +0200 Subject: [PATCH] Add target specific pinmux for TMS570_HYDCTR --- rpp/include/sys/_tms570_hydctr/sys_pinmux.h | 4 + rpp/src/sys/_tms570_hydctr/.gitattributes | 1 + rpp/src/sys/_tms570_hydctr/sys_pinmux.c | 154 ++++++++++++++++++++ 3 files changed, 159 insertions(+) create mode 100644 rpp/src/sys/_tms570_hydctr/sys_pinmux.c diff --git a/rpp/include/sys/_tms570_hydctr/sys_pinmux.h b/rpp/include/sys/_tms570_hydctr/sys_pinmux.h index 55cf7c7..ec9159d 100644 --- a/rpp/include/sys/_tms570_hydctr/sys_pinmux.h +++ b/rpp/include/sys/_tms570_hydctr/sys_pinmux.h @@ -698,6 +698,10 @@ typedef volatile struct pinMuxBase uint32_t PINMUX28; /**< 0xEB80 Pin Mux 28 register*/ uint32_t PINMUX29; /**< 0xEB84 Pin Mux 29 register*/ uint32_t PINMUX30; /**< 0xEB88 Pin Mux 30 register*/ + uint32_t PINMUX31; /**< 0xEB88 Pin Mux 31 register*/ + uint32_t PINMUX32; /**< 0xEB88 Pin Mux 32 register*/ + uint32_t PINMUX33; /**< 0xEB88 Pin Mux 33 register*/ + uint32_t PINMUX34; /**< 0xEB88 Pin Mux 34 register*/ }pinMuxBASE_t; diff --git a/rpp/src/sys/_tms570_hydctr/.gitattributes b/rpp/src/sys/_tms570_hydctr/.gitattributes index 4a3995b..e309cd8 100644 --- a/rpp/src/sys/_tms570_hydctr/.gitattributes +++ b/rpp/src/sys/_tms570_hydctr/.gitattributes @@ -1,3 +1,4 @@ /notification.c eaton +/sys_pinmux.c eaton /sys_startup.c eaton /ti_drv_adc.c eaton diff --git a/rpp/src/sys/_tms570_hydctr/sys_pinmux.c b/rpp/src/sys/_tms570_hydctr/sys_pinmux.c new file mode 100644 index 0000000..64e306f --- /dev/null +++ b/rpp/src/sys/_tms570_hydctr/sys_pinmux.c @@ -0,0 +1,154 @@ +/** @file pinmux.c +* @brief PINMUX Driver Implementation File +* @date 15.Mar.2012 +* @version 03.01.00 +* +*/ + +/* (c) Texas Instruments 2009-2012, All rights reserved. */ + +/* Include Files */ + +#include "sys/_tms570_hydctr/sys_pinmux.h" + +#define PINMUX_SET(REG, BALLID, MUX) \ + pinMuxReg->PINMUX##REG = (pinMuxReg->PINMUX##REG & PINMUX_BALL_##BALLID##_MASK) | (PINMUX_BALL_##BALLID##_##MUX) + +#define PINMUX_GATE_EMIF_CLK_ENABLE \ + pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_GATE_EMIF_CLK_MASK) | PINMUX_GATE_EMIF_CLK + +#define PINMUX_GIOB_DISABLE_HET2_ENABLE(state) \ + (pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_GIOB_DISABLE_HET2_MASK) | (PINMUX_GIOB_DISABLE_HET2_##state)) + +#define PINMUX_ALT_ADC_TRIGGER_SELECT(num) \ + pinMuxReg->PINMUX30 = (pinMuxReg->PINMUX30 & PINMUX_ALT_ADC_TRIGGER_MASK) | (PINMUX_ALT_ADC_TRIGGER_##num) + +#define PINMUX_ETHERNET_SELECT(interface) \ + pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_ETHERNET_MASK) | (PINMUX_ETHERNET_##interface) + +void muxInit(void){ + + /* Enable Pin Muxing */ + kickerReg->KICKER0 = 0x83E70B13; + kickerReg->KICKER1 = 0x95A4F1E0; + + pinMuxReg->PINMUX0 = PINMUX_BALL_C3_I2C_SCL | PINMUX_BALL_B2_I2C_SDA; + + pinMuxReg->PINMUX1 = PINMUX_BALL_E3_MIBSPI3NCS_4; + + pinMuxReg->PINMUX2 = PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_E1_GIOA_3 | (1 << 26) /* EPWM1A */; + + pinMuxReg->PINMUX3 = (1 << 19) /* EPWM1B */; + + pinMuxReg->PINMUX4 = (1 << 2) /* EPWM2A */ | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_HET1_03; + + pinMuxReg->PINMUX5 = (1 << 2) /* EPWM2B */ | (1 << 10) /* EPWM3A */ | (1 << 19) /* EPWM3B */; + + pinMuxReg->PINMUX6 = (1 << 4) /* EPWM7B */ | PINMUX_BALL_P5_EMIF_DATA_11 | (1 << 20) /* EPWM7A */; + + pinMuxReg->PINMUX7 = (1 << 18) /* EPWM5A */ | PINMUX_BALL_V5_MIBSPI3NCS_1; + + pinMuxReg->PINMUX8 = PINMUX_BALL_G3_MIBSPI1NCS_2 | (1 << 18) /* ECAP1 */ | (1 << 2) /* EPWM5B */; + + pinMuxReg->PINMUX9 = PINMUX_BALL_J3_MIBSPI1NCS_3 | PINMUX_BALL_W9_MIBSPI3NCS_5 | PINMUX_BALL_V10_MIBSPI3NCS_0; + + pinMuxReg->PINMUX10 = PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_N17_EMIF_nCS_0; + + pinMuxReg->PINMUX11 = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_P1_HET1_24; + + pinMuxReg->PINMUX12 = PINMUX_BALL_A14_HET1_26 | (0x1 << 20) /* ECAP4 */ | (0x1 << 29) /* ECAP5 */; + + pinMuxReg->PINMUX13 = PINMUX_BALL_J18_MIBSPI5SOMI_0 | PINMUX_BALL_J19_MIBSPI5SIMO_0 | PINMUX_BALL_H19_MIBSPI5CLK | (0x1 << 28) /* ECAP6 */; + + pinMuxReg->PINMUX14 = PINMUX_BALL_E18_HET1_08 | PINMUX_BALL_K19_HET1_28 | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1; + + pinMuxReg->PINMUX17 = PINMUX_BALL_D19_HET1_10 | PINMUX_BALL_B4_HET1_12; + + pinMuxReg->PINMUX19 = PINMUX_BALL_B11_HET1_30; + + /* pin mutexed with N2HET1[17], which can (and by this implementation is) also be enabled on another ball + * through register PINMMR24[16]. + * + * On this ball there is a Sensor_Supply_1_En connected. To be able to enable the sensor, the HET pin has + * to be enabled on this ball and disabled on the other. But LED, connected to the other ball will not work. + */ + pinMuxReg->PINMUX20 = PINMUX_BALL_F3_MIBSPI1NCS_1; + + pinMuxReg->PINMUX21 = PINMUX_BALL_D5_EMIF_ADDR_1; + + pinMuxReg->PINMUX22 = PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6 | (0x1 << 24) /* EMIF_ADDR_8 */; + + pinMuxReg->PINMUX23 = ((~(pinMuxReg->PINMUX5 >> 1U) & 0x00000001U ) << 8U) | ((~(pinMuxReg->PINMUX5 >> 9U) & 0x00000001U ) << 16U) | ((~(pinMuxReg->PINMUX5 >> 17U) & 0x00000001U ) << 24U) | PINMUX_BALL_C6_EMIF_ADDR_8; + + pinMuxReg->PINMUX24 = ((~(pinMuxReg->PINMUX4 >> 17U) & 0x00000001U ) << 0U) | ((~(pinMuxReg->PINMUX4 >> 25U) & 0x00000001U ) << 8U) | PINMUX_BALL_A13_HET1_17 | PINMUX_BALL_B13_HET1_19; + + pinMuxReg->PINMUX25 = PINMUX_BALL_H4_HET1_21 | PINMUX_BALL_J4_HET1_23 | PINMUX_BALL_M3_HET1_25 | (1 << 24) /* N2HET1[27] */; + + pinMuxReg->PINMUX26 = PINMUX_BALL_A3_HET1_29 | PINMUX_BALL_J17_HET1_31; + + pinMuxReg->PINMUX27 = (1 << 2) /* EPWM4A */; + + pinMuxReg->PINMUX29 = PINMUX_BALL_D3_SPI2NENA | (1 << 16) /* GIOB[2] */; + + pinMuxReg->PINMUX33 = (1 << 1) /* EPWM4B */ | (1 << 8) /* MIBSPI3SOMI[0] */ | (1 << 16) /* MIBSPI3SIMO[0] */ | (1 << 24) /* MIBSPI3CLK */; + + pinMuxReg->PINMUX34 = (1 << 0) /* N2HET1[16] */ | (1 << 9) /* EPWM6A */ | (1 << 17) /* EPWM6B */; + + PINMUX_GATE_EMIF_CLK_ENABLE; + PINMUX_GIOB_DISABLE_HET2_ENABLE(OFF); + PINMUX_ALT_ADC_TRIGGER_SELECT(1); + PINMUX_ETHERNET_SELECT(RMII); + + /* Disable Pin Muxing */ + kickerReg->KICKER0 = 0x00000000U; + kickerReg->KICKER1 = 0x00000000U; + + /* Bit 31 of register GPREG1 is used to gate off the + EMIF module outputs */ + systemREG1->GPREG1 |= 0x80000; +} + +/* + * This function explicitly enable/disable HET2 inputs for IRC module + * Parameters: irc - IRC number + * 1 for IRC is connected to DIN10 and DIN11 + * 2 for IRC is connected to DIN14 and DIN15 + * enable - TRUE for IRC, FALSE for normal usage as digital inputs + */ +void setMuxForIRC(int8_t irc, boolean_t enable) { + + /* Enable Pin Muxing */ + kickerReg->KICKER0 = 0x83E70B13; + kickerReg->KICKER1 = 0x95A4F1E0; + + if (enable) { + switch (irc) { + case 1: // set DIN10 and DIN11 to HET2 + PINMUX_SET(2,C1,HET2_0); + PINMUX_SET(2,E1,HET2_2); + break; + case 2: // set DIN14 and DIN15 to HET2 + PINMUX_SET(3,H3,HET2_4); + PINMUX_SET(4,M1,HET2_6); + break; + } + } else { + switch (irc) { + case 1: // set DIN10 and DIN11 back from HET2 + PINMUX_SET(2,C1,GIOA_2); + PINMUX_SET(2,E1,GIOA_3); + break; + case 2: // set DIN14 and DIN15 back from HET2 + PINMUX_SET(3,H3,GIOA_6); + PINMUX_SET(4,M1,GIOA_7); + break; + } + } + + + + /* Disable Pin Muxing */ + kickerReg->KICKER0 = 0x00000000; + kickerReg->KICKER1 = 0x00000000; + +} -- 2.39.2