From 3814183deb0f4efa95b2fc7d31391d7118842cf5 Mon Sep 17 00:00:00 2001
From: Michal Sojka <sojkam1@fel.cvut.cz>
Date: Wed, 2 Sep 2015 17:57:18 +0200
Subject: [PATCH] tms570_hydctr: Reconfigure ADC to 24 channels

---
 rpp/include/drv/_tms570_hydctr/port_def.h |  2 +-
 rpp/src/sys/_tms570_hydctr/ti_drv_adc.c   | 14 +++++++++++---
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/rpp/include/drv/_tms570_hydctr/port_def.h b/rpp/include/drv/_tms570_hydctr/port_def.h
index b264b88..c08554c 100644
--- a/rpp/include/drv/_tms570_hydctr/port_def.h
+++ b/rpp/include/drv/_tms570_hydctr/port_def.h
@@ -31,7 +31,7 @@ enum port_id {
 	_PORT_COUNT,
 };
 
-#define PORT_ADC_CHANNELS 16
+#define PORT_ADC_CHANNELS 24
 
 static double port_adc_lsb2volts(uint16_t lsb)
 {
diff --git a/rpp/src/sys/_tms570_hydctr/ti_drv_adc.c b/rpp/src/sys/_tms570_hydctr/ti_drv_adc.c
index 0620182..07cf84c 100644
--- a/rpp/src/sys/_tms570_hydctr/ti_drv_adc.c
+++ b/rpp/src/sys/_tms570_hydctr/ti_drv_adc.c
@@ -35,7 +35,7 @@ void adcInit(void)
     adcREG1->CLOCKCR = 100/(1*1000000000/RPP_VCLK1_FREQ);	/* 100 = cycle time in ns */
 
     /** - Setup memory boundaries */
-    adcREG1->BNDCR  =(8U << 16U)|(8U + 8U);
+    adcREG1->BNDCR  =(8U << 16U)|(8U + 12U);
     adcREG1->BNDEND = 2U;
 
     /** - Setup event group conversion mode
@@ -267,7 +267,7 @@ static const uint32_t s_adcSelect[2U][3U] =
 
 
     // ADC1, Group1
-    // AD1IN[0-15] used on the HDK
+    // AD1IN[0-23] used on the HydCtr board
     _BV( 0) |
     _BV( 1) |
     _BV( 2) |
@@ -284,6 +284,14 @@ static const uint32_t s_adcSelect[2U][3U] =
     _BV(13) |
     _BV(14) |
     _BV(15) |
+    _BV(16) |
+    _BV(17) |
+    _BV(18) |
+    _BV(19) |
+    _BV(20) |
+    _BV(21) |
+    _BV(22) |
+    _BV(23) |
          0x0,
 
     // ADC1, Group2
@@ -367,7 +375,7 @@ static const uint32_t s_adcSelect[2U][3U] =
                                       // ADC, Group
 static const uint32_t s_adcFiFoSize[2U][3U] =
 {
-    {0U, 16U, 0U},
+    {0U, 24U, 0U},
     {0U,  0U, 0U}
 };
 
-- 
2.39.2