From: Michal Sojka Date: Wed, 2 Sep 2015 05:22:11 +0000 (+0200) Subject: Replace pinmux code for hydctr by halcogen generated one X-Git-Tag: eaton-0.6~5 X-Git-Url: http://rtime.felk.cvut.cz/gitweb/pes-rpp/rpp-lib.git/commitdiff_plain/e7f6b2ff04b04ea7887024b8b4c4141a64b1e1f5 Replace pinmux code for hydctr by halcogen generated one See the last but one commit for scripts that automatically generated this. --- diff --git a/rpp/include/sys/.gitattributes b/rpp/include/sys/.gitattributes index eb03979..e45bbe9 100644 --- a/rpp/include/sys/.gitattributes +++ b/rpp/include/sys/.gitattributes @@ -5,6 +5,7 @@ /hw_reg_access.h eaton /phy_dp83848h.h eaton /port.h eaton +/reg_pinmux.h eaton /std_nhet.h eaton /sys.h eaton /sys_core.h eaton diff --git a/rpp/include/sys/_tms570_hydctr/.gitattributes b/rpp/include/sys/_tms570_hydctr/.gitattributes index 2268aec..624400f 100644 --- a/rpp/include/sys/_tms570_hydctr/.gitattributes +++ b/rpp/include/sys/_tms570_hydctr/.gitattributes @@ -1,2 +1,3 @@ /port.h eaton +/reg_pinmux.h eaton /sys_pinmux.h eaton diff --git a/rpp/include/sys/_tms570_hydctr/reg_pinmux.h b/rpp/include/sys/_tms570_hydctr/reg_pinmux.h new file mode 100644 index 0000000..12263b0 --- /dev/null +++ b/rpp/include/sys/_tms570_hydctr/reg_pinmux.h @@ -0,0 +1,176 @@ +/** @file reg_pinmux.h +* @brief PINMUX Register Layer Header File +* @date 15.July.2015 +* @version 04.05.00 +* +* This file contains: +* - Definitions +* - Types +* - Interface Prototypes +* . +* which are relevant for the PINMUX driver. +*/ + +/* +* Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + +#ifndef __REG_PINMUX_H__ +#define __REG_PINMUX_H__ + +#include "base.h" + + + +/* IOMM Revision and Boot Register */ +#define REVISION_REG (*(volatile uint32_t *)0xFFFFEA00U) +#define ENDIAN_REG (*(volatile uint32_t *)0xFFFFEA20U) + +/* IOMM Error and Fault Registers */ +/** @struct iommErrFault +* @brief IOMM Error and Fault Register Definition +* +* This structure is used to access the IOMM Error and Fault registers. +*/ +typedef volatile struct iommErrFault +{ + uint32_t ERR_RAW_STATUS_REG; /* Error Raw Status / Set Register */ + uint32_t ERR_ENABLED_STATUS_REG; /* Error Enabled Status / Clear Register */ + uint32_t ERR_ENABLE_REG; /* Error Signaling Enable Register */ + uint32_t ERR_ENABLE_CLR_REG; /* Error Signaling Enable Clear Register */ + uint32_t rsvd; /* Reserved */ + uint32_t FAULT_ADDRESS_REG; /* Fault Address Register */ + uint32_t FAULT_STATUS_REG; /* Fault Status Register */ + uint32_t FAULT_CLEAR_REG; /* Fault Clear Register */ +} iommErrFault_t; +/* Pinmux Register Frame Definition */ +/** @struct pinMuxKicker +* @brief Pin Muxing Kicker Register Definition +* +* This structure is used to access the Pin Muxing Kicker registers. +*/ +typedef volatile struct pinMuxKicker +{ + uint32_t KICKER0; /* kicker 0 register */ + uint32_t KICKER1; /* kicker 1 register */ +} pinMuxKICKER_t; + +/** @struct pinMuxBase +* @brief PINMUX Register Definition +* +* This structure is used to access the PINMUX module registers. +*/ +/** @typedef pinMuxBASE_t +* @brief PINMUX Register Frame Type Definition +* +* This type is used to access the PINMUX Registers. +*/ +typedef volatile struct pinMuxBase +{ + uint32_t PINMMR0; /**< 0xEB10 Pin Mux 0 register*/ + uint32_t PINMMR1; /**< 0xEB14 Pin Mux 1 register*/ + uint32_t PINMMR2; /**< 0xEB18 Pin Mux 2 register*/ + uint32_t PINMMR3; /**< 0xEB1C Pin Mux 3 register*/ + uint32_t PINMMR4; /**< 0xEB20 Pin Mux 4 register*/ + uint32_t PINMMR5; /**< 0xEB24 Pin Mux 5 register*/ + uint32_t PINMMR6; /**< 0xEB28 Pin Mux 6 register*/ + uint32_t PINMMR7; /**< 0xEB2C Pin Mux 7 register*/ + uint32_t PINMMR8; /**< 0xEB30 Pin Mux 8 register*/ + uint32_t PINMMR9; /**< 0xEB34 Pin Mux 9 register*/ + uint32_t PINMMR10; /**< 0xEB38 Pin Mux 10 register*/ + uint32_t PINMMR11; /**< 0xEB3C Pin Mux 11 register*/ + uint32_t PINMMR12; /**< 0xEB40 Pin Mux 12 register*/ + uint32_t PINMMR13; /**< 0xEB44 Pin Mux 13 register*/ + uint32_t PINMMR14; /**< 0xEB48 Pin Mux 14 register*/ + uint32_t PINMMR15; /**< 0xEB4C Pin Mux 15 register*/ + uint32_t PINMMR16; /**< 0xEB50 Pin Mux 16 register*/ + uint32_t PINMMR17; /**< 0xEB54 Pin Mux 17 register*/ + uint32_t PINMMR18; /**< 0xEB58 Pin Mux 18 register*/ + uint32_t PINMMR19; /**< 0xEB5C Pin Mux 19 register*/ + uint32_t PINMMR20; /**< 0xEB60 Pin Mux 20 register*/ + uint32_t PINMMR21; /**< 0xEB64 Pin Mux 21 register*/ + uint32_t PINMMR22; /**< 0xEB68 Pin Mux 22 register*/ + uint32_t PINMMR23; /**< 0xEB6C Pin Mux 23 register*/ + uint32_t PINMMR24; /**< 0xEB70 Pin Mux 24 register*/ + uint32_t PINMMR25; /**< 0xEB74 Pin Mux 25 register*/ + uint32_t PINMMR26; /**< 0xEB78 Pin Mux 26 register*/ + uint32_t PINMMR27; /**< 0xEB7C Pin Mux 27 register*/ + uint32_t PINMMR28; /**< 0xEB80 Pin Mux 28 register*/ + uint32_t PINMMR29; /**< 0xEB84 Pin Mux 29 register*/ + uint32_t PINMMR30; /**< 0xEB88 Pin Mux 30 register*/ + uint32_t PINMMR31; /**< 0xEB8C Pin Mux 31 register*/ + uint32_t PINMMR32; /**< 0xEB90 Pin Mux 32 register*/ + uint32_t PINMMR33; /**< 0xEB94 Pin Mux 33 register*/ + uint32_t PINMMR34; /**< 0xEB98 Pin Mux 34 register*/ + uint32_t PINMMR35; /**< 0xEB9C Pin Mux 35 register*/ + uint32_t PINMMR36; /**< 0xEBA0 Pin Mux 36 register*/ + uint32_t PINMMR37; /**< 0xEBA4 Pin Mux 37 register*/ + uint32_t PINMMR38; /**< 0xEBA8 Pin Mux 38 register*/ + uint32_t PINMMR39; /**< 0xEBAC Pin Mux 39 register*/ + uint32_t PINMMR40; /**< 0xEBB0 Pin Mux 40 register*/ + uint32_t PINMMR41; /**< 0xEBB4 Pin Mux 41 register*/ + uint32_t PINMMR42; /**< 0xEBB8 Pin Mux 42 register*/ + uint32_t PINMMR43; /**< 0xEBBC Pin Mux 43 register*/ + uint32_t PINMMR44; /**< 0xEBC0 Pin Mux 44 register*/ + uint32_t PINMMR45; /**< 0xEBC4 Pin Mux 45 register*/ + uint32_t PINMMR46; /**< 0xEBC8 Pin Mux 46 register*/ + uint32_t PINMMR47; /**< 0xEBCC Pin Mux 47 register*/ + +}pinMuxBASE_t; + + +/** @def iommErrFaultReg +* @brief IOMM Error Fault Register Frame Pointer +* +* This pointer is used to control IOMM Error and Fault across the device. +*/ +#define iommErrFaultReg ((iommErrFault_t *) 0xFFFFEAE0U) + +/** @def kickerReg +* @brief Pin Muxing Kicker Register Frame Pointer +* +* This pointer is used to enable and disable muxing across the device. +*/ +#define kickerReg ((pinMuxKICKER_t *) 0xFFFFEA38U) + +/** @def pinMuxReg +* @brief Pin Muxing Control Register Frame Pointer +* +* This pointer is used to set the muxing registers across the device. +*/ +#define pinMuxReg ((pinMuxBASE_t *) 0xFFFFEB10U) + + + +#endif diff --git a/rpp/include/sys/_tms570_hydctr/sys_pinmux.h b/rpp/include/sys/_tms570_hydctr/sys_pinmux.h index 75a11ce..ecbe3e0 100644 --- a/rpp/include/sys/_tms570_hydctr/sys_pinmux.h +++ b/rpp/include/sys/_tms570_hydctr/sys_pinmux.h @@ -1,839 +1,687 @@ /** @file pinmux.h * @brief PINMUX Driver Implementation File -* @date 15.Mar.2012 -* @version 03.01.00 +* @date 15.July.2015 +* @version 04.05.00 * */ -/* (c) Texas Instruments 2009-2012, All rights reserved. */ +/* +* Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ -#include "base.h" -#include "../system.h" #ifndef __PINMUX_H__ #define __PINMUX_H__ -/* Pin A3 options */ -#define PINMUX_BALL_A3_SHIFT 0 -#define PINMUX_BALL_A5_SHIFT 8 -#define PINMUX_BALL_A9_SHIFT 24 -#define PINMUX_BALL_A11_SHIFT 8 -#define PINMUX_BALL_A13_SHIFT 16 -#define PINMUX_BALL_A14_SHIFT 0 -#define PINMUX_BALL_B2_SHIFT 24 -#define PINMUX_BALL_B3_SHIFT 8 -#define PINMUX_BALL_B4_SHIFT 16 -#define PINMUX_BALL_B5_SHIFT 24 -#define PINMUX_BALL_B6_SHIFT 8 -#define PINMUX_BALL_B11_SHIFT 8 -#define PINMUX_BALL_B13_SHIFT 24 -#define PINMUX_BALL_C1_SHIFT 0 -#define PINMUX_BALL_C2_SHIFT 0 -#define PINMUX_BALL_C3_SHIFT 16 -#define PINMUX_BALL_C4_SHIFT 16 -#define PINMUX_BALL_C5_SHIFT 8 -#define PINMUX_BALL_C6_SHIFT 0 -#define PINMUX_BALL_C7_SHIFT 24 -#define PINMUX_BALL_C8_SHIFT 16 -#define PINMUX_BALL_C9_SHIFT 24 -#define PINMUX_BALL_C10_SHIFT 8 -#define PINMUX_BALL_C11_SHIFT 0 -#define PINMUX_BALL_C12_SHIFT 16 -#define PINMUX_BALL_C13_SHIFT 0 -#define PINMUX_BALL_C14_SHIFT 8 -#define PINMUX_BALL_C15_SHIFT 16 -#define PINMUX_BALL_C16_SHIFT 8 -#define PINMUX_BALL_C17_SHIFT 0 -#define PINMUX_BALL_D3_SHIFT 0 -#define PINMUX_BALL_D4_SHIFT 0 -#define PINMUX_BALL_D5_SHIFT 0 -#define PINMUX_BALL_D14_SHIFT 16 -#define PINMUX_BALL_D15_SHIFT 24 -#define PINMUX_BALL_D16_SHIFT 24 -#define PINMUX_BALL_D17_SHIFT 16 -#define PINMUX_BALL_D19_SHIFT 0 -#define PINMUX_BALL_E1_SHIFT 16 -#define PINMUX_BALL_E3_SHIFT 8 -#define PINMUX_BALL_E5_SHIFT 16 -#define PINMUX_BALL_E6_SHIFT 24 -#define PINMUX_BALL_E7_SHIFT 24 -#define PINMUX_BALL_E8_SHIFT 0 -#define PINMUX_BALL_E9_SHIFT 24 -#define PINMUX_BALL_E10_SHIFT 16 -#define PINMUX_BALL_E11_SHIFT 8 -#define PINMUX_BALL_E12_SHIFT 24 -#define PINMUX_BALL_E13_SHIFT 0 -#define PINMUX_BALL_E16_SHIFT 16 -#define PINMUX_BALL_E17_SHIFT 8 -#define PINMUX_BALL_E18_SHIFT 0 -#define PINMUX_BALL_E19_SHIFT 0 -#define PINMUX_BALL_F3_SHIFT 16 -#define PINMUX_BALL_F5_SHIFT 24 -#define PINMUX_BALL_G3_SHIFT 8 -#define PINMUX_BALL_G5_SHIFT 8 -#define PINMUX_BALL_G16_SHIFT 24 -#define PINMUX_BALL_G17_SHIFT 0 -#define PINMUX_BALL_G19_SHIFT 16 -#define PINMUX_BALL_H3_SHIFT 16 -#define PINMUX_BALL_H4_SHIFT 0 -#define PINMUX_BALL_H16_SHIFT 16 -#define PINMUX_BALL_H17_SHIFT 24 -#define PINMUX_BALL_H18_SHIFT 24 -#define PINMUX_BALL_H19_SHIFT 16 -#define PINMUX_BALL_J3_SHIFT 24 -#define PINMUX_BALL_J4_SHIFT 8 -#define PINMUX_BALL_J17_SHIFT 8 -#define PINMUX_BALL_J18_SHIFT 0 -#define PINMUX_BALL_J19_SHIFT 8 -#define PINMUX_BALL_K2_SHIFT 8 -#define PINMUX_BALL_K5_SHIFT 0 -#define PINMUX_BALL_K15_SHIFT 8 -#define PINMUX_BALL_K17_SHIFT 0 -#define PINMUX_BALL_K18_SHIFT 0 -#define PINMUX_BALL_K19_SHIFT 8 -#define PINMUX_BALL_L5_SHIFT 24 -#define PINMUX_BALL_L15_SHIFT 16 -#define PINMUX_BALL_M1_SHIFT 0 -#define PINMUX_BALL_M2_SHIFT 24 -#define PINMUX_BALL_M3_SHIFT 16 -#define PINMUX_BALL_M5_SHIFT 8 -#define PINMUX_BALL_M15_SHIFT 24 -#define PINMUX_BALL_M17_SHIFT 8 -#define PINMUX_BALL_N1_SHIFT 16 -#define PINMUX_BALL_N2_SHIFT 0 -#define PINMUX_BALL_N5_SHIFT 24 -#define PINMUX_BALL_N15_SHIFT 8 -#define PINMUX_BALL_N17_SHIFT 16 -#define PINMUX_BALL_N19_SHIFT 0 -#define PINMUX_BALL_P1_SHIFT 24 -#define PINMUX_BALL_P5_SHIFT 8 -#define PINMUX_BALL_R2_SHIFT 24 -#define PINMUX_BALL_R5_SHIFT 24 -#define PINMUX_BALL_R6_SHIFT 0 -#define PINMUX_BALL_R7_SHIFT 24 -#define PINMUX_BALL_R8_SHIFT 24 -#define PINMUX_BALL_R9_SHIFT 0 -#define PINMUX_BALL_T1_SHIFT 0 -#define PINMUX_BALL_T12_SHIFT 24 -#define PINMUX_BALL_U1_SHIFT 24 -#define PINMUX_BALL_V2_SHIFT 16 -#define PINMUX_BALL_V5_SHIFT 8 -#define PINMUX_BALL_V6_SHIFT 16 -#define PINMUX_BALL_V7_SHIFT 16 -#define PINMUX_BALL_V10_SHIFT 16 -#define PINMUX_BALL_W3_SHIFT 16 -#define PINMUX_BALL_W5_SHIFT 8 -#define PINMUX_BALL_W6_SHIFT 16 -#define PINMUX_BALL_W9_SHIFT 8 -#define PINMUX_BALL_W10_SHIFT 0 - -#define PINMUX_GATE_EMIF_CLK_SHIFT 8 -#define PINMUX_GIOB_DISABLE_HET2_SHIFT 16 -#define PINMUX_ALT_ADC_TRIGGER_SHIFT 0 -#define PINMUX_ETHERNET_SHIFT 24 - -#define PINMUX_BALL_A3_MASK (~(0xFF << PINMUX_BALL_A3_SHIFT)) -#define PINMUX_BALL_A5_MASK (~(0xFF << PINMUX_BALL_A5_SHIFT)) -#define PINMUX_BALL_A9_MASK (~(0xFF << PINMUX_BALL_A9_SHIFT)) -#define PINMUX_BALL_A11_MASK (~(0xFF << PINMUX_BALL_A11_SHIFT)) -#define PINMUX_BALL_A13_MASK (~(0xFF << PINMUX_BALL_A13_SHIFT)) -#define PINMUX_BALL_A14_MASK (~(0xFF << PINMUX_BALL_A14_SHIFT)) -#define PINMUX_BALL_B2_MASK (~(0xFF << PINMUX_BALL_B2_SHIFT)) -#define PINMUX_BALL_B3_MASK (~(0xFF << PINMUX_BALL_B3_SHIFT)) -#define PINMUX_BALL_B4_MASK (~(0xFF << PINMUX_BALL_B4_SHIFT)) -#define PINMUX_BALL_B5_MASK (~(0xFF << PINMUX_BALL_B5_SHIFT)) -#define PINMUX_BALL_B6_MASK (~(0xFF << PINMUX_BALL_B6_SHIFT)) -#define PINMUX_BALL_B11_MASK (~(0xFF << PINMUX_BALL_B11_SHIFT)) -#define PINMUX_BALL_B13_MASK (~(0xFF << PINMUX_BALL_B13_SHIFT)) -#define PINMUX_BALL_C1_MASK (~(0xFF << PINMUX_BALL_C1_SHIFT)) -#define PINMUX_BALL_C2_MASK (~(0xFF << PINMUX_BALL_C2_SHIFT)) -#define PINMUX_BALL_C3_MASK (~(0xFF << PINMUX_BALL_C3_SHIFT)) -#define PINMUX_BALL_C4_MASK (~(0xFF << PINMUX_BALL_C4_SHIFT)) -#define PINMUX_BALL_C5_MASK (~(0xFF << PINMUX_BALL_C5_SHIFT)) -#define PINMUX_BALL_C6_MASK (~(0xFF << PINMUX_BALL_C6_SHIFT)) -#define PINMUX_BALL_C7_MASK (~(0xFF << PINMUX_BALL_C7_SHIFT)) -#define PINMUX_BALL_C8_MASK (~(0xFF << PINMUX_BALL_C8_SHIFT)) -#define PINMUX_BALL_C9_MASK (~(0xFF << PINMUX_BALL_C9_SHIFT)) -#define PINMUX_BALL_C10_MASK (~(0xFF << PINMUX_BALL_C10_SHIFT)) -#define PINMUX_BALL_C11_MASK (~(0xFF << PINMUX_BALL_C11_SHIFT)) -#define PINMUX_BALL_C12_MASK (~(0xFF << PINMUX_BALL_C12_SHIFT)) -#define PINMUX_BALL_C13_MASK (~(0xFF << PINMUX_BALL_C13_SHIFT)) -#define PINMUX_BALL_C14_MASK (~(0xFF << PINMUX_BALL_C14_SHIFT)) -#define PINMUX_BALL_C15_MASK (~(0xFF << PINMUX_BALL_C15_SHIFT)) -#define PINMUX_BALL_C16_MASK (~(0xFF << PINMUX_BALL_C16_SHIFT)) -#define PINMUX_BALL_C17_MASK (~(0xFF << PINMUX_BALL_C17_SHIFT)) -#define PINMUX_BALL_D3_MASK (~(0xFF << PINMUX_BALL_D3_SHIFT)) -#define PINMUX_BALL_D4_MASK (~(0xFF << PINMUX_BALL_D4_SHIFT)) -#define PINMUX_BALL_D5_MASK (~(0xFF << PINMUX_BALL_D5_SHIFT)) -#define PINMUX_BALL_D14_MASK (~(0xFF << PINMUX_BALL_D14_SHIFT)) -#define PINMUX_BALL_D15_MASK (~(0xFF << PINMUX_BALL_D15_SHIFT)) -#define PINMUX_BALL_D16_MASK (~(0xFF << PINMUX_BALL_D16_SHIFT)) -#define PINMUX_BALL_D17_MASK (~(0xFF << PINMUX_BALL_D17_SHIFT)) -#define PINMUX_BALL_D19_MASK (~(0xFF << PINMUX_BALL_D19_SHIFT)) -#define PINMUX_BALL_E1_MASK (~(0xFF << PINMUX_BALL_E1_SHIFT)) -#define PINMUX_BALL_E3_MASK (~(0xFF << PINMUX_BALL_E3_SHIFT)) -#define PINMUX_BALL_E5_MASK (~(0xFF << PINMUX_BALL_E5_SHIFT)) -#define PINMUX_BALL_E6_MASK (~(0xFF << PINMUX_BALL_E6_SHIFT)) -#define PINMUX_BALL_E7_MASK (~(0xFF << PINMUX_BALL_E7_SHIFT)) -#define PINMUX_BALL_E8_MASK (~(0xFF << PINMUX_BALL_E8_SHIFT)) -#define PINMUX_BALL_E9_MASK (~(0xFF << PINMUX_BALL_E9_SHIFT)) -#define PINMUX_BALL_E10_MASK (~(0xFF << PINMUX_BALL_E10_SHIFT)) -#define PINMUX_BALL_E11_MASK (~(0xFF << PINMUX_BALL_E11_SHIFT)) -#define PINMUX_BALL_E12_MASK (~(0xFF << PINMUX_BALL_E12_SHIFT)) -#define PINMUX_BALL_E13_MASK (~(0xFF << PINMUX_BALL_E13_SHIFT)) -#define PINMUX_BALL_E16_MASK (~(0xFF << PINMUX_BALL_E16_SHIFT)) -#define PINMUX_BALL_E17_MASK (~(0xFF << PINMUX_BALL_E17_SHIFT)) -#define PINMUX_BALL_E18_MASK (~(0xFF << PINMUX_BALL_E18_SHIFT)) -#define PINMUX_BALL_E19_MASK (~(0xFF << PINMUX_BALL_E19_SHIFT)) -#define PINMUX_BALL_F3_MASK (~(0xFF << PINMUX_BALL_F3_SHIFT)) -#define PINMUX_BALL_F5_MASK (~(0xFF << PINMUX_BALL_F4_SHIFT)) -#define PINMUX_BALL_G3_MASK (~(0xFF << PINMUX_BALL_G3_SHIFT)) -#define PINMUX_BALL_G5_MASK (~(0xFF << PINMUX_BALL_G4_SHIFT)) -#define PINMUX_BALL_G16_MASK (~(0xFF << PINMUX_BALL_G16_SHIFT)) -#define PINMUX_BALL_G17_MASK (~(0xFF << PINMUX_BALL_G17_SHIFT)) -#define PINMUX_BALL_G19_MASK (~(0xFF << PINMUX_BALL_G19_SHIFT)) -#define PINMUX_BALL_H3_MASK (~(0xFF << PINMUX_BALL_H3_SHIFT)) -#define PINMUX_BALL_H4_MASK (~(0xFF << PINMUX_BALL_H4_SHIFT)) -#define PINMUX_BALL_H16_MASK (~(0xFF << PINMUX_BALL_H16_SHIFT)) -#define PINMUX_BALL_H17_MASK (~(0xFF << PINMUX_BALL_H17_SHIFT)) -#define PINMUX_BALL_H18_MASK (~(0xFF << PINMUX_BALL_H18_SHIFT)) -#define PINMUX_BALL_H19_MASK (~(0xFF << PINMUX_BALL_H19_SHIFT)) -#define PINMUX_BALL_J3_MASK (~(0xFF << PINMUX_BALL_J3_SHIFT)) -#define PINMUX_BALL_J4_MASK (~(0xFF << PINMUX_BALL_J4_SHIFT)) -#define PINMUX_BALL_J17_MASK (~(0xFF << PINMUX_BALL_J17_SHIFT)) -#define PINMUX_BALL_J18_MASK (~(0xFF << PINMUX_BALL_J18_SHIFT)) -#define PINMUX_BALL_J19_MASK (~(0xFF << PINMUX_BALL_J19_SHIFT)) -#define PINMUX_BALL_K2_MASK (~(0xFF << PINMUX_BALL_K2_SHIFT)) -#define PINMUX_BALL_K5_MASK (~(0xFF << PINMUX_BALL_K4_SHIFT)) -#define PINMUX_BALL_K15_MASK (~(0xFF << PINMUX_BALL_K15_SHIFT)) -#define PINMUX_BALL_K17_MASK (~(0xFF << PINMUX_BALL_K17_SHIFT)) -#define PINMUX_BALL_K18_MASK (~(0xFF << PINMUX_BALL_K18_SHIFT)) -#define PINMUX_BALL_K19_MASK (~(0xFF << PINMUX_BALL_K19_SHIFT)) -#define PINMUX_BALL_L5_MASK (~(0xFF << PINMUX_BALL_L4_SHIFT)) -#define PINMUX_BALL_L15_MASK (~(0xFF << PINMUX_BALL_L15_SHIFT)) -#define PINMUX_BALL_M1_MASK (~(0xFF << PINMUX_BALL_M1_SHIFT)) -#define PINMUX_BALL_M2_MASK (~(0xFF << PINMUX_BALL_M2_SHIFT)) -#define PINMUX_BALL_M3_MASK (~(0xFF << PINMUX_BALL_M3_SHIFT)) -#define PINMUX_BALL_M5_MASK (~(0xFF << PINMUX_BALL_M4_SHIFT)) -#define PINMUX_BALL_M15_MASK (~(0xFF << PINMUX_BALL_M15_SHIFT)) -#define PINMUX_BALL_M17_MASK (~(0xFF << PINMUX_BALL_M17_SHIFT)) -#define PINMUX_BALL_N1_MASK (~(0xFF << PINMUX_BALL_N1_SHIFT)) -#define PINMUX_BALL_N2_MASK (~(0xFF << PINMUX_BALL_N2_SHIFT)) -#define PINMUX_BALL_N5_MASK (~(0xFF << PINMUX_BALL_N4_SHIFT)) -#define PINMUX_BALL_N15_MASK (~(0xFF << PINMUX_BALL_N15_SHIFT)) -#define PINMUX_BALL_N17_MASK (~(0xFF << PINMUX_BALL_N17_SHIFT)) -#define PINMUX_BALL_N19_MASK (~(0xFF << PINMUX_BALL_N19_SHIFT)) -#define PINMUX_BALL_P1_MASK (~(0xFF << PINMUX_BALL_P1_SHIFT)) -#define PINMUX_BALL_P5_MASK (~(0xFF << PINMUX_BALL_P4_SHIFT)) -#define PINMUX_BALL_R2_MASK (~(0xFF << PINMUX_BALL_R2_SHIFT)) -#define PINMUX_BALL_R5_MASK (~(0xFF << PINMUX_BALL_R5_SHIFT)) -#define PINMUX_BALL_R6_MASK (~(0xFF << PINMUX_BALL_R6_SHIFT)) -#define PINMUX_BALL_R7_MASK (~(0xFF << PINMUX_BALL_R7_SHIFT)) -#define PINMUX_BALL_R8_MASK (~(0xFF << PINMUX_BALL_R8_SHIFT)) -#define PINMUX_BALL_R9_MASK (~(0xFF << PINMUX_BALL_R9_SHIFT)) -#define PINMUX_BALL_T1_MASK (~(0xFF << PINMUX_BALL_T1_SHIFT)) -#define PINMUX_BALL_T12_MASK (~(0xFF << PINMUX_BALL_T12_SHIFT)) -#define PINMUX_BALL_U1_MASK (~(0xFF << PINMUX_BALL_U1_SHIFT)) -#define PINMUX_BALL_V2_MASK (~(0xFF << PINMUX_BALL_V2_SHIFT)) -#define PINMUX_BALL_V5_MASK (~(0xFF << PINMUX_BALL_V5_SHIFT)) -#define PINMUX_BALL_V6_MASK (~(0xFF << PINMUX_BALL_V6_SHIFT)) -#define PINMUX_BALL_V7_MASK (~(0xFF << PINMUX_BALL_V7_SHIFT)) -#define PINMUX_BALL_V10_MASK (~(0xFF << PINMUX_BALL_V10_SHIFT)) -#define PINMUX_BALL_W3_MASK (~(0xFF << PINMUX_BALL_W3_SHIFT)) -#define PINMUX_BALL_W5_MASK (~(0xFF << PINMUX_BALL_W5_SHIFT)) -#define PINMUX_BALL_W6_MASK (~(0xFF << PINMUX_BALL_W6_SHIFT)) -#define PINMUX_BALL_W9_MASK (~(0xFF << PINMUX_BALL_W9_SHIFT)) -#define PINMUX_BALL_W10_MASK (~(0xFF << PINMUX_BALL_W10_SHIFT)) - -#define PINMUX_GATE_EMIF_CLK_MASK (~(0xFF << PINMUX_GATE_EMIF_CLK_SHIFT)) -#define PINMUX_GIOB_DISABLE_HET2_MASK (~(0xFF << PINMUX_GIOB_DISABLE_HET2_SHIFT)) -#define PINMUX_ALT_ADC_TRIGGER_MASK (~(0xFF << PINMUX_ALT_ADC_TRIGGER_SHIFT)) -#define PINMUX_ETHERNET_MASK (~(0xFF << PINMUX_ETHERNET_SHIFT)) - - -/* Pin A3 options */ -#define PINMUX_BALL_A3_HET1_29 (0x1 << PINMUX_BALL_A3_SHIFT) +#include "base.h" +#include "sys/reg_pinmux.h" -/* Pin A5 options */ -#define PINMUX_BALL_A5_GIOA_0 (0x1 << PINMUX_BALL_A5_SHIFT) -#define PINMUX_BALL_A5_OHCI_PRT_RcvDpls_1 (0x2 << PINMUX_BALL_A5_SHIFT) -#define PINMUX_BALL_A5_W2FC_RXDPI (0x4 << PINMUX_BALL_A5_SHIFT) +#ifdef __cplusplus +extern "C" { +#endif -/* Pin A9 options */ -#define PINMUX_BALL_A9_HET1_27 (0x1 << PINMUX_BALL_A9_SHIFT) +/* Pin A4 options */ +#define PINMUX_BALL_A4_SHIFT 0U +#define PINMUX_BALL_A5_SHIFT 8U +#define PINMUX_BALL_A11_SHIFT 8U +#define PINMUX_BALL_A14_SHIFT 0U +#define PINMUX_BALL_B2_SHIFT 24U +#define PINMUX_BALL_B3_SHIFT 8U +#define PINMUX_BALL_B4_SHIFT 16U +#define PINMUX_BALL_B5_SHIFT 24U +#define PINMUX_BALL_B11_SHIFT 8U +#define PINMUX_BALL_B12_SHIFT 0U +#define PINMUX_BALL_C1_SHIFT 0U +#define PINMUX_BALL_C2_SHIFT 0U +#define PINMUX_BALL_C3_SHIFT 16U +#define PINMUX_BALL_C4_SHIFT 16U +#define PINMUX_BALL_C5_SHIFT 8U +#define PINMUX_BALL_C6_SHIFT 0U +#define PINMUX_BALL_D3_SHIFT 0U +#define PINMUX_BALL_D4_SHIFT 0U +#define PINMUX_BALL_D5_SHIFT 0U +#define PINMUX_BALL_D16_SHIFT 24U +#define PINMUX_BALL_D17_SHIFT 16U +#define PINMUX_BALL_D19_SHIFT 0U +#define PINMUX_BALL_E1_SHIFT 16U +#define PINMUX_BALL_E3_SHIFT 8U +#define PINMUX_BALL_E18_SHIFT 0U +#define PINMUX_BALL_E19_SHIFT 0U +#define PINMUX_BALL_F3_SHIFT 16U +#define PINMUX_BALL_G3_SHIFT 8U +#define PINMUX_BALL_G19_SHIFT 16U +#define PINMUX_BALL_H3_SHIFT 16U +#define PINMUX_BALL_H18_SHIFT 24U +#define PINMUX_BALL_H19_SHIFT 16U +#define PINMUX_BALL_J1_SHIFT 8U +#define PINMUX_BALL_J3_SHIFT 24U +#define PINMUX_BALL_J18_SHIFT 0U +#define PINMUX_BALL_J19_SHIFT 8U +#define PINMUX_BALL_K2_SHIFT 8U +#define PINMUX_BALL_K17_SHIFT 0U +#define PINMUX_BALL_K18_SHIFT 0U +#define PINMUX_BALL_K19_SHIFT 8U +#define PINMUX_BALL_M1_SHIFT 0U +#define PINMUX_BALL_M2_SHIFT 24U +#define PINMUX_BALL_N1_SHIFT 16U +#define PINMUX_BALL_N2_SHIFT 0U +#define PINMUX_BALL_N17_SHIFT 16U +#define PINMUX_BALL_N19_SHIFT 0U +#define PINMUX_BALL_P1_SHIFT 24U +#define PINMUX_BALL_P2_SHIFT 16U +#define PINMUX_BALL_R2_SHIFT 24U +#define PINMUX_BALL_T1_SHIFT 0U +#define PINMUX_BALL_U1_SHIFT 24U +#define PINMUX_BALL_V2_SHIFT 16U +#define PINMUX_BALL_V5_SHIFT 8U +#define PINMUX_BALL_V6_SHIFT 16U +#define PINMUX_BALL_V7_SHIFT 16U +#define PINMUX_BALL_V8_SHIFT 8U +#define PINMUX_BALL_V9_SHIFT 24U +#define PINMUX_BALL_V10_SHIFT 16U +#define PINMUX_BALL_W3_SHIFT 16U +#define PINMUX_BALL_W5_SHIFT 8U +#define PINMUX_BALL_W8_SHIFT 16U +#define PINMUX_BALL_W9_SHIFT 8U +#define PINMUX_BALL_W10_SHIFT 0U + +#define PINMUX_GATE_EMIF_CLK_SHIFT 8U +#define PINMUX_GIOB_DISABLE_HET2_SHIFT 16U +#define PINMUX_ALT_ADC_TRIGGER_SHIFT 0U +#define PINMUX_ETHERNET_SHIFT 24U +#define PINMUX_ETPWM1_SHIFT 0U +#define PINMUX_ETPWM2_SHIFT 8U +#define PINMUX_ETPWM3_SHIFT 16U +#define PINMUX_ETPWM4_SHIFT 24U +#define PINMUX_ETPWM5_SHIFT 0U +#define PINMUX_ETPWM6_SHIFT 8U +#define PINMUX_ETPWM7_SHIFT 16U +#define PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT 24U +#define PINMUX_ETPWM_TBCLK_SYNC_SHIFT 0U +#define PINMUX_TZ1_SHIFT 16U +#define PINMUX_TZ2_SHIFT 24U +#define PINMUX_TZ3_SHIFT 0U +#define PINMUX_EPWM1SYNCI_SHIFT 8U + + +#define PINMUX_BALL_A4_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_A4_SHIFT)) +#define PINMUX_BALL_A5_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_A5_SHIFT)) +#define PINMUX_BALL_A11_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_A11_SHIFT)) +#define PINMUX_BALL_A14_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_A14_SHIFT)) +#define PINMUX_BALL_B2_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_B2_SHIFT)) +#define PINMUX_BALL_B3_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_B3_SHIFT)) +#define PINMUX_BALL_B4_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_B4_SHIFT)) +#define PINMUX_BALL_B5_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_B5_SHIFT)) +#define PINMUX_BALL_B11_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_B11_SHIFT)) +#define PINMUX_BALL_B12_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_B12_SHIFT)) +#define PINMUX_BALL_C1_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_C1_SHIFT)) +#define PINMUX_BALL_C2_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_C2_SHIFT)) +#define PINMUX_BALL_C3_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_C3_SHIFT)) +#define PINMUX_BALL_C4_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_C4_SHIFT)) +#define PINMUX_BALL_C5_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_C5_SHIFT)) +#define PINMUX_BALL_C6_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_C6_SHIFT)) +#define PINMUX_BALL_D3_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_D3_SHIFT)) +#define PINMUX_BALL_D4_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_D4_SHIFT)) +#define PINMUX_BALL_D5_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_D5_SHIFT)) +#define PINMUX_BALL_D16_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_D16_SHIFT)) +#define PINMUX_BALL_D17_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_D17_SHIFT)) +#define PINMUX_BALL_D19_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_D19_SHIFT)) +#define PINMUX_BALL_E1_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_E1_SHIFT)) +#define PINMUX_BALL_E3_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_E3_SHIFT)) +#define PINMUX_BALL_E18_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_E18_SHIFT)) +#define PINMUX_BALL_E19_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_E19_SHIFT)) +#define PINMUX_BALL_F3_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_F3_SHIFT)) +#define PINMUX_BALL_G3_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_G3_SHIFT)) +#define PINMUX_BALL_G19_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_G19_SHIFT)) +#define PINMUX_BALL_H3_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_H3_SHIFT)) +#define PINMUX_BALL_H18_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_H18_SHIFT)) +#define PINMUX_BALL_H19_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_H19_SHIFT)) +#define PINMUX_BALL_J1_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_J1_SHIFT)) +#define PINMUX_BALL_J3_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_J3_SHIFT)) +#define PINMUX_BALL_J18_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_J18_SHIFT)) +#define PINMUX_BALL_J19_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_J19_SHIFT)) +#define PINMUX_BALL_K2_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_K2_SHIFT)) +#define PINMUX_BALL_K17_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_K17_SHIFT)) +#define PINMUX_BALL_K18_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_K18_SHIFT)) +#define PINMUX_BALL_K19_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_K19_SHIFT)) +#define PINMUX_BALL_M1_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_M1_SHIFT)) +#define PINMUX_BALL_M2_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_M2_SHIFT)) +#define PINMUX_BALL_N1_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_N1_SHIFT)) +#define PINMUX_BALL_N2_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_N2_SHIFT)) +#define PINMUX_BALL_N17_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_N17_SHIFT)) +#define PINMUX_BALL_N19_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_N19_SHIFT)) +#define PINMUX_BALL_P1_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_P1_SHIFT)) +#define PINMUX_BALL_P2_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_P2_SHIFT)) +#define PINMUX_BALL_R2_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_R2_SHIFT)) +#define PINMUX_BALL_T1_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_T1_SHIFT)) +#define PINMUX_BALL_T12_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_T12_SHIFT)) +#define PINMUX_BALL_U1_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_U1_SHIFT)) +#define PINMUX_BALL_V2_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_V2_SHIFT)) +#define PINMUX_BALL_V5_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_V5_SHIFT)) +#define PINMUX_BALL_V6_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_V6_SHIFT)) +#define PINMUX_BALL_V7_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_V7_SHIFT)) +#define PINMUX_BALL_V8_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_V8_SHIFT)) +#define PINMUX_BALL_V9_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_V9_SHIFT)) +#define PINMUX_BALL_V10_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_V10_SHIFT)) +#define PINMUX_BALL_W3_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_W3_SHIFT)) +#define PINMUX_BALL_W5_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_W5_SHIFT)) +#define PINMUX_BALL_W8_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_W8_SHIFT)) +#define PINMUX_BALL_W9_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_W9_SHIFT)) +#define PINMUX_BALL_W10_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_BALL_W10_SHIFT)) + +#define PINMUX_GATE_EMIF_CLK_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_GATE_EMIF_CLK_SHIFT)) +#define PINMUX_GIOB_DISABLE_HET2_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_GIOB_DISABLE_HET2_SHIFT)) +#define PINMUX_ALT_ADC_TRIGGER_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_ALT_ADC_TRIGGER_SHIFT)) +#define PINMUX_ETHERNET_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_ETHERNET_SHIFT)) + +#define PINMUX_ETPWM1_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_ETPWM1_SHIFT)) +#define PINMUX_ETPWM2_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_ETPWM2_SHIFT)) +#define PINMUX_ETPWM3_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_ETPWM3_SHIFT)) +#define PINMUX_ETPWM4_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_ETPWM4_SHIFT)) +#define PINMUX_ETPWM5_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_ETPWM5_SHIFT)) +#define PINMUX_ETPWM6_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_ETPWM6_SHIFT)) +#define PINMUX_ETPWM7_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_ETPWM7_SHIFT)) +#define PINMUX_ETPWM_TIME_BASE_SYNC_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT)) +#define PINMUX_ETPWM_TBCLK_SYNC_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_ETPWM_TBCLK_SYNC_SHIFT)) +#define PINMUX_TZ1_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_TZ1_SHIFT)) +#define PINMUX_TZ2_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_TZ2_SHIFT)) +#define PINMUX_TZ3_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_TZ3_SHIFT)) +#define PINMUX_EPWM1SYNCI_MASK (~(uint32_t)((uint32_t)0xFFU << PINMUX_EPWM1SYNCI_SHIFT)) + + + +/* Pin A4 options */ +#define PINMUX_BALL_A4_HET1_16 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_A4_SHIFT)) +#define PINMUX_BALL_A4_ETPWM1SYNCI ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_A4_SHIFT)) +#define PINMUX_BALL_A4_ETPWM1SYNCO ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_A4_SHIFT)) -/* Pin A11 options */ -#define PINMUX_BALL_A11_HET1_14 (0x1 << PINMUX_BALL_A11_SHIFT) -#define PINMUX_BALL_A11_OHCI_RCFG_txSe0_0 (0x2 << PINMUX_BALL_A11_SHIFT) +/* Pin A5 options */ +#define PINMUX_BALL_A5_GIOA_0 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_A5_SHIFT)) +#define PINMUX_BALL_A5_OHCI_PRT_RcvDpls_1 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_A5_SHIFT)) +#define PINMUX_BALL_A5_W2FC_RXDPI ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_A5_SHIFT)) -/* Pin A13 options */ -#define PINMUX_BALL_A13_HET1_17 (0x1 << PINMUX_BALL_F3_SHIFT) +/* Pin A11 options */ +#define PINMUX_BALL_A11_HET1_14 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_A11_SHIFT)) +#define PINMUX_BALL_A11_OHCI_RCFG_txSe0_0 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_A11_SHIFT)) /* Pin A14 options */ -#define PINMUX_BALL_A14_HET1_26 (0x1 << PINMUX_BALL_A14_SHIFT) -#define PINMUX_BALL_A14_MII_RXD_1 (0x2 << PINMUX_BALL_A14_SHIFT) -#define PINMUX_BALL_A14_RMII_RXD_1 (0x4 << PINMUX_BALL_A14_SHIFT) +#define PINMUX_BALL_A14_HET1_26 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_A14_SHIFT)) +#define PINMUX_BALL_A14_MII_RXD_1 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_A14_SHIFT)) +#define PINMUX_BALL_A14_RMII_RXD_1 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_A14_SHIFT)) /* Pin B2 options */ -#define PINMUX_BALL_B2_MIBSPI3NCS_2 (0x1 << PINMUX_BALL_B2_SHIFT) -#define PINMUX_BALL_B2_I2C_SDA (0x2 << PINMUX_BALL_B2_SHIFT) -#define PINMUX_BALL_B2_HET1_27 (0x4 << PINMUX_BALL_B2_SHIFT) +#define PINMUX_BALL_B2_MIBSPI3NCS_2 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_B2_SHIFT)) +#define PINMUX_BALL_B2_I2C_SDA ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_B2_SHIFT)) +#define PINMUX_BALL_B2_HET1_27 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_B2_SHIFT)) +#define PINMUX_BALL_B2_nTZ2 ((uint32_t)((uint32_t)0x8U << PINMUX_BALL_B2_SHIFT)) /* Pin B3 options */ -#define PINMUX_BALL_B3_HET1_22 (0x1 << PINMUX_BALL_B3_SHIFT) -#define PINMUX_BALL_B3_OHCI_RCFG_txSe0_1 (0x2 << PINMUX_BALL_B3_SHIFT) -#define PINMUX_BALL_B3_W2FC_SE0O (0x4 << PINMUX_BALL_B3_SHIFT) +#define PINMUX_BALL_B3_HET1_22 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_B3_SHIFT)) +#define PINMUX_BALL_B3_OHCI_RCFG_txSe0_1 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_B3_SHIFT)) +#define PINMUX_BALL_B3_W2FC_SE0O ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_B3_SHIFT)) /* Pin B4 options */ -#define PINMUX_BALL_B4_HET1_12 (0x1 << PINMUX_BALL_B4_SHIFT) -#define PINMUX_BALL_B4_MII_CRS (0x2 << PINMUX_BALL_B4_SHIFT) -#define PINMUX_BALL_B4_RMII_CRS_DV (0x4 << PINMUX_BALL_B4_SHIFT) +#define PINMUX_BALL_B4_HET1_12 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_B4_SHIFT)) +#define PINMUX_BALL_B4_MII_CRS ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_B4_SHIFT)) +#define PINMUX_BALL_B4_RMII_CRS_DV ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_B4_SHIFT)) /* Pin B5 options */ -#define PINMUX_BALL_B5_GIOA_5 (0x1 << PINMUX_BALL_B5_SHIFT) -#define PINMUX_BALL_B5_EXTCLKIN (0x2 << PINMUX_BALL_B5_SHIFT) - -/* Pin B6 options */ -#define PINMUX_BALL_B6_MIBSPI5NCS_1 (0x1 << PINMUX_BALL_B6_SHIFT) -#define PINMUX_BALL_B6_DMM_DATA_6 (0x2 << PINMUX_BALL_B6_SHIFT) +#define PINMUX_BALL_B5_GIOA_5 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_B5_SHIFT)) +#define PINMUX_BALL_B5_EXTCLKIN ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_B5_SHIFT)) +#define PINMUX_BALL_B5_ETPWM1A ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_B5_SHIFT)) /* Pin B11 options */ -#define PINMUX_BALL_B11_HET1_30 (0x1 << PINMUX_BALL_B11_SHIFT) -#define PINMUX_BALL_B11_MII_RX_DV (0x2 << PINMUX_BALL_B11_SHIFT) -#define PINMUX_BALL_B11_OHCI_RCFG_speed_0 (0x4 << PINMUX_BALL_B11_SHIFT) - -/* Pin B13 options */ -#define PINMUX_BALL_B13_HET1_19 (0x1 << PINMUX_BALL_B13_SHIFT) +#define PINMUX_BALL_B11_HET1_30 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_B11_SHIFT)) +#define PINMUX_BALL_B11_MII_RX_DV ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_B11_SHIFT)) +#define PINMUX_BALL_B11_OHCI_RCFG_speed_0 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_B11_SHIFT)) +#define PINMUX_BALL_B11_EQEP2S ((uint32_t)((uint32_t)0x8U << PINMUX_BALL_B11_SHIFT)) +/* Pin B12 options */ +#define PINMUX_BALL_B12_HET1_04 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_B12_SHIFT)) +#define PINMUX_BALL_B12_ETPWM4B ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_B12_SHIFT)) /* Pin C1 options */ -#define PINMUX_BALL_C1_GIOA_2 (0x1 << PINMUX_BALL_C1_SHIFT) -#define PINMUX_BALL_C1_OHCI_RCFG_txdPls_1 (0x2 << PINMUX_BALL_C1_SHIFT) -#define PINMUX_BALL_C1_W2FC_TXDO (0x4 << PINMUX_BALL_C1_SHIFT) -#define PINMUX_BALL_C1_HET2_0 (0x8 << PINMUX_BALL_C1_SHIFT) +#define PINMUX_BALL_C1_GIOA_2 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_C1_SHIFT)) +#define PINMUX_BALL_C1_OHCI_RCFG_txdPls_1 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_C1_SHIFT)) +#define PINMUX_BALL_C1_W2FC_TXDO ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_C1_SHIFT)) +#define PINMUX_BALL_C1_HET2_0 ((uint32_t)((uint32_t)0x8U << PINMUX_BALL_C1_SHIFT)) +#define PINMUX_BALL_C1_EQEP2I ((uint32_t)((uint32_t)0x10U << PINMUX_BALL_C1_SHIFT)) + /* Pin C2 options */ -#define PINMUX_BALL_C2_GIOA_1 (0x1 << PINMUX_BALL_C2_SHIFT) -#define PINMUX_BALL_C2_OHCI_PRT_RcvDmns_1 (0x2 << PINMUX_BALL_C2_SHIFT) -#define PINMUX_BALL_C2_W2FC_RXDMI (0x4 << PINMUX_BALL_C2_SHIFT) +#define PINMUX_BALL_C2_GIOA_1 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_C2_SHIFT)) +#define PINMUX_BALL_C2_OHCI_PRT_RcvDmns_1 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_C2_SHIFT)) +#define PINMUX_BALL_C2_W2FC_RXDMI ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_C2_SHIFT)) /* Pin C3 options */ -#define PINMUX_BALL_C3_MIBSPI3NCS_3 (0x1 << PINMUX_BALL_C3_SHIFT) -#define PINMUX_BALL_C3_I2C_SCL (0x2 << PINMUX_BALL_C3_SHIFT) -#define PINMUX_BALL_C3_HET1_29 (0x4 << PINMUX_BALL_C3_SHIFT) +#define PINMUX_BALL_C3_MIBSPI3NCS_3 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_C3_SHIFT)) +#define PINMUX_BALL_C3_I2C_SCL ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_C3_SHIFT)) +#define PINMUX_BALL_C3_HET1_29 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_C3_SHIFT)) +#define PINMUX_BALL_C3_nTZ1 ((uint32_t)((uint32_t)0x8U << PINMUX_BALL_C3_SHIFT)) /* Pin C4 options */ -#define PINMUX_BALL_C4_EMIF_ADDR_6 (0x1 << PINMUX_BALL_C4_SHIFT) -#define PINMUX_BALL_C4_RTP_DATA_13 (0x2 << PINMUX_BALL_C4_SHIFT) -#define PINMUX_BALL_C4_HET2_11 (0x4 << PINMUX_BALL_C4_SHIFT) +#define PINMUX_BALL_C4_EMIF_ADDR_6 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_C4_SHIFT)) +#define PINMUX_BALL_C4_HET2_11 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_C4_SHIFT)) /* Pin C5 options */ -#define PINMUX_BALL_C5_EMIF_ADDR_7 (0x1 << PINMUX_BALL_C5_SHIFT) -#define PINMUX_BALL_C5_RTP_DATA_12 (0x2 << PINMUX_BALL_C5_SHIFT) -#define PINMUX_BALL_C5_HET2_13 (0x4 << PINMUX_BALL_C5_SHIFT) +#define PINMUX_BALL_C5_EMIF_ADDR_7 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_C5_SHIFT)) +#define PINMUX_BALL_C5_HET2_13 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_C5_SHIFT)) /* Pin C6 options */ -#define PINMUX_BALL_C6_EMIF_ADDR_8 (0x1 << PINMUX_BALL_C6_SHIFT) -#define PINMUX_BALL_C6_RTP_DATA_11 (0x2 << PINMUX_BALL_C6_SHIFT) -#define PINMUX_BALL_C6_HET2_15 (0x4 << PINMUX_BALL_C6_SHIFT) - -/* Pin C7 options */ -#define PINMUX_BALL_C7_EMIF_ADDR_9 (0x1 << PINMUX_BALL_C7_SHIFT) -#define PINMUX_BALL_C7_RTP_DATA_10 (0x2 << PINMUX_BALL_C7_SHIFT) - -/* Pin C8 options */ -#define PINMUX_BALL_C8_EMIF_ADDR_10 (0x1 << PINMUX_BALL_C8_SHIFT) -#define PINMUX_BALL_C8_RTP_DATA_09 (0x2 << PINMUX_BALL_C8_SHIFT) - -/* Pin C9 options */ -#define PINMUX_BALL_C9_EMIF_ADDR_11 (0x1 << PINMUX_BALL_C9_SHIFT) -#define PINMUX_BALL_C9_RTP_DATA_08 (0x2 << PINMUX_BALL_C9_SHIFT) - -/* Pin C10 options */ -#define PINMUX_BALL_C10_EMIF_ADDR_12 (0x1 << PINMUX_BALL_C10_SHIFT) -#define PINMUX_BALL_C10_RTP_DATA_06 (0x2 << PINMUX_BALL_C10_SHIFT) +#define PINMUX_BALL_C6_EMIF_ADDR_8 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_C6_SHIFT)) +#define PINMUX_BALL_C6_HET2_15 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_C6_SHIFT)) -/* Pin C11 options */ -#define PINMUX_BALL_C11_EMIF_ADDR_13 (0x1 << PINMUX_BALL_C11_SHIFT) -#define PINMUX_BALL_C11_RTP_DATA_05 (0x2 << PINMUX_BALL_C11_SHIFT) - -/* Pin C12 options */ -#define PINMUX_BALL_C12_EMIF_ADDR_14 (0x1 << PINMUX_BALL_C12_SHIFT) -#define PINMUX_BALL_C12_RTP_DATA_04 (0x2 << PINMUX_BALL_C12_SHIFT) - -/* Pin C13 options */ -#define PINMUX_BALL_C13_EMIF_ADDR_15 (0x1 << PINMUX_BALL_C13_SHIFT) -#define PINMUX_BALL_C13_RTP_DATA_03 (0x2 << PINMUX_BALL_C13_SHIFT) - -/* Pin C14 options */ -#define PINMUX_BALL_C14_EMIF_ADDR_17 (0x1 << PINMUX_BALL_C14_SHIFT) -#define PINMUX_BALL_C14_RTP_DATA_01 (0x2 << PINMUX_BALL_C14_SHIFT) - -/* Pin C15 options */ -#define PINMUX_BALL_C15_EMIF_ADDR_19 (0x1 << PINMUX_BALL_C15_SHIFT) -#define PINMUX_BALL_C15_RTP_nENA (0x2 << PINMUX_BALL_C15_SHIFT) - -/* Pin C16 options */ -#define PINMUX_BALL_C16_EMIF_ADDR_20 (0x1 << PINMUX_BALL_C16_SHIFT) -#define PINMUX_BALL_C16_RTP_nSYNC (0x2 << PINMUX_BALL_C16_SHIFT) - -/* Pin C17 options */ -#define PINMUX_BALL_C17_EMIF_ADDR_21 (0x1 << PINMUX_BALL_C17_SHIFT) -#define PINMUX_BALL_C17_RTP_CLK (0x2 << PINMUX_BALL_C17_SHIFT) /* Pin D3 options */ -#define PINMUX_BALL_D3_SPI2NENA (0x1 << PINMUX_BALL_D3_SHIFT) -#define PINMUX_BALL_D3_SPI2NCS_1 (0x2 << PINMUX_BALL_D3_SHIFT) +#define PINMUX_BALL_D3_SPI2NENA ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_D3_SHIFT)) +#define PINMUX_BALL_D3_SPI2NCS_1 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_D3_SHIFT)) /* Pin D4 options */ -#define PINMUX_BALL_D4_EMIF_ADDR_0 (0x1 << PINMUX_BALL_D4_SHIFT) -#define PINMUX_BALL_D4_HET2_1 (0x2 << PINMUX_BALL_D4_SHIFT) +#define PINMUX_BALL_D4_EMIF_ADDR_0 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_D4_SHIFT)) +#define PINMUX_BALL_D4_HET2_1 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_D4_SHIFT)) /* Pin D5 options */ -#define PINMUX_BALL_D5_EMIF_ADDR_1 (0x1 << PINMUX_BALL_D5_SHIFT) -#define PINMUX_BALL_D5_HET2_3 (0x2 << PINMUX_BALL_D5_SHIFT) - -/* Pin D14 options */ -#define PINMUX_BALL_D14_EMIF_ADDR_16 (0x1 << PINMUX_BALL_D14_SHIFT) -#define PINMUX_BALL_D14_RTP_DATA_02 (0x2 << PINMUX_BALL_D14_SHIFT) - -/* Pin D15 options */ -#define PINMUX_BALL_D15_EMIF_ADDR_18 (0x1 << PINMUX_BALL_D15_SHIFT) -#define PINMUX_BALL_D15_RTP_DATA_0 (0x2 << PINMUX_BALL_D15_SHIFT) +#define PINMUX_BALL_D5_EMIF_ADDR_1 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_D5_SHIFT)) +#define PINMUX_BALL_D5_HET2_3 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_D5_SHIFT)) /* Pin D16 options */ -#define PINMUX_BALL_D16_EMIF_BA_1 (0x1 << PINMUX_BALL_D16_SHIFT) -#define PINMUX_BALL_D16_HET2_5 (0x2 << PINMUX_BALL_D16_SHIFT) +#define PINMUX_BALL_D16_EMIF_BA_1 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_D16_SHIFT)) +#define PINMUX_BALL_D16_HET2_5 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_D16_SHIFT)) /* Pin D17 options */ -#define PINMUX_BALL_D17_EMIF_nWE (0x1 << PINMUX_BALL_D17_SHIFT) -#define PINMUX_BALL_D17_EMIF_RNW (0x2 << PINMUX_BALL_D17_SHIFT) +#define PINMUX_BALL_D17_EMIF_nWE ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_D17_SHIFT)) +#define PINMUX_BALL_D17_EMIF_RNW ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_D17_SHIFT)) /* Pin D19 options */ -#define PINMUX_BALL_D19_HET1_10 (0x1 << PINMUX_BALL_D19_SHIFT) -#define PINMUX_BALL_D19_MII_TX_CLK (0x2 << PINMUX_BALL_D19_SHIFT) -#define PINMUX_BALL_D19_OHCI_RCFG_txEnL_0 (0x4 << PINMUX_BALL_D19_SHIFT) -#define PINMUX_BALL_D19_MII_TX_AVCLK4 (0x8 << PINMUX_BALL_D19_SHIFT) +#define PINMUX_BALL_D19_HET1_10 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_D19_SHIFT)) +#define PINMUX_BALL_D19_MII_TX_CLK ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_D19_SHIFT)) +#define PINMUX_BALL_D19_OHCI_RCFG_txEnL_0 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_D19_SHIFT)) +#define PINMUX_BALL_D19_MII_TX_AVCLK4 ((uint32_t)((uint32_t)0x8U << PINMUX_BALL_D19_SHIFT)) +#define PINMUX_BALL_D19_nTZ3 ((uint32_t)((uint32_t)0x10U << PINMUX_BALL_D19_SHIFT)) /* Pin E1 options */ -#define PINMUX_BALL_E1_GIOA_3 (0x1 << PINMUX_BALL_E1_SHIFT) -#define PINMUX_BALL_E1_HET2_2 (0x2 << PINMUX_BALL_E1_SHIFT) +#define PINMUX_BALL_E1_GIOA_3 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_E1_SHIFT)) +#define PINMUX_BALL_E1_HET2_02 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_E1_SHIFT)) /* Pin E3 options */ -#define PINMUX_BALL_E3_HET1_11 (0x1 << PINMUX_BALL_E3_SHIFT) -#define PINMUX_BALL_E3_MIBSPI3NCS_4 (0x2 << PINMUX_BALL_E3_SHIFT) -#define PINMUX_BALL_E3_HET2_18 (0x4 << PINMUX_BALL_E3_SHIFT) -#define PINMUX_BALL_E3_OHCI_PRT_OvrCurrent_1 (0x8 << PINMUX_BALL_E3_SHIFT) -#define PINMUX_BALL_E3_W2FC_VBUSI (0x10 << PINMUX_BALL_E3_SHIFT) - -/* Pin E5 options */ -#define PINMUX_BALL_E5_ETMDATA_20 (0x1 << PINMUX_BALL_E5_SHIFT) -#define PINMUX_BALL_E5_EMIF_DATA_4 (0x2 << PINMUX_BALL_E5_SHIFT) - -/* Pin E6 options */ -#define PINMUX_BALL_E6_ETMDATA_11 (0x1 << PINMUX_BALL_E6_SHIFT) -#define PINMUX_BALL_E6_EMIF_ADDR_2 (0x2 << PINMUX_BALL_E6_SHIFT) - -/* Pin E7 options */ -#define PINMUX_BALL_E7_ETMDATA_10 (0x1 << PINMUX_BALL_E7_SHIFT) -#define PINMUX_BALL_E7_EMIF_ADDR_3 (0x2 << PINMUX_BALL_E7_SHIFT) - -/* Pin E8 options */ -#define PINMUX_BALL_E8_ETMDATA_09 (0x1 << PINMUX_BALL_E8_SHIFT) -#define PINMUX_BALL_E8_EMIF_ADDR_4 (0x2 << PINMUX_BALL_E8_SHIFT) - -/* Pin E9 options */ -#define PINMUX_BALL_E9_ETMDATA_08 (0x1 << PINMUX_BALL_E9_SHIFT) -#define PINMUX_BALL_E9_EMIF_ADDR_5 (0x2 << PINMUX_BALL_E9_SHIFT) - -/* Pin E10 options */ -#define PINMUX_BALL_E10_ETMDATA_15 (0x1 << PINMUX_BALL_E10_SHIFT) -#define PINMUX_BALL_E10_EMIF_nDQM_0 (0x2 << PINMUX_BALL_E10_SHIFT) - -/* Pin E11 options */ -#define PINMUX_BALL_E11_ETMDATA_14 (0x1 << PINMUX_BALL_E11_SHIFT) -#define PINMUX_BALL_E11_EMIF_nDQM_1 (0x2 << PINMUX_BALL_E11_SHIFT) - -/* Pin E12 options */ -#define PINMUX_BALL_E12_ETMDATA_13 (0x1 << PINMUX_BALL_E12_SHIFT) -#define PINMUX_BALL_E12_EMIF_nOE (0x2 << PINMUX_BALL_E12_SHIFT) - -/* Pin E13 options */ -#define PINMUX_BALL_E13_ETMDATA_12 (0x1 << PINMUX_BALL_E13_SHIFT) -#define PINMUX_BALL_E13_EMIF_BA_0 (0x2 << PINMUX_BALL_E13_SHIFT) - -/* Pin E16 options */ -#define PINMUX_BALL_E16_MIBSPI5SIMO_1 (0x1 << PINMUX_BALL_E16_SHIFT) -#define PINMUX_BALL_E16_DMM_DATA_9 (0x2 << PINMUX_BALL_E16_SHIFT) - -/* Pin E17 options */ -#define PINMUX_BALL_E17_MIBSPI5SOMI_1 (0x1 << PINMUX_BALL_E17_SHIFT) -#define PINMUX_BALL_E17_DMM_DATA_13 (0x2 << PINMUX_BALL_E17_SHIFT) +#define PINMUX_BALL_E3_HET1_11 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_E3_SHIFT)) +#define PINMUX_BALL_E3_MIBSPI3NCS_4 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_E3_SHIFT)) +#define PINMUX_BALL_E3_HET2_18 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_E3_SHIFT)) +#define PINMUX_BALL_E3_OHCI_PRT_OvrCurrent_1 ((uint32_t)((uint32_t)0x8U << PINMUX_BALL_E3_SHIFT)) +#define PINMUX_BALL_E3_W2FC_VBUSI ((uint32_t)((uint32_t)0x10U << PINMUX_BALL_E3_SHIFT)) +#define PINMUX_BALL_E3_ETPWM1SYNCO ((uint32_t)((uint32_t)0x20U << PINMUX_BALL_E3_SHIFT)) /* Pin E18 options */ -#define PINMUX_BALL_E18_HET1_08 (0x1 << PINMUX_BALL_E18_SHIFT) -#define PINMUX_BALL_E18_MIBSPI1SIMO_1 (0x2 << PINMUX_BALL_E18_SHIFT) -#define PINMUX_BALL_E18_MII_TXD_3 (0x4 << PINMUX_BALL_E18_SHIFT) -#define PINMUX_BALL_E18_OHCI_PRT_OvrCurrent_0 (0x8 << PINMUX_BALL_E18_SHIFT) +#define PINMUX_BALL_E18_HET1_08 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_E18_SHIFT)) +#define PINMUX_BALL_E18_MIBSPI1SIMO_1 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_E18_SHIFT)) +#define PINMUX_BALL_E18_MII_TXD_3 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_E18_SHIFT)) +#define PINMUX_BALL_E18_OHCI_PRT_OvrCurrent_0 ((uint32_t)((uint32_t)0x8U << PINMUX_BALL_E18_SHIFT)) /* Pin E19 options */ -#define PINMUX_BALL_E19_MIBSPI5NCS_0 (0x1 << PINMUX_BALL_E19_SHIFT) -#define PINMUX_BALL_E19_DMM_DATA_5 (0x2 << PINMUX_BALL_E19_SHIFT) +#define PINMUX_BALL_E19_MIBSPI5NCS_0 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_E19_SHIFT)) +#define PINMUX_BALL_E19_ETPWM4A ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_E19_SHIFT)) /* Pin F3 options */ -#define PINMUX_BALL_F3_MIBSPI1NCS_1 (0x1 << PINMUX_BALL_F3_SHIFT) -#define PINMUX_BALL_F3_HET1_17 (0x2 << PINMUX_BALL_F3_SHIFT) -#define PINMUX_BALL_F3_MII_COL (0x4 << PINMUX_BALL_F3_SHIFT) -#define PINMUX_BALL_F3_OHCI_RCFG_suspend_0 (0x8 << PINMUX_BALL_F3_SHIFT) - -/* Pin F5 options */ -#define PINMUX_BALL_F5_ETMDATA_21 (0x1 << PINMUX_BALL_F5_SHIFT) -#define PINMUX_BALL_F5_EMIF_DATA_5 (0x2 << PINMUX_BALL_F5_SHIFT) +#define PINMUX_BALL_F3_MIBSPI1NCS_1 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_F3_SHIFT)) +#define PINMUX_BALL_F3_HET1_17 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_F3_SHIFT)) +#define PINMUX_BALL_F3_MII_COL ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_F3_SHIFT)) +#define PINMUX_BALL_F3_OHCI_RCFG_suspend_0 ((uint32_t)((uint32_t)0x8U << PINMUX_BALL_F3_SHIFT)) +#define PINMUX_BALL_F3_EQEP1S ((uint32_t)((uint32_t)0x10U << PINMUX_BALL_F3_SHIFT)) /* Pin G3 options */ -#define PINMUX_BALL_G3_MIBSPI1NCS_2 (0x1 << PINMUX_BALL_G3_SHIFT) -#define PINMUX_BALL_G3_HET1_19 (0x2 << PINMUX_BALL_G3_SHIFT) -#define PINMUX_BALL_G3_MDIO (0x4 << PINMUX_BALL_G3_SHIFT) - -/* Pin G5 options */ -#define PINMUX_BALL_G5_ETMDATA_22 (0x1 << PINMUX_BALL_G5_SHIFT) -#define PINMUX_BALL_G5_EMIF_DATA_6 (0x2 << PINMUX_BALL_G5_SHIFT) - -/* Pin G16 options */ -#define PINMUX_BALL_G16_MIBSPI5SOMI_3 (0x1 << PINMUX_BALL_G16_SHIFT) -#define PINMUX_BALL_G16_DMM_DATA_15 (0x2 << PINMUX_BALL_G16_SHIFT) - -/* Pin G17 options */ -#define PINMUX_BALL_G17_MIBSPI5SIMO_3 (0x1 << PINMUX_BALL_G17_SHIFT) -#define PINMUX_BALL_G17_DMM_DATA_11 (0x2 << PINMUX_BALL_G17_SHIFT) +#define PINMUX_BALL_G3_MIBSPI1NCS_2 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_G3_SHIFT)) +#define PINMUX_BALL_G3_HET1_19 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_G3_SHIFT)) +#define PINMUX_BALL_G3_MDIO ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_G3_SHIFT)) /* Pin G19 options */ -#define PINMUX_BALL_G19_MIBSPI1NENA (0x1 << PINMUX_BALL_G19_SHIFT) -#define PINMUX_BALL_G19_HET1_23 (0x2 << PINMUX_BALL_G19_SHIFT) -#define PINMUX_BALL_G19_MII_RXD_2 (0x4 << PINMUX_BALL_G19_SHIFT) -#define PINMUX_BALL_G19_OHCI_PRT_RcvDpls_0 (0x8 << PINMUX_BALL_G19_SHIFT) - -/* Pin H3 options */ -#define PINMUX_BALL_H3_GIOA_6 (0x1 << PINMUX_BALL_H3_SHIFT) -#define PINMUX_BALL_H3_HET2_4 (0x2 << PINMUX_BALL_H3_SHIFT) - -/* Pin H4 options */ -#define PINMUX_BALL_H4_HET1_21 (0x1 << PINMUX_BALL_H4_SHIFT) +#define PINMUX_BALL_G19_MIBSPI1NENA ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_G19_SHIFT)) +#define PINMUX_BALL_G19_HET1_23 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_G19_SHIFT)) +#define PINMUX_BALL_G19_MII_RXD_2 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_G19_SHIFT)) +#define PINMUX_BALL_G19_OHCI_PRT_RcvDpls_0 ((uint32_t)((uint32_t)0x8U << PINMUX_BALL_G19_SHIFT)) +#define PINMUX_BALL_G19_ECAP4 ((uint32_t)((uint32_t)0x10U << PINMUX_BALL_G19_SHIFT)) -/* Pin H16 options */ -#define PINMUX_BALL_H16_MIBSPI5SOMI_2 (0x1 << PINMUX_BALL_H16_SHIFT) -#define PINMUX_BALL_H16_DMM_DATA_14 (0x2 << PINMUX_BALL_H16_SHIFT) -/* Pin H17 options */ -#define PINMUX_BALL_H17_MIBSPI5SIMO_2 (0x1 << PINMUX_BALL_H17_SHIFT) -#define PINMUX_BALL_H17_DMM_DATA_10 (0x2 << PINMUX_BALL_H17_SHIFT) +/* Pin H3 options */ +#define PINMUX_BALL_H3_GIOA_6 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_H3_SHIFT)) +#define PINMUX_BALL_H3_HET2_04 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_H3_SHIFT)) +#define PINMUX_BALL_H3_ETPWM1B ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_H3_SHIFT)) /* Pin H18 options */ -#define PINMUX_BALL_H18_MIBSPI5NENA (0x1 << PINMUX_BALL_H18_SHIFT) -#define PINMUX_BALL_H18_DMM_DATA_7 (0x2 << PINMUX_BALL_H18_SHIFT) -#define PINMUX_BALL_H18_MII_RXD_3 (0x4 << PINMUX_BALL_H18_SHIFT) -#define PINMUX_BALL_H18_OHCI_PRT_RcvDmns_0 (0x8 << PINMUX_BALL_H18_SHIFT) +#define PINMUX_BALL_H18_MIBSPI5NENA ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_H18_SHIFT)) +#define PINMUX_BALL_H18_MII_RXD_3 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_H18_SHIFT)) +#define PINMUX_BALL_H18_OHCI_PRT_RcvDmns_0 ((uint32_t)((uint32_t)0x8U << PINMUX_BALL_H18_SHIFT)) +#define PINMUX_BALL_H18_MIBSPI5SOMI_1 ((uint32_t)((uint32_t)0x10U << PINMUX_BALL_H18_SHIFT)) +#define PINMUX_BALL_H18_ECAP5 ((uint32_t)((uint32_t)0x20U << PINMUX_BALL_H18_SHIFT)) /* Pin H19 options */ -#define PINMUX_BALL_H19_MIBSPI5CLK (0x1 << PINMUX_BALL_H19_SHIFT) -#define PINMUX_BALL_H19_DMM_DATA_4 (0x2 << PINMUX_BALL_H19_SHIFT) -#define PINMUX_BALL_H19_MII_TXEN (0x4 << PINMUX_BALL_H19_SHIFT) -#define PINMUX_BALL_H19_RMII_TXEN (0x8 << PINMUX_BALL_H19_SHIFT) - -/* Pin J3 options */ -#define PINMUX_BALL_J3_MIBSPI1NCS_3 (0x1 << PINMUX_BALL_J3_SHIFT) -#define PINMUX_BALL_J3_HET1_21 (0x2 << PINMUX_BALL_J3_SHIFT) +#define PINMUX_BALL_H19_MIBSPI5CLK ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_H19_SHIFT)) +#define PINMUX_BALL_H19_MII_TXEN ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_H19_SHIFT)) +#define PINMUX_BALL_H19_RMII_TXEN ((uint32_t)((uint32_t)0x8U << PINMUX_BALL_H19_SHIFT)) -/* Pin J4 options */ -#define PINMUX_BALL_J4_HET1_23 (0x1 << PINMUX_BALL_J4_SHIFT) +/* Pin J1 options */ +#define PINMUX_BALL_J1_HET1_18 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_J1_SHIFT)) +#define PINMUX_BALL_J1_ETPWM6A ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_J1_SHIFT)) -/* Pin J17 options */ -#define PINMUX_BALL_J17_HET1_31 (0x1 << PINMUX_BALL_J17_SHIFT) +/* Pin J3 options */ +#define PINMUX_BALL_J3_MIBSPI1NCS_3 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_J3_SHIFT)) +#define PINMUX_BALL_J3_HET1_21 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_J3_SHIFT)) /* Pin J18 options */ -#define PINMUX_BALL_J18_MIBSPI5SOMI_0 (0x1 << PINMUX_BALL_J18_SHIFT) -#define PINMUX_BALL_J18_DMM_DATA_12 (0x2 << PINMUX_BALL_J18_SHIFT) -#define PINMUX_BALL_J18_MII_TXD_0 (0x4 << PINMUX_BALL_J18_SHIFT) -#define PINMUX_BALL_J18_RMII_TXD_0 (0x8 << PINMUX_BALL_J18_SHIFT) +#define PINMUX_BALL_J18_MIBSPI5SOMI_0 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_J18_SHIFT)) +#define PINMUX_BALL_J18_MII_TXD_0 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_J18_SHIFT)) +#define PINMUX_BALL_J18_RMII_TXD_0 ((uint32_t)((uint32_t)0x8U << PINMUX_BALL_J18_SHIFT)) /* Pin J19 options */ -#define PINMUX_BALL_J19_MIBSPI5SIMO_0 (0x1 << PINMUX_BALL_J19_SHIFT) -#define PINMUX_BALL_J19_DMM_DATA_8 (0x2 << PINMUX_BALL_J19_SHIFT) -#define PINMUX_BALL_J19_MII_TXD_1 (0x4 << PINMUX_BALL_J19_SHIFT) -#define PINMUX_BALL_J19_RMII_TXD_1 (0x8 << PINMUX_BALL_J19_SHIFT) +#define PINMUX_BALL_J19_MIBSPI5SIMO_0 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_J19_SHIFT)) +#define PINMUX_BALL_J19_MII_TXD_1 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_J19_SHIFT)) +#define PINMUX_BALL_J19_RMII_TXD_1 ((uint32_t)((uint32_t)0x8U << PINMUX_BALL_J19_SHIFT)) +#define PINMUX_BALL_J19_MIBSPI5SOMI_2 ((uint32_t)((uint32_t)0x10U << PINMUX_BALL_J19_SHIFT)) /* Pin K2 options */ -#define PINMUX_BALL_K2_GIOB_1 (0x1 << PINMUX_BALL_K2_SHIFT) -#define PINMUX_BALL_K2_OHCI_RCFG_PrtPower_0 (0x2 << PINMUX_BALL_K2_SHIFT) - -/* Pin K5 options */ -#define PINMUX_BALL_K5_ETMDATA_23 (0x1 << PINMUX_BALL_K5_SHIFT) -#define PINMUX_BALL_K5_EMIF_DATA_7 (0x2 << PINMUX_BALL_K5_SHIFT) - -/* Pin K15 options */ -#define PINMUX_BALL_K15_ETMDATA_16 (0x1 << PINMUX_BALL_K15_SHIFT) -#define PINMUX_BALL_K15_EMIF_DATA_0 (0x2 << PINMUX_BALL_K15_SHIFT) +#define PINMUX_BALL_K2_GIOB_1 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_K2_SHIFT)) +#define PINMUX_BALL_K2_OHCI_RCFG_PrtPower_0 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_K2_SHIFT)) /* Pin K17 options */ -#define PINMUX_BALL_K17_EMIF_nCS_3 (0x1 << PINMUX_BALL_K17_SHIFT) -#define PINMUX_BALL_K17_RTP_DATA_14 (0x2 << PINMUX_BALL_K17_SHIFT) -#define PINMUX_BALL_K17_HET2_9 (0x4 << PINMUX_BALL_K17_SHIFT) +#define PINMUX_BALL_K17_EMIF_nCS_3 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_K17_SHIFT)) +#define PINMUX_BALL_K17_HET2_09 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_K17_SHIFT)) /* Pin K18 options */ -#define PINMUX_BALL_K18_HET1_0 (0x1 << PINMUX_BALL_K18_SHIFT) -#define PINMUX_BALL_K18_SPI4CLK (0x2 << PINMUX_BALL_K18_SHIFT) +#define PINMUX_BALL_K18_HET1_0 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_K18_SHIFT)) +#define PINMUX_BALL_K18_SPI4CLK ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_K18_SHIFT)) +#define PINMUX_BALL_K18_ETPWM2B ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_K18_SHIFT)) /* Pin K19 options */ -#define PINMUX_BALL_K19_HET1_28 (0x1 << PINMUX_BALL_K19_SHIFT) -#define PINMUX_BALL_K19_MII_RXCLK (0x2 << PINMUX_BALL_K19_SHIFT) -#define PINMUX_BALL_K19_RMII_REFCLK (0x4 << PINMUX_BALL_K19_SHIFT) -#define PINMUX_BALL_K19_MII_RX_AVCLK4 (0x8 << PINMUX_BALL_K19_SHIFT) - -/* Pin L5 options */ -#define PINMUX_BALL_L5_ETMDATA_24 (0x1 << PINMUX_BALL_L5_SHIFT) -#define PINMUX_BALL_L5_EMIF_DATA_8 (0x2 << PINMUX_BALL_L5_SHIFT) - -/* Pin L15 options */ -#define PINMUX_BALL_L15_ETMDATA_17 (0x1 << PINMUX_BALL_L15_SHIFT) -#define PINMUX_BALL_L15_EMIF_DATA_1 (0x2 << PINMUX_BALL_L15_SHIFT) +#define PINMUX_BALL_K19_HET1_28 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_K19_SHIFT)) +#define PINMUX_BALL_K19_MII_RXCLK ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_K19_SHIFT)) +#define PINMUX_BALL_K19_RMII_REFCLK ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_K19_SHIFT)) +#define PINMUX_BALL_K19_MII_RX_AVCLK4 ((uint32_t)((uint32_t)0x8U << PINMUX_BALL_K19_SHIFT)) /* Pin M1 options */ -#define PINMUX_BALL_M1_GIOA_7 (0x1 << PINMUX_BALL_M1_SHIFT) -#define PINMUX_BALL_M1_HET2_6 (0x2 << PINMUX_BALL_M1_SHIFT) +#define PINMUX_BALL_M1_GIOA_7 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_M1_SHIFT)) +#define PINMUX_BALL_M1_HET2_06 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_M1_SHIFT)) +#define PINMUX_BALL_M1_ETPWM2A ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_M1_SHIFT)) /* Pin M2 options */ -#define PINMUX_BALL_M2_GIOB_0 (0x1 << PINMUX_BALL_M2_SHIFT) -#define PINMUX_BALL_M2_OHCI_RCFG_txDpls_0 (0x2 << PINMUX_BALL_M2_SHIFT) - -/* Pin M3 options */ -#define PINMUX_BALL_M3_HET1_25 (0x1 << PINMUX_BALL_M3_SHIFT) - -/* Pin M5 options */ -#define PINMUX_BALL_M5_ETMDATA_25 (0x1 << PINMUX_BALL_M5_SHIFT) -#define PINMUX_BALL_M5_EMIF_DATA_9 (0x2 << PINMUX_BALL_M5_SHIFT) - -/* Pin M15 options */ -#define PINMUX_BALL_M15_ETMDATA_18 (0x1 << PINMUX_BALL_M15_SHIFT) -#define PINMUX_BALL_M15_EMIF_DATA_2 (0x2 << PINMUX_BALL_M15_SHIFT) - -/* Pin M17 options */ -#define PINMUX_BALL_M17_EMIF_nCS_4 (0x1 << PINMUX_BALL_M17_SHIFT) -#define PINMUX_BALL_M17_RTP_DATA_07 (0x2 << PINMUX_BALL_M17_SHIFT) +#define PINMUX_BALL_M2_GIOB_0 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_M2_SHIFT)) +#define PINMUX_BALL_M2_OHCI_RCFG_txDpls_0 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_M2_SHIFT)) /* Pin N1 options */ -#define PINMUX_BALL_N1_HET1_15 (0x1 << PINMUX_BALL_N1_SHIFT) -#define PINMUX_BALL_N1_MIBSPI1NCS_4 (0x2 << PINMUX_BALL_N1_SHIFT) +#define PINMUX_BALL_N1_HET1_15 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_N1_SHIFT)) +#define PINMUX_BALL_N1_MIBSPI1NCS_4 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_N1_SHIFT)) +#define PINMUX_BALL_N1_ECAP1 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_N1_SHIFT)) /* Pin N2 options */ -#define PINMUX_BALL_N2_HET1_13 (0x1 << PINMUX_BALL_N2_SHIFT) -#define PINMUX_BALL_N2_SCITX (0x2 << PINMUX_BALL_N2_SHIFT) - -/* Pin N5 options */ -#define PINMUX_BALL_N5_ETMDATA_26 (0x1 << PINMUX_BALL_N5_SHIFT) -#define PINMUX_BALL_N5_EMIF_DATA_10 (0x2 << PINMUX_BALL_N5_SHIFT) - -/* Pin N15 options */ -#define PINMUX_BALL_N15_ETMDATA_19 (0x1 << PINMUX_BALL_N15_SHIFT) -#define PINMUX_BALL_N15_EMIF_DATA_3 (0x2 << PINMUX_BALL_N15_SHIFT) +#define PINMUX_BALL_N2_HET1_13 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_N2_SHIFT)) +#define PINMUX_BALL_N2_SCITX ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_N2_SHIFT)) +#define PINMUX_BALL_N2_ETPWM5B ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_N2_SHIFT)) /* Pin N17 options */ -#define PINMUX_BALL_N17_EMIF_nCS_0 (0x1 << PINMUX_BALL_N17_SHIFT) -#define PINMUX_BALL_N17_RTP_DATA_15 (0x2 << PINMUX_BALL_N17_SHIFT) -#define PINMUX_BALL_N17_HET2_7 (0x4 << PINMUX_BALL_N17_SHIFT) +#define PINMUX_BALL_N17_EMIF_nCS_0 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_N17_SHIFT)) +#define PINMUX_BALL_N17_HET2_07 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_N17_SHIFT)) /* Pin N19 options */ -#define PINMUX_BALL_N19_AD1EVT (0x1 << PINMUX_BALL_N19_SHIFT) -#define PINMUX_BALL_N19_MII_RX_ER (0x2 << PINMUX_BALL_N19_SHIFT) -#define PINMUX_BALL_N19_RMII_RX_ER (0x4 << PINMUX_BALL_N19_SHIFT) +#define PINMUX_BALL_N19_AD1EVT ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_N19_SHIFT)) +#define PINMUX_BALL_N19_MII_RX_ER ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_N19_SHIFT)) +#define PINMUX_BALL_N19_RMII_RX_ER ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_N19_SHIFT)) /* Pin P1 options */ -#define PINMUX_BALL_P1_HET1_24 (0x1 << PINMUX_BALL_P1_SHIFT) -#define PINMUX_BALL_P1_MIBSPI1NCS_5 (0x2 << PINMUX_BALL_P1_SHIFT) -#define PINMUX_BALL_P1_MII_RXD_0 (0x4 << PINMUX_BALL_P1_SHIFT) -#define PINMUX_BALL_P1_RMII_RXD_0 (0x8 << PINMUX_BALL_P1_SHIFT) +#define PINMUX_BALL_P1_HET1_24 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_P1_SHIFT)) +#define PINMUX_BALL_P1_MIBSPI1NCS_5 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_P1_SHIFT)) +#define PINMUX_BALL_P1_MII_RXD_0 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_P1_SHIFT)) +#define PINMUX_BALL_P1_RMII_RXD_0 ((uint32_t)((uint32_t)0x8U << PINMUX_BALL_P1_SHIFT)) -/* Pin P5 options */ -#define PINMUX_BALL_P5_ETMDATA_27 (0x1 << PINMUX_BALL_P5_SHIFT) -#define PINMUX_BALL_P5_EMIF_DATA_11 (0x2 << PINMUX_BALL_P5_SHIFT) +/* Pin P2 options */ +#define PINMUX_BALL_P2_HET1_20 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_P2_SHIFT)) +#define PINMUX_BALL_P2_ETPWM6B ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_P2_SHIFT)) /* Pin R2 options */ -#define PINMUX_BALL_R2_MIBSPI1NCS_0 (0x1 << PINMUX_BALL_R2_SHIFT) -#define PINMUX_BALL_R2_MIBSPI1SOMI_1 (0x2 << PINMUX_BALL_R2_SHIFT) -#define PINMUX_BALL_R2_MII_TXD_2 (0x4 << PINMUX_BALL_R2_SHIFT) -#define PINMUX_BALL_R2_OHCI_PRT_RcvData_0 (0x8 << PINMUX_BALL_R2_SHIFT) - -/* Pin R5 options */ -#define PINMUX_BALL_R5_ETMDATA_28 (0x1 << PINMUX_BALL_R5_SHIFT) -#define PINMUX_BALL_R5_EMIF_DATA_12 (0x2 << PINMUX_BALL_R5_SHIFT) - -/* Pin R6 options */ -#define PINMUX_BALL_R6_ETMDATA_29 (0x1 << PINMUX_BALL_R6_SHIFT) -#define PINMUX_BALL_R6_EMIF_DATA_13 (0x2 << PINMUX_BALL_R6_SHIFT) - -/* Pin R7 options */ -#define PINMUX_BALL_R7_ETMDATA_30 (0x1 << PINMUX_BALL_R7_SHIFT) -#define PINMUX_BALL_R7_EMIF_DATA_14 (0x2 << PINMUX_BALL_R7_SHIFT) - -/* Pin R8 options */ -#define PINMUX_BALL_R8_ETMDATA_31 (0x1 << PINMUX_BALL_R8_SHIFT) -#define PINMUX_BALL_R8_EMIF_DATA_15 (0x2 << PINMUX_BALL_R8_SHIFT) - -/* Pin R9 options */ -#define PINMUX_BALL_R9_ETMTRACECLKIN (0x1 << PINMUX_BALL_R9_SHIFT) -#define PINMUX_BALL_R9_EXTCLKIN2 (0x2 << PINMUX_BALL_R9_SHIFT) +#define PINMUX_BALL_R2_MIBSPI1NCS_0 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_R2_SHIFT)) +#define PINMUX_BALL_R2_MIBSPI1SOMI_1 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_R2_SHIFT)) +#define PINMUX_BALL_R2_MII_TXD_2 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_R2_SHIFT)) +#define PINMUX_BALL_R2_OHCI_PRT_RcvData_0 ((uint32_t)((uint32_t)0x8U << PINMUX_BALL_R2_SHIFT)) +#define PINMUX_BALL_R2_ECAP6 ((uint32_t)((uint32_t)0x10U << PINMUX_BALL_R2_SHIFT)) /* Pin T1 options */ -#define PINMUX_BALL_T1_HET1_07 (0x1 << PINMUX_BALL_T1_SHIFT) -#define PINMUX_BALL_T1_OHCI_RCFG_PrtPower_1 (0x2 << PINMUX_BALL_T1_SHIFT) -#define PINMUX_BALL_T1_W2FC_GZO (0x4 << PINMUX_BALL_T1_SHIFT) -#define PINMUX_BALL_T1_HET2_14 (0x8 << PINMUX_BALL_T1_SHIFT) +#define PINMUX_BALL_T1_HET1_07 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_T1_SHIFT)) +#define PINMUX_BALL_T1_OHCI_RCFG_PrtPower_1 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_T1_SHIFT)) +#define PINMUX_BALL_T1_W2FC_GZO ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_T1_SHIFT)) +#define PINMUX_BALL_T1_HET2_14 ((uint32_t)((uint32_t)0x8U << PINMUX_BALL_T1_SHIFT)) +#define PINMUX_BALL_T1_ETPWM7B ((uint32_t)((uint32_t)0x10U << PINMUX_BALL_T1_SHIFT)) -/* Pin T12 options */ -#define PINMUX_BALL_T12_MIBSPI5NCS_3 (0x1 << PINMUX_BALL_T12_SHIFT) -#define PINMUX_BALL_T12_DMM_DATA_3 (0x2 << PINMUX_BALL_T12_SHIFT) /* Pin U1 options */ -#define PINMUX_BALL_U1_HET1_03 (0x1 << PINMUX_BALL_U1_SHIFT) -#define PINMUX_BALL_U1_SPI4NCS_0 (0x2 << PINMUX_BALL_U1_SHIFT) -#define PINMUX_BALL_U1_OHCI_RCFG_speed_1 (0x4 << PINMUX_BALL_U1_SHIFT) -#define PINMUX_BALL_U1_W2FC_PUENON (0x8 << PINMUX_BALL_U1_SHIFT) -#define PINMUX_BALL_U1_HET2_10 (0x10 << PINMUX_BALL_U1_SHIFT) +#define PINMUX_BALL_U1_HET1_03 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_U1_SHIFT)) +#define PINMUX_BALL_U1_SPI4NCS_0 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_U1_SHIFT)) +#define PINMUX_BALL_U1_OHCI_RCFG_speed_1 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_U1_SHIFT)) +#define PINMUX_BALL_U1_W2FC_PUENON ((uint32_t)((uint32_t)0x8U << PINMUX_BALL_U1_SHIFT)) +#define PINMUX_BALL_U1_HET2_10 ((uint32_t)((uint32_t)0x10U << PINMUX_BALL_U1_SHIFT)) +#define PINMUX_BALL_U1_EQEP2B ((uint32_t)((uint32_t)0x20U << PINMUX_BALL_U1_SHIFT)) /* Pin V2 options */ -#define PINMUX_BALL_V2_HET1_01 (0x1 << PINMUX_BALL_V2_SHIFT) -#define PINMUX_BALL_V2_SPI4NENA (0x2 << PINMUX_BALL_V2_SHIFT) -#define PINMUX_BALL_V2_OHCI_RCFG_txEnL_1 (0x4 << PINMUX_BALL_V2_SHIFT) -#define PINMUX_BALL_V2_W2FC_PUENO (0x8 << PINMUX_BALL_V2_SHIFT) -#define PINMUX_BALL_V2_HET2_8 (0x10 << PINMUX_BALL_V2_SHIFT) +#define PINMUX_BALL_V2_HET1_01 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_V2_SHIFT)) +#define PINMUX_BALL_V2_SPI4NENA ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_V2_SHIFT)) +#define PINMUX_BALL_V2_OHCI_RCFG_txEnL_1 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_V2_SHIFT)) +#define PINMUX_BALL_V2_W2FC_PUENO ((uint32_t)((uint32_t)0x8U << PINMUX_BALL_V2_SHIFT)) +#define PINMUX_BALL_V2_HET2_08 ((uint32_t)((uint32_t)0x10U << PINMUX_BALL_V2_SHIFT)) +#define PINMUX_BALL_V2_EQEP2A ((uint32_t)((uint32_t)0x20U << PINMUX_BALL_V2_SHIFT)) /* Pin V5 options */ -#define PINMUX_BALL_V5_MIBSPI3NCS_1 (0x1 << PINMUX_BALL_V5_SHIFT) -#define PINMUX_BALL_V5_HET1_25 (0x2 << PINMUX_BALL_V5_SHIFT) -#define PINMUX_BALL_V5_MDCLK (0x4 << PINMUX_BALL_V5_SHIFT) +#define PINMUX_BALL_V5_MIBSPI3NCS_1 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_V5_SHIFT)) +#define PINMUX_BALL_V5_HET1_25 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_V5_SHIFT)) +#define PINMUX_BALL_V5_MDCLK ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_V5_SHIFT)) /* Pin V6 options */ -#define PINMUX_BALL_V6_HET1_05 (0x1 << PINMUX_BALL_V6_SHIFT) -#define PINMUX_BALL_V6_SPI4SOMI (0x2 << PINMUX_BALL_V6_SHIFT) -#define PINMUX_BALL_V6_HET2_12 (0x4 << PINMUX_BALL_V6_SHIFT) +#define PINMUX_BALL_V6_HET1_05 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_V6_SHIFT)) +#define PINMUX_BALL_V6_SPI4SOMI ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_V6_SHIFT)) +#define PINMUX_BALL_V6_HET2_12 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_V6_SHIFT)) +#define PINMUX_BALL_V6_ETPWM3B ((uint32_t)((uint32_t)0x8U << PINMUX_BALL_V6_SHIFT)) /* Pin V7 options */ -#define PINMUX_BALL_V7_HET1_09 (0x1 << PINMUX_BALL_V7_SHIFT) -#define PINMUX_BALL_V7_HET2_16 (0x2 << PINMUX_BALL_V7_SHIFT) -#define PINMUX_BALL_V7_OHCI_RCFG_suspend_1 (0x4 << PINMUX_BALL_V7_SHIFT) -#define PINMUX_BALL_V7_W2FC_SUSPENDO (0x8 << PINMUX_BALL_V7_SHIFT) +#define PINMUX_BALL_V7_HET1_09 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_V7_SHIFT)) +#define PINMUX_BALL_V7_HET2_16 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_V7_SHIFT)) +#define PINMUX_BALL_V7_OHCI_RCFG_suspend_1 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_V7_SHIFT)) +#define PINMUX_BALL_V7_W2FC_SUSPENDO ((uint32_t)((uint32_t)0x8U << PINMUX_BALL_V7_SHIFT)) +#define PINMUX_BALL_V7_ETPWM7A ((uint32_t)((uint32_t)0x10U << PINMUX_BALL_V7_SHIFT)) + +/* Pin V8 options */ +#define PINMUX_BALL_V8_MIBSPI3SOMI ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_V8_SHIFT)) +#define PINMUX_BALL_V8_AWM_EXT_ENA ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_V8_SHIFT)) +#define PINMUX_BALL_V8_ECAP2 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_V8_SHIFT)) + +/* Pin V9 options */ +#define PINMUX_BALL_V9_MIBSPI3CLK ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_V9_SHIFT)) +#define PINMUX_BALL_V9_AWM_EXT_SEL_1 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_V9_SHIFT)) +#define PINMUX_BALL_V9_EQEP1A ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_V9_SHIFT)) /* Pin V10 options */ -#define PINMUX_BALL_V10_MIBSPI3NCS_0 (0x1 << PINMUX_BALL_V10_SHIFT) -#define PINMUX_BALL_V10_AD2EVT (0x2 << PINMUX_BALL_V10_SHIFT) -#define PINMUX_BALL_V10_GIOB_2 (0x4 << PINMUX_BALL_V10_SHIFT) +#define PINMUX_BALL_V10_MIBSPI3NCS_0 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_V10_SHIFT)) +#define PINMUX_BALL_V10_AD2EVT ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_V10_SHIFT)) +#define PINMUX_BALL_V10_GIOB_2 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_V10_SHIFT)) +#define PINMUX_BALL_V10_EQEP1I ((uint32_t)((uint32_t)0x8U << PINMUX_BALL_V10_SHIFT)) /* Pin W3 options */ -#define PINMUX_BALL_W3_HET1_06 (0x1 << PINMUX_BALL_W3_SHIFT) -#define PINMUX_BALL_W3_SCIRX (0x2 << PINMUX_BALL_W3_SHIFT) +#define PINMUX_BALL_W3_HET1_06 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_W3_SHIFT)) +#define PINMUX_BALL_W3_SCIRX ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_W3_SHIFT)) +#define PINMUX_BALL_W3_ETPWM5A ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_W3_SHIFT)) /* Pin W5 options */ -#define PINMUX_BALL_W5_HET1_02 (0x1 << PINMUX_BALL_W5_SHIFT) -#define PINMUX_BALL_W5_SPI4SIMO (0x2 << PINMUX_BALL_W5_SHIFT) +#define PINMUX_BALL_W5_HET1_02 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_W5_SHIFT)) +#define PINMUX_BALL_W5_SPI4SIMO ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_W5_SHIFT)) +#define PINMUX_BALL_W5_ETPWM3A ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_W5_SHIFT)) -/* Pin W6 options */ -#define PINMUX_BALL_W6_MIBSPI5NCS_2 (0x1 << PINMUX_BALL_W6_SHIFT) -#define PINMUX_BALL_W6_DMM_DATA_2 (0x2 << PINMUX_BALL_W6_SHIFT) +/* Pin W8 options */ +#define PINMUX_BALL_W8_MIBSPI3SIMO ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_W8_SHIFT)) +#define PINMUX_BALL_W8_AWM_EXT_SEL_0 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_W8_SHIFT)) +#define PINMUX_BALL_W8_ECAP3 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_W8_SHIFT)) /* Pin W9 options */ -#define PINMUX_BALL_W9_MIBSPI3NENA (0x1 << PINMUX_BALL_W9_SHIFT) -#define PINMUX_BALL_W9_MIBSPI3NCS_5 (0x2 << PINMUX_BALL_W9_SHIFT) -#define PINMUX_BALL_W9_HET1_31 (0x4 << PINMUX_BALL_W9_SHIFT) +#define PINMUX_BALL_W9_MIBSPI3NENA ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_W9_SHIFT)) +#define PINMUX_BALL_W9_MIBSPI3NCS_5 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_W9_SHIFT)) +#define PINMUX_BALL_W9_HET1_31 ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_W9_SHIFT)) +#define PINMUX_BALL_W9_EQEP1B ((uint32_t)((uint32_t)0x8U << PINMUX_BALL_W9_SHIFT)) /* Pin W10 options */ -#define PINMUX_BALL_W10_GIOB_3 (0x1 << PINMUX_BALL_W10_SHIFT) -#define PINMUX_BALL_W10_OHCI_PRT_RcvData_1 (0x2 << PINMUX_BALL_W10_SHIFT) -#define PINMUX_BALL_W10_W2FC_RXDI (0x4 << PINMUX_BALL_W10_SHIFT) - -#define PINMUX_GATE_EMIF_CLK (0x0 << PINMUX_GATE_EMIF_CLK_SHIFT) /**/ -#define PINMUX_GIOB_DISABLE_HET2_ON (0x1 << PINMUX_GIOB_DISABLE_HET2_SHIFT) -#define PINMUX_GIOB_DISABLE_HET2_OFF (0x0 << PINMUX_GIOB_DISABLE_HET2_SHIFT) -#define PINMUX_ALT_ADC_TRIGGER_1 (0x1 << PINMUX_ALT_ADC_TRIGGER_SHIFT) -#define PINMUX_ALT_ADC_TRIGGER_2 (0x2 << PINMUX_ALT_ADC_TRIGGER_SHIFT) -#define PINMUX_ETHERNET_MII (0x0 << PINMUX_ETHERNET_SHIFT) -#define PINMUX_ETHERNET_RMII (0x1 << PINMUX_ETHERNET_SHIFT) - -/** @struct pinMuxKicker -* @brief Pin Muxing Kicker Register Definition -* -* This structure is used to access the Pin Muxing Kicker registers. -*/ -typedef volatile struct pinMuxKicker +#define PINMUX_BALL_W10_GIOB_3 ((uint32_t)((uint32_t)0x1U << PINMUX_BALL_W10_SHIFT)) +#define PINMUX_BALL_W10_OHCI_PRT_RcvData_1 ((uint32_t)((uint32_t)0x2U << PINMUX_BALL_W10_SHIFT)) +#define PINMUX_BALL_W10_W2FC_RXDI ((uint32_t)((uint32_t)0x4U << PINMUX_BALL_W10_SHIFT)) + +#define PINMUX_GATE_EMIF_CLK_ON ((uint32_t)((uint32_t)0x0U << PINMUX_GATE_EMIF_CLK_SHIFT)) +#define PINMUX_GIOB_DISABLE_HET2_ON ((uint32_t)((uint32_t)0x1U << PINMUX_GIOB_DISABLE_HET2_SHIFT)) +#define PINMUX_GATE_EMIF_CLK_OFF ((uint32_t)((uint32_t)0x1U << PINMUX_GATE_EMIF_CLK_SHIFT)) +#define PINMUX_GIOB_DISABLE_HET2_OFF ((uint32_t)((uint32_t)0x0U << PINMUX_GIOB_DISABLE_HET2_SHIFT)) +#define PINMUX_ALT_ADC_TRIGGER_1 ((uint32_t)((uint32_t)0x1U << PINMUX_ALT_ADC_TRIGGER_SHIFT)) +#define PINMUX_ALT_ADC_TRIGGER_2 ((uint32_t)((uint32_t)0x2U << PINMUX_ALT_ADC_TRIGGER_SHIFT)) +#define PINMUX_ETHERNET_MII ((uint32_t)((uint32_t)0x0U << PINMUX_ETHERNET_SHIFT)) +#define PINMUX_ETHERNET_RMII ((uint32_t)((uint32_t)0x1U << PINMUX_ETHERNET_SHIFT)) + +#define PINMUX_ETPWM1_EQEPERR12 ((uint32_t)((uint32_t)0x1U << PINMUX_ETPWM1_SHIFT)) +#define PINMUX_ETPWM1_EQEPERR1 ((uint32_t)((uint32_t)0x2U << PINMUX_ETPWM1_SHIFT)) +#define PINMUX_ETPWM1_EQEPERR2 ((uint32_t)((uint32_t)0x4U << PINMUX_ETPWM1_SHIFT)) +#define PINMUX_ETPWM2_EQEPERR12 ((uint32_t)((uint32_t)0x1U << PINMUX_ETPWM2_SHIFT)) +#define PINMUX_ETPWM2_EQEPERR1 ((uint32_t)((uint32_t)0x2U << PINMUX_ETPWM2_SHIFT)) +#define PINMUX_ETPWM2_EQEPERR2 ((uint32_t)((uint32_t)0x4U << PINMUX_ETPWM2_SHIFT)) +#define PINMUX_ETPWM3_EQEPERR12 ((uint32_t)((uint32_t)0x1U << PINMUX_ETPWM3_SHIFT)) +#define PINMUX_ETPWM3_EQEPERR1 ((uint32_t)((uint32_t)0x2U << PINMUX_ETPWM3_SHIFT)) +#define PINMUX_ETPWM3_EQEPERR2 ((uint32_t)((uint32_t)0x4U << PINMUX_ETPWM3_SHIFT)) +#define PINMUX_ETPWM4_EQEPERR12 ((uint32_t)((uint32_t)0x1U << PINMUX_ETPWM4_SHIFT)) +#define PINMUX_ETPWM4_EQEPERR1 ((uint32_t)((uint32_t)0x2U << PINMUX_ETPWM4_SHIFT)) +#define PINMUX_ETPWM4_EQEPERR2 ((uint32_t)((uint32_t)0x4U << PINMUX_ETPWM4_SHIFT)) +#define PINMUX_ETPWM5_EQEPERR12 ((uint32_t)((uint32_t)0x1U << PINMUX_ETPWM5_SHIFT)) +#define PINMUX_ETPWM5_EQEPERR1 ((uint32_t)((uint32_t)0x2U << PINMUX_ETPWM5_SHIFT)) +#define PINMUX_ETPWM5_EQEPERR2 ((uint32_t)((uint32_t)0x4U << PINMUX_ETPWM5_SHIFT)) +#define PINMUX_ETPWM6_EQEPERR12 ((uint32_t)((uint32_t)0x1U << PINMUX_ETPWM6_SHIFT)) +#define PINMUX_ETPWM6_EQEPERR1 ((uint32_t)((uint32_t)0x2U << PINMUX_ETPWM6_SHIFT)) +#define PINMUX_ETPWM6_EQEPERR2 ((uint32_t)((uint32_t)0x4U << PINMUX_ETPWM6_SHIFT)) +#define PINMUX_ETPWM7_EQEPERR12 ((uint32_t)((uint32_t)0x1U << PINMUX_ETPWM7_SHIFT)) +#define PINMUX_ETPWM7_EQEPERR1 ((uint32_t)((uint32_t)0x2U << PINMUX_ETPWM7_SHIFT)) +#define PINMUX_ETPWM7_EQEPERR2 ((uint32_t)((uint32_t)0x4U << PINMUX_ETPWM7_SHIFT)) +#define PINMUX_ETPWM_TIME_BASE_SYNC_ON ((uint32_t)((uint32_t)0x2U << PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT)) +#define PINMUX_ETPWM_TBCLK_SYNC_ON ((uint32_t)((uint32_t)0x2U << PINMUX_ETPWM_TBCLK_SYNC_SHIFT)) +#define PINMUX_ETPWM_TIME_BASE_SYNC_OFF ((uint32_t)((uint32_t)0x0U << PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT)) +#define PINMUX_ETPWM_TBCLK_SYNC_OFF ((uint32_t)((uint32_t)0x0U << PINMUX_ETPWM_TBCLK_SYNC_SHIFT)) +#define PINMUX_TZ1_ASYNC ((uint32_t)((uint32_t)0x1U << PINMUX_TZ1_SHIFT)) +#define PINMUX_TZ1_SYNC ((uint32_t)((uint32_t)0x2U << PINMUX_TZ1_SHIFT)) +#define PINMUX_TZ1_FILTERED ((uint32_t)((uint32_t)0x4U << PINMUX_TZ1_SHIFT)) +#define PINMUX_TZ2_ASYNC ((uint32_t)((uint32_t)0x1U << PINMUX_TZ2_SHIFT)) +#define PINMUX_TZ2_SYNC ((uint32_t)((uint32_t)0x2U << PINMUX_TZ2_SHIFT)) +#define PINMUX_TZ2_FILTERED ((uint32_t)((uint32_t)0x4U << PINMUX_TZ2_SHIFT)) +#define PINMUX_TZ3_ASYNC ((uint32_t)((uint32_t)0x1U << PINMUX_TZ3_SHIFT)) +#define PINMUX_TZ3_SYNC ((uint32_t)((uint32_t)0x2U << PINMUX_TZ3_SHIFT)) +#define PINMUX_TZ3_FILTERED ((uint32_t)((uint32_t)0x4U << PINMUX_TZ3_SHIFT)) +#define PINMUX_EPWM1SYNCI_ASYNC ((uint32_t)((uint32_t)0x1U << PINMUX_EPWM1SYNCI_SHIFT)) +#define PINMUX_EPWM1SYNCI_SYNC ((uint32_t)((uint32_t)0x2U << PINMUX_EPWM1SYNCI_SHIFT)) +#define PINMUX_EPWM1SYNCI_FILTERED ((uint32_t)((uint32_t)0x4U << PINMUX_EPWM1SYNCI_SHIFT)) + +typedef struct pinmux_config_reg { - uint32_t KICKER0; /* kicker 0 register */ - uint32_t KICKER1; /* kicker 1 register */ -} pinMuxKICKER_t; - -/** @struct pinMuxBase -* @brief PINMUX Register Definition + uint32_t CONFIG_PINMMR0; + uint32_t CONFIG_PINMMR1; + uint32_t CONFIG_PINMMR2; + uint32_t CONFIG_PINMMR3; + uint32_t CONFIG_PINMMR4; + uint32_t CONFIG_PINMMR5; + uint32_t CONFIG_PINMMR6; + uint32_t CONFIG_PINMMR7; + uint32_t CONFIG_PINMMR8; + uint32_t CONFIG_PINMMR9; + uint32_t CONFIG_PINMMR10; + uint32_t CONFIG_PINMMR11; + uint32_t CONFIG_PINMMR12; + uint32_t CONFIG_PINMMR13; + uint32_t CONFIG_PINMMR14; + uint32_t CONFIG_PINMMR15; + uint32_t CONFIG_PINMMR16; + uint32_t CONFIG_PINMMR17; + uint32_t CONFIG_PINMMR18; + uint32_t CONFIG_PINMMR19; + uint32_t CONFIG_PINMMR20; + uint32_t CONFIG_PINMMR21; + uint32_t CONFIG_PINMMR22; + uint32_t CONFIG_PINMMR23; + uint32_t CONFIG_PINMMR24; + uint32_t CONFIG_PINMMR25; + uint32_t CONFIG_PINMMR26; + uint32_t CONFIG_PINMMR27; + uint32_t CONFIG_PINMMR28; + uint32_t CONFIG_PINMMR29; + uint32_t CONFIG_PINMMR30; + uint32_t CONFIG_PINMMR31; + uint32_t CONFIG_PINMMR32; + uint32_t CONFIG_PINMMR33; + uint32_t CONFIG_PINMMR34; + uint32_t CONFIG_PINMMR35; + uint32_t CONFIG_PINMMR36; + uint32_t CONFIG_PINMMR37; + uint32_t CONFIG_PINMMR38; + uint32_t CONFIG_PINMMR39; + uint32_t CONFIG_PINMMR40; + uint32_t CONFIG_PINMMR41; + uint32_t CONFIG_PINMMR42; + uint32_t CONFIG_PINMMR43; + uint32_t CONFIG_PINMMR44; + uint32_t CONFIG_PINMMR45; + uint32_t CONFIG_PINMMR46; + uint32_t CONFIG_PINMMR47; +}pinmux_config_reg_t; + +/** + * @defgroup IOMM IOMM + * @brief I/O Multiplexing and Control Module. + * + * The IOMM contains memory-mapped registers (MMR) that control device-specific multiplexed functions. + * The safety and diagnostic features of the IOMM are: + * - Kicker mechanism to protect the MMRs from accidental writes + * - Master-id checker to only allow the CPU to write to the MMRs + * - Error indication for access violations + * + * Related Files + * - reg_pinmux.h + * - pinmux.h + * - pinmux.c + * @addtogroup IOMM + * @{ + */ + +/** @fn void muxInit(void) +* @brief Initializes the PINMUX Driver * -* This structure is used to access the PINMUX module egisters. +* This function initializes the PINMUX module and configures the selected +* pinmux settings as per the user selection in the GUI */ -/** @typedef pinMuxBASE_t -* @brief PINMUX Register Frame Type Definition -* -* This type is used to access the PINMUX Registers. -*/ -typedef volatile struct pinMuxBase -{ - uint32_t PINMUX0; /**< 0xEB10 Pin Mux 0 register*/ - uint32_t PINMUX1; /**< 0xEB14 Pin Mux 1 register*/ - uint32_t PINMUX2; /**< 0xEB18 Pin Mux 2 register*/ - uint32_t PINMUX3; /**< 0xEB1C Pin Mux 3 register*/ - uint32_t PINMUX4; /**< 0xEB20 Pin Mux 4 register*/ - uint32_t PINMUX5; /**< 0xEB24 Pin Mux 5 register*/ - uint32_t PINMUX6; /**< 0xEB28 Pin Mux 6 register*/ - uint32_t PINMUX7; /**< 0xEB2C Pin Mux 7 register*/ - uint32_t PINMUX8; /**< 0xEB30 Pin Mux 8 register*/ - uint32_t PINMUX9; /**< 0xEB34 Pin Mux 9 register*/ - uint32_t PINMUX10; /**< 0xEB38 Pin Mux 10 register*/ - uint32_t PINMUX11; /**< 0xEB3C Pin Mux 11 register*/ - uint32_t PINMUX12; /**< 0xEB40 Pin Mux 12 register*/ - uint32_t PINMUX13; /**< 0xEB44 Pin Mux 13 register*/ - uint32_t PINMUX14; /**< 0xEB48 Pin Mux 14 register*/ - uint32_t PINMUX15; /**< 0xEB4C Pin Mux 15 register*/ - uint32_t PINMUX16; /**< 0xEB50 Pin Mux 16 register*/ - uint32_t PINMUX17; /**< 0xEB54 Pin Mux 17 register*/ - uint32_t PINMUX18; /**< 0xEB58 Pin Mux 18 register*/ - uint32_t PINMUX19; /**< 0xEB5C Pin Mux 19 register*/ - uint32_t PINMUX20; /**< 0xEB60 Pin Mux 20 register*/ - uint32_t PINMUX21; /**< 0xEB64 Pin Mux 21 register*/ - uint32_t PINMUX22; /**< 0xEB68 Pin Mux 22 register*/ - uint32_t PINMUX23; /**< 0xEB6C Pin Mux 23 register*/ - uint32_t PINMUX24; /**< 0xEB70 Pin Mux 24 register*/ - uint32_t PINMUX25; /**< 0xEB74 Pin Mux 25 register*/ - uint32_t PINMUX26; /**< 0xEB78 Pin Mux 26 register*/ - uint32_t PINMUX27; /**< 0xEB7C Pin Mux 27 register*/ - uint32_t PINMUX28; /**< 0xEB80 Pin Mux 28 register*/ - uint32_t PINMUX29; /**< 0xEB84 Pin Mux 29 register*/ - uint32_t PINMUX30; /**< 0xEB88 Pin Mux 30 register*/ - uint32_t PINMUX31; /**< 0xEB88 Pin Mux 31 register*/ - uint32_t PINMUX32; /**< 0xEB88 Pin Mux 32 register*/ - uint32_t PINMUX33; /**< 0xEB88 Pin Mux 33 register*/ - uint32_t PINMUX34; /**< 0xEB88 Pin Mux 34 register*/ -}pinMuxBASE_t; - - -/** @def kickerReg -* @brief Pin Muxing Kicker Register Frame Pointer -* -* This pointer is used to enable and disable muxing accross the device. -*/ -#define kickerReg ((pinMuxKICKER_t *) 0xFFFFEA38) - -/** @def pinMuxReg -* @brief Pin Muxing Control Register Frame Pointer -* -* This pointer is used to set the muxing registers accross the device. -*/ -#define pinMuxReg ((pinMuxBASE_t *) 0xFFFFEB10) - -/* PINMUX Interface Functions */ void muxInit(void); -void setMuxForIRC(int8_t irc, boolean_t enable); +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ #endif diff --git a/rpp/include/sys/reg_pinmux.h b/rpp/include/sys/reg_pinmux.h new file mode 100644 index 0000000..e1907bd --- /dev/null +++ b/rpp/include/sys/reg_pinmux.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2015 Czech Technical University in Prague + * + * Authors: + * - Michal Sojka + * + * This document contains proprietary information belonging to Czech + * Technical University in Prague. Passing on and copying of this + * document, and communication of its contents is not permitted + * without prior written authorization. + * + */ + +#ifndef SYS_REG_PINMUX_H +#define SYS_REG_PINMUX_H + +#if defined(TARGET_RM48_HDK) +#include "sys/_rm48_hdk/reg_pinmux.h" +#elif defined(TARGET_TMS570_HDK) +#include "sys/_tms570_hdk/reg_pinmux.h" +#elif defined(TARGET_TMS570_HYDCTR) +#include "sys/_tms570_hydctr/reg_pinmux.h" +#elif defined(TARGET_TMS570_RPP) +#include "sys/_tms570_rpp/reg_pinmux.h" +#else +#error No target specified! +#endif + + +#endif diff --git a/rpp/src/sys/_tms570_hydctr/sys_pinmux.c b/rpp/src/sys/_tms570_hydctr/sys_pinmux.c index 75d841d..1771a04 100644 --- a/rpp/src/sys/_tms570_hydctr/sys_pinmux.c +++ b/rpp/src/sys/_tms570_hydctr/sys_pinmux.c @@ -1,154 +1,278 @@ -/** @file pinmux.c +/** @file pinmux.c * @brief PINMUX Driver Implementation File -* @date 15.Mar.2012 -* @version 03.01.00 +* @date 15.July.2015 +* @version 04.05.00 * */ -/* (c) Texas Instruments 2009-2012, All rights reserved. */ +/* +* Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ -/* Include Files */ -#include "sys/_tms570_hydctr/sys_pinmux.h" +/* Include Files */ +#include "sys/system.h" +#include "sys/sys_pinmux.h" + +/*LDRA_INSPECTWINDOW 50 */ +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */ +/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */ +/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */ +/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */ +/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */ +/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */ +/*SAFETYMCUSW 76 S MR: 19.12 REVIEWED " Needs usage of multiple ## in the macro " */ #define PINMUX_SET(REG, BALLID, MUX) \ - pinMuxReg->PINMMR##REG = (pinMuxReg->PINMMR##REG & PINMUX_BALL_##BALLID##_MASK) | (PINMUX_BALL_##BALLID##_##MUX) + (pinMuxReg->PINMMR##REG = (pinMuxReg->PINMMR##REG & PINMUX_BALL_##BALLID##_MASK) | (PINMUX_BALL_##BALLID##_##MUX)) -#define PINMUX_GATE_EMIF_CLK_ENABLE \ - pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_GATE_EMIF_CLK_MASK) | PINMUX_GATE_EMIF_CLK +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_GATE_EMIF_CLK_ENABLE(state) \ + (pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_GATE_EMIF_CLK_MASK) | (PINMUX_GATE_EMIF_CLK_##state)) +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ #define PINMUX_GIOB_DISABLE_HET2_ENABLE(state) \ (pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_GIOB_DISABLE_HET2_MASK) | (PINMUX_GIOB_DISABLE_HET2_##state)) +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ #define PINMUX_ALT_ADC_TRIGGER_SELECT(num) \ - pinMuxReg->PINMMR30 = (pinMuxReg->PINMMR30 & PINMUX_ALT_ADC_TRIGGER_MASK) | (PINMUX_ALT_ADC_TRIGGER_##num) + (pinMuxReg->PINMMR30 = (pinMuxReg->PINMMR30 & PINMUX_ALT_ADC_TRIGGER_MASK) | (PINMUX_ALT_ADC_TRIGGER_##num)) +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ #define PINMUX_ETHERNET_SELECT(interface) \ - pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_ETHERNET_MASK) | (PINMUX_ETHERNET_##interface) + (pinMuxReg->PINMMR29 = (pinMuxReg->PINMMR29 & PINMUX_ETHERNET_MASK) | (PINMUX_ETHERNET_##interface)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM1_EQEPERR_ENABLE(interface) \ + (pinMuxReg->PINMMR41 = (pinMuxReg->PINMMR41 & PINMUX_ETPWM1_MASK) | (PINMUX_ETPWM1_##interface)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM2_EQEPERR_ENABLE(interface) \ + (pinMuxReg->PINMMR41 = (pinMuxReg->PINMMR41 & PINMUX_ETPWM2_MASK) | (PINMUX_ETPWM2_##interface)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM3_EQEPERR_ENABLE(interface) \ + (pinMuxReg->PINMMR41 = (pinMuxReg->PINMMR41 & PINMUX_ETPWM3_MASK) | (PINMUX_ETPWM3_##interface)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM4_EQEPERR_ENABLE(interface) \ + (pinMuxReg->PINMMR41 = (pinMuxReg->PINMMR41 & PINMUX_ETPWM4_MASK) | (PINMUX_ETPWM4_##interface)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM5_EQEPERR_ENABLE(interface) \ + (pinMuxReg->PINMMR42 = (pinMuxReg->PINMMR42 & PINMUX_ETPWM5_MASK) | (PINMUX_ETPWM5_##interface)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM6_EQEPERR_ENABLE(interface) \ + (pinMuxReg->PINMMR42 = (pinMuxReg->PINMMR42 & PINMUX_ETPWM6_MASK) | (PINMUX_ETPWM6_##interface)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM7_EQEPERR_ENABLE(interface) \ + (pinMuxReg->PINMMR42 = (pinMuxReg->PINMMR42 & PINMUX_ETPWM7_MASK) | (PINMUX_ETPWM7_##interface)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM_TZ1_ENABLE(interface) \ + (pinMuxReg->PINMMR46 = (pinMuxReg->PINMMR46 & PINMUX_TZ1_SHIFT) | (PINMUX_TZ1_##interface)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM_TZ2_ENABLE(interface) \ + (pinMuxReg->PINMMR46 = (pinMuxReg->PINMMR46 & PINMUX_TZ2_SHIFT) | (PINMUX_TZ2_##interface)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM_TZ3_ENABLE(interface) \ + (pinMuxReg->PINMMR47 = (pinMuxReg->PINMMR47 & PINMUX_TZ3_SHIFT) | (PINMUX_TZ3_##interface)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM_EPWM1SYNCI_ENABLE(interface) \ + (pinMuxReg->PINMMR47 = (pinMuxReg->PINMMR47 & PINMUX_EPWM1SYNCI_SHIFT) | (PINMUX_EPWM1SYNCI_##interface)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM_TIME_BASE_SYNC_ENABLE(state) \ + (pinMuxReg->PINMMR36 = (pinMuxReg->PINMMR36 & PINMUX_ETPWM_TIME_BASE_SYNC_MASK) | (PINMUX_ETPWM_TIME_BASE_SYNC_##state)) + +/*SAFETYMCUSW 125 S MR: 19.13 REVIEWED " Needs usage of ## in the macro " */ +/*SAFETYMCUSW 78 S MR: 19.10 REVIEWED " Macro parameter used for concatenation " */ +#define PINMUX_ETPWM_TBCLK_SYNC_ENABLE(state) \ + (pinMuxReg->PINMMR37 = (pinMuxReg->PINMMR37 & PINMUX_ETPWM_TBCLK_SYNC_MASK) | (PINMUX_ETPWM_TBCLK_SYNC_##state)) + + + + +/* SourceId : PINMUX_SourceId_001 */ +/* DesignId : PINMUX_DesignId_001 */ +/* Requirements : HL_SR325 */ void muxInit(void){ + /* Enable Pin Muxing */ - kickerReg->KICKER0 = 0x83E70B13; - kickerReg->KICKER1 = 0x95A4F1E0; + kickerReg->KICKER0 = 0x83E70B13U; + kickerReg->KICKER1 = 0x95A4F1E0U; + + + pinMuxReg->PINMMR0 = PINMUX_BALL_C3_HET1_29 | PINMUX_BALL_B2_HET1_27; + + pinMuxReg->PINMMR1 = PINMUX_BALL_E3_MIBSPI3NCS_4; + + pinMuxReg->PINMMR2 = PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5; - pinMuxReg->PINMMR0 = PINMUX_BALL_C3_I2C_SCL | PINMUX_BALL_B2_I2C_SDA; + pinMuxReg->PINMMR3 = PINMUX_BALL_B3_HET1_22 | PINMUX_BALL_H3_GIOA_6; - pinMuxReg->PINMMR1 = PINMUX_BALL_E3_MIBSPI3NCS_4; + pinMuxReg->PINMMR4 = PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_HET1_03; - pinMuxReg->PINMMR2 = PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_E1_GIOA_3 | (1 << 26) /* EPWM1A */; + pinMuxReg->PINMMR5 = PINMUX_BALL_K18_HET1_0 | PINMUX_BALL_W5_HET1_02 | PINMUX_BALL_V6_HET1_05; - pinMuxReg->PINMMR3 = (1 << 19) /* EPWM1B */; + pinMuxReg->PINMMR6 = PINMUX_BALL_T1_HET1_07 | PINMUX_BALL_V7_HET1_09; - pinMuxReg->PINMMR4 = (1 << 2) /* EPWM2A */ | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_HET1_03; + pinMuxReg->PINMMR7 = PINMUX_BALL_V5_MDCLK | PINMUX_BALL_W3_HET1_06; - pinMuxReg->PINMMR5 = (1 << 2) /* EPWM2B */ | (1 << 10) /* EPWM3A */ | (1 << 19) /* EPWM3B */; + pinMuxReg->PINMMR8 = PINMUX_BALL_N2_HET1_13 | PINMUX_BALL_G3_MIBSPI1NCS_2 | PINMUX_BALL_N1_HET1_15; - pinMuxReg->PINMMR6 = (1 << 4) /* EPWM7B */ | PINMUX_BALL_P5_EMIF_DATA_11 | (1 << 20) /* EPWM7A */; + pinMuxReg->PINMMR9 = ((~(pinMuxReg->PINMMR9 >> 18U) & 0x00000001U ) << 18U) | PINMUX_BALL_W9_MIBSPI3NCS_5 | PINMUX_BALL_V10_MIBSPI3NCS_0 | PINMUX_BALL_J3_HET1_21; - pinMuxReg->PINMMR7 = (1 << 18) /* EPWM5A */ | PINMUX_BALL_V5_MIBSPI3NCS_1; + pinMuxReg->PINMMR10 = PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_N17_EMIF_nCS_0; - pinMuxReg->PINMMR8 = PINMUX_BALL_G3_MIBSPI1NCS_2 | (1 << 18) /* ECAP1 */ | (1 << 2) /* EPWM5B */; + pinMuxReg->PINMMR11 = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_P1_HET1_24; - pinMuxReg->PINMMR9 = PINMUX_BALL_J3_MIBSPI1NCS_3 | PINMUX_BALL_W9_MIBSPI3NCS_5 | PINMUX_BALL_V10_MIBSPI3NCS_0; + pinMuxReg->PINMMR12 = PINMUX_BALL_A14_HET1_26 | PINMUX_BALL_G19_HET1_23 | PINMUX_BALL_H18_ECAP5; - pinMuxReg->PINMMR10 = PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_N17_EMIF_nCS_0; + pinMuxReg->PINMMR13 = PINMUX_BALL_J18_MIBSPI5SOMI_0 | PINMUX_BALL_J19_MIBSPI5SIMO_0 | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_R2_ECAP6; - pinMuxReg->PINMMR11 = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_P1_HET1_24; + pinMuxReg->PINMMR14 = PINMUX_BALL_E18_MIBSPI1SIMO_1 | PINMUX_BALL_K19_HET1_28 | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1; - pinMuxReg->PINMMR12 = PINMUX_BALL_A14_HET1_26 | (0x1 << 20) /* ECAP4 */ | (0x1 << 29) /* ECAP5 */; + pinMuxReg->PINMMR15 = 0x01010101U; - pinMuxReg->PINMMR13 = PINMUX_BALL_J18_MIBSPI5SOMI_0 | PINMUX_BALL_J19_MIBSPI5SIMO_0 | PINMUX_BALL_H19_MIBSPI5CLK | (0x1 << 28) /* ECAP6 */; + pinMuxReg->PINMMR16 = 0x01010101U; - pinMuxReg->PINMMR14 = PINMUX_BALL_E18_HET1_08 | PINMUX_BALL_K19_HET1_28 | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1; + pinMuxReg->PINMMR17 = PINMUX_BALL_D19_HET1_10 | PINMUX_BALL_B4_HET1_12; - pinMuxReg->PINMMR17 = PINMUX_BALL_D19_HET1_10 | PINMUX_BALL_B4_HET1_12; + pinMuxReg->PINMMR18 = 0x01010101U; - pinMuxReg->PINMMR19 = PINMUX_BALL_B11_HET1_30; + pinMuxReg->PINMMR19 = PINMUX_BALL_B11_HET1_30; - /* pin mutexed with N2HET1[17], which can (and by this implementation is) also be enabled on another ball - * through register PINMMR24[16]. - * - * On this ball there is a Sensor_Supply_1_En connected. To be able to enable the sensor, the HET pin has - * to be enabled on this ball and disabled on the other. But LED, connected to the other ball will not work. - */ - pinMuxReg->PINMMR20 = PINMUX_BALL_F3_MIBSPI1NCS_1; + pinMuxReg->PINMMR20 = PINMUX_BALL_F3_MIBSPI1NCS_1; - pinMuxReg->PINMMR21 = PINMUX_BALL_D5_EMIF_ADDR_1; + pinMuxReg->PINMMR21 = PINMUX_BALL_D5_EMIF_ADDR_1; - pinMuxReg->PINMMR22 = PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6 | (0x1 << 24) /* EMIF_ADDR_8 */; + pinMuxReg->PINMMR22 = PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6; pinMuxReg->PINMMR23 = ((~(pinMuxReg->PINMMR5 >> 1U) & 0x00000001U ) << 8U) | ((~(pinMuxReg->PINMMR5 >> 9U) & 0x00000001U ) << 16U) | ((~(pinMuxReg->PINMMR5 >> 17U) & 0x00000001U ) << 24U) | PINMUX_BALL_C6_EMIF_ADDR_8; - pinMuxReg->PINMMR24 = ((~(pinMuxReg->PINMMR4 >> 17U) & 0x00000001U ) << 0U) | ((~(pinMuxReg->PINMMR4 >> 25U) & 0x00000001U ) << 8U) | PINMUX_BALL_A13_HET1_17 | PINMUX_BALL_B13_HET1_19; + pinMuxReg->PINMMR24 = ((~(pinMuxReg->PINMMR20 >> 17U) & 0x00000001U ) << 16U) | ((~(pinMuxReg->PINMMR8 >> 9U) & 0x00000001U ) << 24U); - pinMuxReg->PINMMR25 = PINMUX_BALL_H4_HET1_21 | PINMUX_BALL_J4_HET1_23 | PINMUX_BALL_M3_HET1_25 | (1 << 24) /* N2HET1[27] */; + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + pinMuxReg->PINMMR25 = ((~(pinMuxReg->PINMMR9 >> 25U) & 0x00000001U ) << 0U) | ((~(pinMuxReg->PINMMR12 >> 17U) & 0x00000001U ) << 8U) | ((~(pinMuxReg->PINMMR7 >> 9U) & 0x00000001U ) << 16U) | ((~(pinMuxReg->PINMMR0 >> 26U) & 0x00000001U ) << 24U); - pinMuxReg->PINMMR26 = PINMUX_BALL_A3_HET1_29 | PINMUX_BALL_J17_HET1_31; + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + pinMuxReg->PINMMR26 = ((~(pinMuxReg->PINMMR0 >> 18U) & 0x00000001U ) << 0U) | ((~(pinMuxReg->PINMMR9 >> 10U) & 0x00000001U ) << 8U); - pinMuxReg->PINMMR27 = (1 << 2) /* EPWM4A */; + pinMuxReg->PINMMR27 = PINMUX_BALL_E19_MIBSPI5NCS_0; - pinMuxReg->PINMMR29 = PINMUX_BALL_D3_SPI2NENA | (1 << 16) /* GIOB[2] */; + pinMuxReg->PINMMR29 = PINMUX_BALL_D3_SPI2NCS_1; - pinMuxReg->PINMMR33 = (1 << 1) /* EPWM4B */ | (1 << 8) /* MIBSPI3SOMI[0] */ | (1 << 16) /* MIBSPI3SIMO[0] */ | (1 << 24) /* MIBSPI3CLK */; + pinMuxReg->PINMMR30 = 0x01010100U; - pinMuxReg->PINMMR34 = (1 << 0) /* N2HET1[16] */ | (1 << 9) /* EPWM6A */ | (1 << 17) /* EPWM6B */; + pinMuxReg->PINMMR31 = 0x01010101U; - PINMUX_GATE_EMIF_CLK_ENABLE; + pinMuxReg->PINMMR32 = 0x00010101U; + + pinMuxReg->PINMMR33 = PINMUX_BALL_B12_HET1_04 | PINMUX_BALL_V8_MIBSPI3SOMI | PINMUX_BALL_W8_MIBSPI3SIMO | PINMUX_BALL_V9_MIBSPI3CLK; + + pinMuxReg->PINMMR34 = PINMUX_BALL_A4_HET1_16 | PINMUX_BALL_J1_HET1_18 | PINMUX_BALL_P2_HET1_20; + + + PINMUX_GATE_EMIF_CLK_ENABLE(OFF); PINMUX_GIOB_DISABLE_HET2_ENABLE(OFF); PINMUX_ALT_ADC_TRIGGER_SELECT(1); PINMUX_ETHERNET_SELECT(RMII); + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + PINMUX_SET(0,A5,GIOA_0); + PINMUX_SET(18,A11,HET1_14); + PINMUX_SET(3,B3,HET1_22); + PINMUX_SET(1,C2,GIOA_1); + PINMUX_SET(21,K2,GIOB_1); + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + PINMUX_SET(0,W10,GIOB_3); + PINMUX_SET(18,M2,GIOB_0); + + + PINMUX_ETPWM1_EQEPERR_ENABLE(EQEPERR12); + PINMUX_ETPWM2_EQEPERR_ENABLE(EQEPERR12); + PINMUX_ETPWM3_EQEPERR_ENABLE(EQEPERR12); + PINMUX_ETPWM4_EQEPERR_ENABLE(EQEPERR12); + PINMUX_ETPWM5_EQEPERR_ENABLE(EQEPERR12); + PINMUX_ETPWM6_EQEPERR_ENABLE(EQEPERR12); + PINMUX_ETPWM7_EQEPERR_ENABLE(EQEPERR12); + PINMUX_ETPWM_TIME_BASE_SYNC_ENABLE(OFF); + PINMUX_ETPWM_TZ1_ENABLE(ASYNC); + PINMUX_ETPWM_TZ2_ENABLE(ASYNC); + PINMUX_ETPWM_TZ3_ENABLE(ASYNC); + PINMUX_ETPWM_EPWM1SYNCI_ENABLE(ASYNC); + + + /* Disable Pin Muxing */ kickerReg->KICKER0 = 0x00000000U; kickerReg->KICKER1 = 0x00000000U; /* Bit 31 of register GPREG1 is used to gate off the EMIF module outputs */ - systemREG1->GPREG1 |= 0x80000; -} - -/* - * This function explicitly enable/disable HET2 inputs for IRC module - * Parameters: irc - IRC number - * 1 for IRC is connected to DIN10 and DIN11 - * 2 for IRC is connected to DIN14 and DIN15 - * enable - TRUE for IRC, FALSE for normal usage as digital inputs - */ -void setMuxForIRC(int8_t irc, boolean_t enable) { - - /* Enable Pin Muxing */ - kickerReg->KICKER0 = 0x83E70B13; - kickerReg->KICKER1 = 0x95A4F1E0; - - if (enable) { - switch (irc) { - case 1: // set DIN10 and DIN11 to HET2 - PINMUX_SET(2,C1,HET2_0); - PINMUX_SET(2,E1,HET2_2); - break; - case 2: // set DIN14 and DIN15 to HET2 - PINMUX_SET(3,H3,HET2_4); - PINMUX_SET(4,M1,HET2_6); - break; - } - } else { - switch (irc) { - case 1: // set DIN10 and DIN11 back from HET2 - PINMUX_SET(2,C1,GIOA_2); - PINMUX_SET(2,E1,GIOA_3); - break; - case 2: // set DIN14 and DIN15 back from HET2 - PINMUX_SET(3,H3,GIOA_6); - PINMUX_SET(4,M1,GIOA_7); - break; - } - } + systemREG1->GPREG1 |= 0x80000000U; +} - /* Disable Pin Muxing */ - kickerReg->KICKER0 = 0x00000000; - kickerReg->KICKER1 = 0x00000000; - -}