From: Michal Sojka <sojkam1@fel.cvut.cz>
Date: Sat, 8 Aug 2015 15:57:43 +0000 (+0200)
Subject: Uncrustify
X-Git-Tag: eaton-0.5.5~9
X-Git-Url: http://rtime.felk.cvut.cz/gitweb/pes-rpp/rpp-lib.git/commitdiff_plain/49901f543393051038bf8dd7fb1cffb0ee9a7be8

Uncrustify
---

diff --git a/apps/rpp-test-suite/src/_tms570_rpp/main.c b/apps/rpp-test-suite/src/_tms570_rpp/main.c
index 36da690..59fa646 100644
--- a/apps/rpp-test-suite/src/_tms570_rpp/main.c
+++ b/apps/rpp-test-suite/src/_tms570_rpp/main.c
@@ -212,7 +212,7 @@ int main(void)
 
 	// Speed up the SCI
 	rpp_sci_setup(115200);
-	
+
 	// Spawn tasks
 	portBASE_TYPE task_created =
 		xTaskCreate(test_cmdproc,
diff --git a/rpp/include/base.h b/rpp/include/base.h
index d336374..749b2cd 100644
--- a/rpp/include/base.h
+++ b/rpp/include/base.h
@@ -52,7 +52,7 @@
 #define STATIC_ASSERT(COND,MSG) static_assert(COND, #MSG)
 #else
 /** Static assertion - non-C11 fall-back */
-#define STATIC_ASSERT(COND,MSG) typedef char static_assertion_##MSG[(COND)?1:-1]
+#define STATIC_ASSERT(COND,MSG) typedef char static_assertion_##MSG[(COND) ? 1 : -1]
 #endif
 
 #endif /* __BASE_H */
diff --git a/rpp/include/binary.h b/rpp/include/binary.h
index cccaa88..a72a8f0 100644
--- a/rpp/include/binary.h
+++ b/rpp/include/binary.h
@@ -146,7 +146,7 @@
  *      value = __insval2mfld(mask, value, 4);
  *  will change value into 0x1244;
  */
-#define __insval2mfld(mask, value, val) (__clrvalmsk(mask, value) |	\
+#define __insval2mfld(mask, value, val) (__clrvalmsk(mask, value) | \
 										 __val2mfld(mask,val))
 
 #endif /* __RPP_BINARY_H */
diff --git a/rpp/include/drv/_rm48_hdk/gio_def.h b/rpp/include/drv/_rm48_hdk/gio_def.h
index d76877b..74bd0ac 100644
--- a/rpp/include/drv/_rm48_hdk/gio_def.h
+++ b/rpp/include/drv/_rm48_hdk/gio_def.h
@@ -28,54 +28,54 @@
 /* Pin definition generators */
 
 /*              Name       Port Pin Configuration */
-GIO_PIN_DEF_GEN(GIOA0,	   GIOA, 0, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOA1,	   GIOA, 1, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOA2,	   GIOA, 2, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOA3,	   GIOA, 3, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOA4,	   GIOA, 4, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOA5,	   GIOA, 5, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOA6,	   GIOA, 6, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOA7,	   GIOA, 7, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOA0,     GIOA, 0, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOA1,     GIOA, 1, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOA2,     GIOA, 2, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOA3,     GIOA, 3, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOA4,     GIOA, 4, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOA5,     GIOA, 5, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOA6,     GIOA, 6, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOA7,     GIOA, 7, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
 
-GIO_PIN_DEF_GEN(GIOB0,	   GIOB, 0, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOB1,	   GIOB, 1, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOB2,	   GIOB, 2, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOB3,	   GIOB, 3, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOB4,	   GIOB, 4, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOB5,	   GIOB, 5, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOB6,	   GIOB, 6, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOB7,	   GIOB, 7, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOB0,     GIOB, 0, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOB1,     GIOB, 1, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOB2,     GIOB, 2, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOB3,     GIOB, 3, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOB4,     GIOB, 4, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOB5,     GIOB, 5, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOB6,     GIOB, 6, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOB7,     GIOB, 7, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
 
-GIO_PIN_DEF_GEN(NHET10,	   HET1,  0, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET11,	   HET1,  1, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET12,	   HET1,  2, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET13,	   HET1,  3, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET14,	   HET1,  4, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET15,	   HET1,  5, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET17,	   HET1,  7, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET18,	   HET1,  8, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET19,	   HET1,  9, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET110,	   HET1, 10, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET111,	   HET1, 11, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET112,	   HET1, 12, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET114,	   HET1, 14, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET115,	   HET1, 15, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET116,	   HET1, 16, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET117,	   HET1, 17, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET118,	   HET1, 18, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET119,	   HET1, 19, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET120,	   HET1, 20, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET121,	   HET1, 21, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET122,	   HET1, 22, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET123,	   HET1, 23, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET124,	   HET1, 24, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET125,	   HET1, 25, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET126,	   HET1, 26, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET127,	   HET1, 27, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET128,	   HET1, 28, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET129,	   HET1, 29, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET130,	   HET1, 30, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET131,	   HET1, 31, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET10,    HET1,  0, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET11,    HET1,  1, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET12,    HET1,  2, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET13,    HET1,  3, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET14,    HET1,  4, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET15,    HET1,  5, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET17,    HET1,  7, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET18,    HET1,  8, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET19,    HET1,  9, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET110,       HET1, 10, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET111,       HET1, 11, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET112,       HET1, 12, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET114,       HET1, 14, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET115,       HET1, 15, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET116,       HET1, 16, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET117,       HET1, 17, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET118,       HET1, 18, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET119,       HET1, 19, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET120,       HET1, 20, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET121,       HET1, 21, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET122,       HET1, 22, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET123,       HET1, 23, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET124,       HET1, 24, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET125,       HET1, 25, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET126,       HET1, 26, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET127,       HET1, 27, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET128,       HET1, 28, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET129,       HET1, 29, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET130,       HET1, 30, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET131,       HET1, 31, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
 
 #undef GIO_PIN_CONF_GPIO_OUT_HI_PD_PEN_ODOFF
 #undef GIO_PIN_CONF_GPIO_OUT_LO_PD_PEN_ODOFF
@@ -89,4 +89,3 @@ GIO_PIN_DEF_GEN(NHET131,	   HET1, 31, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
 #undef GIO_PIN_CONF_GPIO_IN_LO_PD_PDIS_ODOFF
 #undef GIO_PIN_CONF_GPIO_IN_LO_PD_PEN_ODOFF
 #undef GIO_PIN_CONF_GPIO_IN_LO_PU_PDIS_ODOFF
-
diff --git a/rpp/include/drv/_tms570_hdk/gio_def.h b/rpp/include/drv/_tms570_hdk/gio_def.h
index d76877b..74bd0ac 100644
--- a/rpp/include/drv/_tms570_hdk/gio_def.h
+++ b/rpp/include/drv/_tms570_hdk/gio_def.h
@@ -28,54 +28,54 @@
 /* Pin definition generators */
 
 /*              Name       Port Pin Configuration */
-GIO_PIN_DEF_GEN(GIOA0,	   GIOA, 0, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOA1,	   GIOA, 1, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOA2,	   GIOA, 2, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOA3,	   GIOA, 3, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOA4,	   GIOA, 4, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOA5,	   GIOA, 5, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOA6,	   GIOA, 6, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOA7,	   GIOA, 7, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOA0,     GIOA, 0, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOA1,     GIOA, 1, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOA2,     GIOA, 2, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOA3,     GIOA, 3, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOA4,     GIOA, 4, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOA5,     GIOA, 5, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOA6,     GIOA, 6, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOA7,     GIOA, 7, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
 
-GIO_PIN_DEF_GEN(GIOB0,	   GIOB, 0, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOB1,	   GIOB, 1, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOB2,	   GIOB, 2, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOB3,	   GIOB, 3, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOB4,	   GIOB, 4, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOB5,	   GIOB, 5, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOB6,	   GIOB, 6, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOB7,	   GIOB, 7, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOB0,     GIOB, 0, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOB1,     GIOB, 1, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOB2,     GIOB, 2, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOB3,     GIOB, 3, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOB4,     GIOB, 4, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOB5,     GIOB, 5, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOB6,     GIOB, 6, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOB7,     GIOB, 7, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
 
-GIO_PIN_DEF_GEN(NHET10,	   HET1,  0, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET11,	   HET1,  1, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET12,	   HET1,  2, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET13,	   HET1,  3, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET14,	   HET1,  4, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET15,	   HET1,  5, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET17,	   HET1,  7, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET18,	   HET1,  8, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET19,	   HET1,  9, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET110,	   HET1, 10, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET111,	   HET1, 11, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET112,	   HET1, 12, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET114,	   HET1, 14, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET115,	   HET1, 15, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET116,	   HET1, 16, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET117,	   HET1, 17, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET118,	   HET1, 18, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET119,	   HET1, 19, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET120,	   HET1, 20, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET121,	   HET1, 21, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET122,	   HET1, 22, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET123,	   HET1, 23, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET124,	   HET1, 24, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET125,	   HET1, 25, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET126,	   HET1, 26, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET127,	   HET1, 27, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET128,	   HET1, 28, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET129,	   HET1, 29, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET130,	   HET1, 30, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET131,	   HET1, 31, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET10,    HET1,  0, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET11,    HET1,  1, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET12,    HET1,  2, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET13,    HET1,  3, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET14,    HET1,  4, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET15,    HET1,  5, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET17,    HET1,  7, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET18,    HET1,  8, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET19,    HET1,  9, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET110,       HET1, 10, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET111,       HET1, 11, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET112,       HET1, 12, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET114,       HET1, 14, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET115,       HET1, 15, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET116,       HET1, 16, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET117,       HET1, 17, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET118,       HET1, 18, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET119,       HET1, 19, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET120,       HET1, 20, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET121,       HET1, 21, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET122,       HET1, 22, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET123,       HET1, 23, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET124,       HET1, 24, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET125,       HET1, 25, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET126,       HET1, 26, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET127,       HET1, 27, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET128,       HET1, 28, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET129,       HET1, 29, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET130,       HET1, 30, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET131,       HET1, 31, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
 
 #undef GIO_PIN_CONF_GPIO_OUT_HI_PD_PEN_ODOFF
 #undef GIO_PIN_CONF_GPIO_OUT_LO_PD_PEN_ODOFF
@@ -89,4 +89,3 @@ GIO_PIN_DEF_GEN(NHET131,	   HET1, 31, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
 #undef GIO_PIN_CONF_GPIO_IN_LO_PD_PDIS_ODOFF
 #undef GIO_PIN_CONF_GPIO_IN_LO_PD_PEN_ODOFF
 #undef GIO_PIN_CONF_GPIO_IN_LO_PU_PDIS_ODOFF
-
diff --git a/rpp/include/drv/_tms570_hydctr/gio_def.h b/rpp/include/drv/_tms570_hydctr/gio_def.h
index d76877b..74bd0ac 100644
--- a/rpp/include/drv/_tms570_hydctr/gio_def.h
+++ b/rpp/include/drv/_tms570_hydctr/gio_def.h
@@ -28,54 +28,54 @@
 /* Pin definition generators */
 
 /*              Name       Port Pin Configuration */
-GIO_PIN_DEF_GEN(GIOA0,	   GIOA, 0, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOA1,	   GIOA, 1, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOA2,	   GIOA, 2, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOA3,	   GIOA, 3, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOA4,	   GIOA, 4, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOA5,	   GIOA, 5, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOA6,	   GIOA, 6, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOA7,	   GIOA, 7, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOA0,     GIOA, 0, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOA1,     GIOA, 1, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOA2,     GIOA, 2, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOA3,     GIOA, 3, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOA4,     GIOA, 4, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOA5,     GIOA, 5, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOA6,     GIOA, 6, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOA7,     GIOA, 7, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
 
-GIO_PIN_DEF_GEN(GIOB0,	   GIOB, 0, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOB1,	   GIOB, 1, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOB2,	   GIOB, 2, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOB3,	   GIOB, 3, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOB4,	   GIOB, 4, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOB5,	   GIOB, 5, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOB6,	   GIOB, 6, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(GIOB7,	   GIOB, 7, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOB0,     GIOB, 0, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOB1,     GIOB, 1, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOB2,     GIOB, 2, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOB3,     GIOB, 3, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOB4,     GIOB, 4, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOB5,     GIOB, 5, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOB6,     GIOB, 6, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(GIOB7,     GIOB, 7, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
 
-GIO_PIN_DEF_GEN(NHET10,	   HET1,  0, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET11,	   HET1,  1, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET12,	   HET1,  2, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET13,	   HET1,  3, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET14,	   HET1,  4, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET15,	   HET1,  5, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET17,	   HET1,  7, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET18,	   HET1,  8, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET19,	   HET1,  9, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET110,	   HET1, 10, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET111,	   HET1, 11, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET112,	   HET1, 12, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET114,	   HET1, 14, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET115,	   HET1, 15, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET116,	   HET1, 16, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET117,	   HET1, 17, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET118,	   HET1, 18, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET119,	   HET1, 19, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET120,	   HET1, 20, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET121,	   HET1, 21, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET122,	   HET1, 22, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET123,	   HET1, 23, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET124,	   HET1, 24, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET125,	   HET1, 25, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET126,	   HET1, 26, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET127,	   HET1, 27, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET128,	   HET1, 28, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET129,	   HET1, 29, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET130,	   HET1, 30, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
-GIO_PIN_DEF_GEN(NHET131,	   HET1, 31, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET10,    HET1,  0, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET11,    HET1,  1, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET12,    HET1,  2, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET13,    HET1,  3, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET14,    HET1,  4, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET15,    HET1,  5, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET17,    HET1,  7, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET18,    HET1,  8, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET19,    HET1,  9, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET110,       HET1, 10, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET111,       HET1, 11, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET112,       HET1, 12, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET114,       HET1, 14, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET115,       HET1, 15, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET116,       HET1, 16, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET117,       HET1, 17, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET118,       HET1, 18, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET119,       HET1, 19, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET120,       HET1, 20, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET121,       HET1, 21, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET122,       HET1, 22, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET123,       HET1, 23, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET124,       HET1, 24, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET125,       HET1, 25, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET126,       HET1, 26, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET127,       HET1, 27, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET128,       HET1, 28, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET129,       HET1, 29, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET130,       HET1, 30, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
+GIO_PIN_DEF_GEN(NHET131,       HET1, 31, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
 
 #undef GIO_PIN_CONF_GPIO_OUT_HI_PD_PEN_ODOFF
 #undef GIO_PIN_CONF_GPIO_OUT_LO_PD_PEN_ODOFF
@@ -89,4 +89,3 @@ GIO_PIN_DEF_GEN(NHET131,	   HET1, 31, GIO_PIN_CONF_GPIO_OUT_LO_PU_PEN_ODOFF)
 #undef GIO_PIN_CONF_GPIO_IN_LO_PD_PDIS_ODOFF
 #undef GIO_PIN_CONF_GPIO_IN_LO_PD_PEN_ODOFF
 #undef GIO_PIN_CONF_GPIO_IN_LO_PU_PDIS_ODOFF
-
diff --git a/rpp/include/drv/_tms570_rpp/port_def.h b/rpp/include/drv/_tms570_rpp/port_def.h
index 5d61d45..279d55e 100644
--- a/rpp/include/drv/_tms570_rpp/port_def.h
+++ b/rpp/include/drv/_tms570_rpp/port_def.h
@@ -44,4 +44,4 @@ static double port_adc_lsb2volts(uint16_t lsb)
 	return ((double)lsb + 0.0)*2.5/4095*10;
 }
 
-#endif
+#endif /* ifndef _TMS570_RPP_PORT_DEF_H */
diff --git a/rpp/include/drv/gio_names.h b/rpp/include/drv/gio_names.h
index 7e6fdbc..58db1e5 100644
--- a/rpp/include/drv/gio_names.h
+++ b/rpp/include/drv/gio_names.h
@@ -3,9 +3,9 @@
 
 enum pin_name {
 
-    #define GIO_PIN_DEF_GEN(name, port, pin, conf) PIN_##name,
-    #include "drv/gio_def.h"
-    #undef GIO_PIN_DEF_GEN
+	#define GIO_PIN_DEF_GEN(name, port, pin, conf) PIN_##name,
+	#include "drv/gio_def.h"
+	#undef GIO_PIN_DEF_GEN
 
 	_PIN_COUNT,
 	_PIN_INVALID = -1
diff --git a/rpp/include/drv/gio_tab.h b/rpp/include/drv/gio_tab.h
index 3d07a2a..db303b6 100644
--- a/rpp/include/drv/gio_tab.h
+++ b/rpp/include/drv/gio_tab.h
@@ -19,8 +19,8 @@
 #include "drv/port.h"
 
 struct gio_pin {
-	const char *pin_name;	// Pin name
-	uint32_t pin_dsc;		// Pin descriptor computed with GIO_PIN_DESC
+	const char *pin_name;   // Pin name
+	uint32_t pin_dsc;       // Pin descriptor computed with GIO_PIN_DESC
 };
 
 extern const struct gio_pin gio_table[_PIN_COUNT];
@@ -30,12 +30,12 @@ extern const struct gio_pin gio_table[_PIN_COUNT];
  * arithmetic operations like (PIN_DIN8 + 1). The enum is used in the
  * rpp layer, where it protects users from doing stupid things.
  */
-static inline void gio_tab_set(/* enum pin_name */int pin, boolean_t val)
+static inline void gio_tab_set(/* enum pin_name */ int pin, boolean_t val)
 {
 	gio_set(gio_table[pin].pin_dsc, val);
 }
 
-static inline boolean_t gio_tab_get(/* enum pin_name */int pin)
+static inline boolean_t gio_tab_get(/* enum pin_name */ int pin)
 {
 	return gio_get(gio_table[pin].pin_dsc);
 }
diff --git a/rpp/include/drv/port.h b/rpp/include/drv/port.h
index 892b76c..f793b3b 100644
--- a/rpp/include/drv/port.h
+++ b/rpp/include/drv/port.h
@@ -40,8 +40,8 @@
  */
 struct port_desc {
 	char *name;
-	uint16_t numchn;			/**< Number of channels/pins */
-	uint16_t bpch;				/**< Bits per channel */
+	uint16_t numchn;            /**< Number of channels/pins */
+	uint16_t bpch;              /**< Bits per channel */
 	/**
 	 * Getter function. If NULL, the port is write only. All SPI ports
 	 * are write only, because a command has to be sent to obtain an
@@ -73,8 +73,8 @@ struct port_desc {
 			enum pin_name *pins;
 		} gioset;
 		struct {
-			uint8_t ifc;		/**< SPI interface */
-			uint8_t cs;			/**< SPI chipselect */
+			uint8_t ifc;        /**< SPI interface */
+			uint8_t cs;         /**< SPI chipselect */
 		} spi;
 		struct {
 			adcBASE_t *reg;
@@ -86,4 +86,4 @@ struct port_desc {
 
 extern const struct port_desc port_desc[_PORT_COUNT];
 
-#endif
+#endif /* ifndef DRV_PORT_H */
diff --git a/rpp/include/rpp/gio.h b/rpp/include/rpp/gio.h
index fd832f8..a5edd60 100644
--- a/rpp/include/rpp/gio.h
+++ b/rpp/include/rpp/gio.h
@@ -30,7 +30,7 @@ int8_t rpp_gio_get(enum pin_name pin);
 
 /** GIO pin input mode */
 enum rpp_gio_in_mode {
-	RPP_GIO_MODE_PULLDIS,		/**< Disable pull resistor */
+	RPP_GIO_MODE_PULLDIS,       /**< Disable pull resistor */
 	RPP_GIO_MODE_PULLUP,
 	RPP_GIO_MODE_PULLDOWN,
 };
@@ -47,9 +47,9 @@ enum rpp_gio_io {
  * @param pin Pin to configure
  * @param io Configure the pin as input or output.
  * @param in_mode Input settings. Ignored when pin is configured as
- * 		  		  output.
+ *                output.
  * @param open_drain Output is open drain when TRUE, pull/push when
- * 		  			 FALSE. Ignored when pin is configured as input.
+ *                   FALSE. Ignored when pin is configured as input.
  *
  * @return SUCCESS or FAILURE.
  */
diff --git a/rpp/include/rpp/rpp.h b/rpp/include/rpp/rpp.h
index 3ad6e54..37ae7a9 100644
--- a/rpp/include/rpp/rpp.h
+++ b/rpp/include/rpp/rpp.h
@@ -47,7 +47,7 @@
 #include "rpp/mout.h"
 #include "rpp/sci.h"
 #include "rpp/sdr.h"
-#else
+#else /* if defined(TARGET_POSIX) */
 #error No supported target specified!
 #endif /* TARGET_TMS570_HDK */
 
diff --git a/rpp/src/drv/_rm48_hdk/port_def.c b/rpp/src/drv/_rm48_hdk/port_def.c
index d7adfe1..a354840 100644
--- a/rpp/src/drv/_rm48_hdk/port_def.c
+++ b/rpp/src/drv/_rm48_hdk/port_def.c
@@ -18,24 +18,24 @@
 
 // Lists of pins assigned to the ports
 static enum pin_name pins_gioa[] = {
-		PIN_GIOA0, PIN_GIOA1, PIN_GIOA2, PIN_GIOA3,
-		PIN_GIOA4, PIN_GIOA5, PIN_GIOA6, PIN_GIOA7
+	PIN_GIOA0, PIN_GIOA1, PIN_GIOA2, PIN_GIOA3,
+	PIN_GIOA4, PIN_GIOA5, PIN_GIOA6, PIN_GIOA7
 };
 static enum pin_name pins_giob[] = {
-		PIN_GIOB0, PIN_GIOB1, PIN_GIOB2, PIN_GIOB3,
-		PIN_GIOB4, PIN_GIOB5, PIN_GIOB6, PIN_GIOB7
+	PIN_GIOB0, PIN_GIOB1, PIN_GIOB2, PIN_GIOB3,
+	PIN_GIOB4, PIN_GIOB5, PIN_GIOB6, PIN_GIOB7
 };
 static enum pin_name pins_nhet1[] = {
-		PIN_NHET10, PIN_NHET11, PIN_NHET12,
-		PIN_NHET13, PIN_NHET14, PIN_NHET15,
-		PIN_NHET17, PIN_NHET18, PIN_NHET19,
-		PIN_NHET110, PIN_NHET111, PIN_NHET112,
-		PIN_NHET114, PIN_NHET115, PIN_NHET116,
-		PIN_NHET117, PIN_NHET118, PIN_NHET119,
-		PIN_NHET120, PIN_NHET121, PIN_NHET122,
-		PIN_NHET123, PIN_NHET124, PIN_NHET125,
-		PIN_NHET126, PIN_NHET127, PIN_NHET128,
-		PIN_NHET129, PIN_NHET130, PIN_NHET131
+	PIN_NHET10, PIN_NHET11, PIN_NHET12,
+	PIN_NHET13, PIN_NHET14, PIN_NHET15,
+	PIN_NHET17, PIN_NHET18, PIN_NHET19,
+	PIN_NHET110, PIN_NHET111, PIN_NHET112,
+	PIN_NHET114, PIN_NHET115, PIN_NHET116,
+	PIN_NHET117, PIN_NHET118, PIN_NHET119,
+	PIN_NHET120, PIN_NHET121, PIN_NHET122,
+	PIN_NHET123, PIN_NHET124, PIN_NHET125,
+	PIN_NHET126, PIN_NHET127, PIN_NHET128,
+	PIN_NHET129, PIN_NHET130, PIN_NHET131
 };
 
 // Port descriptors
diff --git a/rpp/src/drv/_tms570_hdk/port_def.c b/rpp/src/drv/_tms570_hdk/port_def.c
index d7adfe1..a354840 100644
--- a/rpp/src/drv/_tms570_hdk/port_def.c
+++ b/rpp/src/drv/_tms570_hdk/port_def.c
@@ -18,24 +18,24 @@
 
 // Lists of pins assigned to the ports
 static enum pin_name pins_gioa[] = {
-		PIN_GIOA0, PIN_GIOA1, PIN_GIOA2, PIN_GIOA3,
-		PIN_GIOA4, PIN_GIOA5, PIN_GIOA6, PIN_GIOA7
+	PIN_GIOA0, PIN_GIOA1, PIN_GIOA2, PIN_GIOA3,
+	PIN_GIOA4, PIN_GIOA5, PIN_GIOA6, PIN_GIOA7
 };
 static enum pin_name pins_giob[] = {
-		PIN_GIOB0, PIN_GIOB1, PIN_GIOB2, PIN_GIOB3,
-		PIN_GIOB4, PIN_GIOB5, PIN_GIOB6, PIN_GIOB7
+	PIN_GIOB0, PIN_GIOB1, PIN_GIOB2, PIN_GIOB3,
+	PIN_GIOB4, PIN_GIOB5, PIN_GIOB6, PIN_GIOB7
 };
 static enum pin_name pins_nhet1[] = {
-		PIN_NHET10, PIN_NHET11, PIN_NHET12,
-		PIN_NHET13, PIN_NHET14, PIN_NHET15,
-		PIN_NHET17, PIN_NHET18, PIN_NHET19,
-		PIN_NHET110, PIN_NHET111, PIN_NHET112,
-		PIN_NHET114, PIN_NHET115, PIN_NHET116,
-		PIN_NHET117, PIN_NHET118, PIN_NHET119,
-		PIN_NHET120, PIN_NHET121, PIN_NHET122,
-		PIN_NHET123, PIN_NHET124, PIN_NHET125,
-		PIN_NHET126, PIN_NHET127, PIN_NHET128,
-		PIN_NHET129, PIN_NHET130, PIN_NHET131
+	PIN_NHET10, PIN_NHET11, PIN_NHET12,
+	PIN_NHET13, PIN_NHET14, PIN_NHET15,
+	PIN_NHET17, PIN_NHET18, PIN_NHET19,
+	PIN_NHET110, PIN_NHET111, PIN_NHET112,
+	PIN_NHET114, PIN_NHET115, PIN_NHET116,
+	PIN_NHET117, PIN_NHET118, PIN_NHET119,
+	PIN_NHET120, PIN_NHET121, PIN_NHET122,
+	PIN_NHET123, PIN_NHET124, PIN_NHET125,
+	PIN_NHET126, PIN_NHET127, PIN_NHET128,
+	PIN_NHET129, PIN_NHET130, PIN_NHET131
 };
 
 // Port descriptors
diff --git a/rpp/src/drv/_tms570_hydctr/port_def.c b/rpp/src/drv/_tms570_hydctr/port_def.c
index d7adfe1..a354840 100644
--- a/rpp/src/drv/_tms570_hydctr/port_def.c
+++ b/rpp/src/drv/_tms570_hydctr/port_def.c
@@ -18,24 +18,24 @@
 
 // Lists of pins assigned to the ports
 static enum pin_name pins_gioa[] = {
-		PIN_GIOA0, PIN_GIOA1, PIN_GIOA2, PIN_GIOA3,
-		PIN_GIOA4, PIN_GIOA5, PIN_GIOA6, PIN_GIOA7
+	PIN_GIOA0, PIN_GIOA1, PIN_GIOA2, PIN_GIOA3,
+	PIN_GIOA4, PIN_GIOA5, PIN_GIOA6, PIN_GIOA7
 };
 static enum pin_name pins_giob[] = {
-		PIN_GIOB0, PIN_GIOB1, PIN_GIOB2, PIN_GIOB3,
-		PIN_GIOB4, PIN_GIOB5, PIN_GIOB6, PIN_GIOB7
+	PIN_GIOB0, PIN_GIOB1, PIN_GIOB2, PIN_GIOB3,
+	PIN_GIOB4, PIN_GIOB5, PIN_GIOB6, PIN_GIOB7
 };
 static enum pin_name pins_nhet1[] = {
-		PIN_NHET10, PIN_NHET11, PIN_NHET12,
-		PIN_NHET13, PIN_NHET14, PIN_NHET15,
-		PIN_NHET17, PIN_NHET18, PIN_NHET19,
-		PIN_NHET110, PIN_NHET111, PIN_NHET112,
-		PIN_NHET114, PIN_NHET115, PIN_NHET116,
-		PIN_NHET117, PIN_NHET118, PIN_NHET119,
-		PIN_NHET120, PIN_NHET121, PIN_NHET122,
-		PIN_NHET123, PIN_NHET124, PIN_NHET125,
-		PIN_NHET126, PIN_NHET127, PIN_NHET128,
-		PIN_NHET129, PIN_NHET130, PIN_NHET131
+	PIN_NHET10, PIN_NHET11, PIN_NHET12,
+	PIN_NHET13, PIN_NHET14, PIN_NHET15,
+	PIN_NHET17, PIN_NHET18, PIN_NHET19,
+	PIN_NHET110, PIN_NHET111, PIN_NHET112,
+	PIN_NHET114, PIN_NHET115, PIN_NHET116,
+	PIN_NHET117, PIN_NHET118, PIN_NHET119,
+	PIN_NHET120, PIN_NHET121, PIN_NHET122,
+	PIN_NHET123, PIN_NHET124, PIN_NHET125,
+	PIN_NHET126, PIN_NHET127, PIN_NHET128,
+	PIN_NHET129, PIN_NHET130, PIN_NHET131
 };
 
 // Port descriptors
diff --git a/rpp/src/drv/_tms570_rpp/port_def.c b/rpp/src/drv/_tms570_rpp/port_def.c
index a127ed4..5e41311 100644
--- a/rpp/src/drv/_tms570_rpp/port_def.c
+++ b/rpp/src/drv/_tms570_rpp/port_def.c
@@ -21,24 +21,24 @@
 
 // Lists of pins assigned to the gio ports
 static enum pin_name pins_dinmcu[] = {
-		PIN_DIN8, PIN_DIN9, PIN_DIN10, PIN_DIN11,
-		PIN_DIN12, PIN_DIN13, PIN_DIN14, PIN_DIN15
+	PIN_DIN8, PIN_DIN9, PIN_DIN10, PIN_DIN11,
+	PIN_DIN12, PIN_DIN13, PIN_DIN14, PIN_DIN15
 };
 static enum pin_name pins_houtin[] = {
-		PIN_HOUT1IN, PIN_HOUT2IN, PIN_HOUT3IN,
-		PIN_HOUT4IN, PIN_HOUT5IN, PIN_HOUT6IN
+	PIN_HOUT1IN, PIN_HOUT2IN, PIN_HOUT3IN,
+	PIN_HOUT4IN, PIN_HOUT5IN, PIN_HOUT6IN
 };
 static enum pin_name pins_houtdiag[] = {
-		PIN_HOUT1DIAG, PIN_HOUT2DIAG, PIN_HOUT3DIAG,
-		PIN_HOUT4DIAG, PIN_HOUT5DIAG, PIN_HOUT6DIAG
+	PIN_HOUT1DIAG, PIN_HOUT2DIAG, PIN_HOUT3DIAG,
+	PIN_HOUT4DIAG, PIN_HOUT5DIAG, PIN_HOUT6DIAG
 };
 static enum pin_name pins_mouten[] = {
-		PIN_MOUT1EN, PIN_MOUT2EN, PIN_MOUT3EN,
-		PIN_MOUT4EN, PIN_MOUT5EN, PIN_MOUT6EN
+	PIN_MOUT1EN, PIN_MOUT2EN, PIN_MOUT3EN,
+	PIN_MOUT4EN, PIN_MOUT5EN, PIN_MOUT6EN
 };
 static enum pin_name pins_moutin[] = {
-		PIN_MOUT1IN, PIN_MOUT2IN, PIN_MOUT3IN,
-		PIN_MOUT4IN, PIN_MOUT5IN, PIN_MOUT6IN
+	PIN_MOUT1IN, PIN_MOUT2IN, PIN_MOUT3IN,
+	PIN_MOUT4IN, PIN_MOUT5IN, PIN_MOUT6IN
 };
 
 const struct port_desc port_desc[] = {
@@ -114,7 +114,7 @@ const struct port_desc port_desc[] = {
 		.cfg = { .spi = { .ifc = 3, .cs = 1 }, },
 	},
 	[PORT_ID_DACDREF] = {
-		.name = "DACDREF",		/* Reference voltage for DIN */
+		.name = "DACDREF",      /* Reference voltage for DIN */
 		.numchn = 1,
 		.bpch = 16,
 		.get = NULL,
diff --git a/rpp/src/drv/din.c b/rpp/src/drv/din.c
index 981b827..1a6c8d6 100644
--- a/rpp/src/drv/din.c
+++ b/rpp/src/drv/din.c
@@ -12,13 +12,13 @@
  * File : din.c
 
  * Abstract:
- * 	   This file is written for 33972 Multiple Switch
- * 	   http://www.freescale.com/files/analog/doc/data_sheet/MC33972.pdf
+ *     This file is written for 33972 Multiple Switch
+ *     http://www.freescale.com/files/analog/doc/data_sheet/MC33972.pdf
  *
- * 	   This file contains functions to control DIN
- * 	   Voltage on each pin can be set
- * 	   switch to ground or to battery on programable pins can be set
- * 	   interrupts on each pins can be disabled and enabled
+ *     This file contains functions to control DIN
+ *     Voltage on each pin can be set
+ *     switch to ground or to battery on programable pins can be set
+ *     interrupts on each pins can be disabled and enabled
  */
 
 
@@ -168,9 +168,10 @@ uint16_t din_get_val_word()
  */
 static int din_spi_transfer_mst(const uint32_t din_spi_cmd)
 {
-	const struct port_desc* port = &port_desc[PORT_ID_DINSPI];
+	const struct port_desc *port = &port_desc[PORT_ID_DINSPI];
 
 	char commands[3];
+
 	commands[0] = (din_spi_cmd & 0xFF0000) >> 16;   // command
 	commands[1] = (din_spi_cmd & 0xFF00) >> 8;      // 1.st B of data
 	commands[2] = (din_spi_cmd & 0xFF);             // 2.nd B of data
diff --git a/rpp/src/drv/fr_tms570.c b/rpp/src/drv/fr_tms570.c
index a0a645a..df38339 100644
--- a/rpp/src/drv/fr_tms570.c
+++ b/rpp/src/drv/fr_tms570.c
@@ -11,7 +11,7 @@
  * File : fr_rms570.c
  *
  * Abstract:
- * 	   FlexRay Communication driver for TMS570 source file.
+ *     FlexRay Communication driver for TMS570 source file.
  */
 
 #include "drv/drv.h"
diff --git a/rpp/src/drv/fray.c b/rpp/src/drv/fray.c
index 194c2f6..f7b7dac 100644
--- a/rpp/src/drv/fray.c
+++ b/rpp/src/drv/fray.c
@@ -12,7 +12,7 @@
  * File : fray.c
  *
  * Abstract:
- * 	   This file contains function for getting fray status as spi respons
+ *     This file contains function for getting fray status as spi respons
  *     and functions for FlexRay initialization and usage.
  *     FlexRay chips on SPI are read only.
  */
diff --git a/rpp/src/drv/gio.c b/rpp/src/drv/gio.c
index 7e02f5a..060a893 100644
--- a/rpp/src/drv/gio.c
+++ b/rpp/src/drv/gio.c
@@ -9,7 +9,7 @@
 
 static gioPORT_t *gio_reg[] = {
 #ifdef TARGET_HAS_DMM
-	[GIO_PORT_DMM]	= dmmPORT,
+	[GIO_PORT_DMM]  = dmmPORT,
 #endif
 	[GIO_PORT_GIOA] = gioPORTA,
 	[GIO_PORT_GIOB] = gioPORTB,
@@ -57,7 +57,7 @@ void gio_setup(uint32_t pin_dsc)
 
 	if (pin_dsc & GIO_PIN_CONF_SET_DIR) {
 		if ((pin_dsc & GIO_PIN_CONF_DIR_MASK) ==
-				(GIO_PIN_CONF_DIR_OUT & GIO_PIN_CONF_DIR_MASK))
+			(GIO_PIN_CONF_DIR_OUT & GIO_PIN_CONF_DIR_MASK))
 			gioPort->DIR |= pin_bit;
 		else
 			gioPort->DIR &= ~pin_bit;
diff --git a/rpp/src/drv/hout.c b/rpp/src/drv/hout.c
index 6ea1dfa..481e5ab 100644
--- a/rpp/src/drv/hout.c
+++ b/rpp/src/drv/hout.c
@@ -11,7 +11,7 @@
  * File : hout.c
  *
  * Abstract:
- * 	    This file provides functions and procedures to manipulate HOUT port.
+ *      This file provides functions and procedures to manipulate HOUT port.
  *
  *      Functions for setting, starting and stopping PWM on selected HOUT pin.
  */
@@ -159,7 +159,7 @@ int hout_fail(uint8_t hout_id)
 	uint32_t i;
 	uint16_t pwm_running;
 	int err_cnt = 0;
-	const struct port_desc* hout_in_port = &port_desc[PORT_ID_HOUTIN];
+	const struct port_desc *hout_in_port = &port_desc[PORT_ID_HOUTIN];
 
 
 	if (hout_id >= hout_in_port->numchn)
diff --git a/rpp/src/drv/lout.c b/rpp/src/drv/lout.c
index e3e8ec4..fbc9d07 100644
--- a/rpp/src/drv/lout.c
+++ b/rpp/src/drv/lout.c
@@ -11,7 +11,7 @@
  * File : lout.c
  *
  * Abstract:
- * 	    This file contains functions to control LOUT port over SPI
+ *      This file contains functions to control LOUT port over SPI
  */
 
 //#include "drv/lout.h"
diff --git a/rpp/src/rpp/eth.c b/rpp/src/rpp/eth.c
index cb3e298..6eb21b0 100644
--- a/rpp/src/rpp/eth.c
+++ b/rpp/src/rpp/eth.c
@@ -68,21 +68,21 @@
 
 
 /* Number of EMAC Instances */
-#define MAX_EMAC_INSTANCE			1
+#define MAX_EMAC_INSTANCE           1
 
-#define DEFAULT_PHY_ADDR			0x1
-#define FIND_FIRST_PHY_ALIVE			1 /* or use default (phy_address: 1) */
-#define NUM_OF_PHYs				32
+#define DEFAULT_PHY_ADDR            0x1
+#define FIND_FIRST_PHY_ALIVE            1 /* or use default (phy_address: 1) */
+#define NUM_OF_PHYs             32
 
 /* Size of the Buffer descriptor defined by the EMAC in bytes */
-#define SIZE_OF_DESC				16
+#define SIZE_OF_DESC                16
 
 /* Channel number used for for RX, TX, unicast, broadcast or damaged frames;
  * there are different channels for rx and tx operations (i.e. RXCH0 != TXCH0) */
-#define CHANNEL					0
+#define CHANNEL                 0
 
 /* take in account oversized frames */
-#define MAX_TRANSFER_UNIT			1500
+#define MAX_TRANSFER_UNIT           1500
 
 /* WARNING!
  * Be very carefull when setting this value. We have to keep in mind
@@ -104,27 +104,27 @@
  * This is the implementation limitation. The PBUF_LEN_MAX should therefore
  * be multiple of PBUF_POOL_BUFSIZE
  */
-#define PBUF_LEN_MAX				(PBUF_POOL_BUFSIZE * 6)
+#define PBUF_LEN_MAX                (PBUF_POOL_BUFSIZE * 6)
 
 /* Maximum number of PBUFs preallocated in the driver
  * init function to be used for the RX
  */
-#define MAX_RX_PBUF_ALLOC			10
-#define MIN_PKT_LEN				60
+#define MAX_RX_PBUF_ALLOC           10
+#define MIN_PKT_LEN             60
 
 /* Define those to better describe the network interface. */
-#define IFNAME0					'e'
-#define IFNAME1					'n'
+#define IFNAME0                 'e'
+#define IFNAME1                 'n'
 
 /* Time to wait for autonegotiation in ticks. */
-#define TICKS_PHY_AUTONEG			4000
+#define TICKS_PHY_AUTONEG           4000
 
 /**
  * TODO -- not implemented
  * When cable is connected (link status goes up)
  * autonegotiation and/or dhcp is started.
  */
-#define PHY_LINK_MONITOR_INT			0
+#define PHY_LINK_MONITOR_INT            0
 
 
 /* Statically allocated structure describing interface state -- one per instance */
@@ -146,6 +146,7 @@ boolean_t isPostInitialized()
 uint32_t rpp_eth_phylinkstat(uint32_t instNum)
 {
 	struct hdkif *hdkif = &hdkif_data[instNum];
+
 	return PHY_link_status_get(hdkif->mdio_base, hdkif->phy_addr, 1);
 }
 
@@ -186,7 +187,7 @@ err_t rpp_eth_stringToIP(ip_addr_t * ip, uint8_t * ipstr)
 			ipaddr = (ipaddr << 8) + tmp;
 
 			dots++;
-			if(dots > 3)break;
+			if (dots > 3)break;
 
 			tmp = 0;
 			fldEdit = FALSE;
@@ -283,8 +284,7 @@ static void hdkif_macaddrset(u32_t inst_num, u8_t *mac_addr)
 */
 static void hdkif_inst_config(struct hdkif *hdkif)
 {
-	if (hdkif->inst_num == 0)
-	{
+	if (hdkif->inst_num == 0) {
 		hdkif->emac_base = EMAC_BASE_m(0);
 		hdkif->emac_ctrl_base = EMAC_CTRL_BASE_m(0);
 		hdkif->emac_ctrl_ram = EMAC_CTRL_RAM_BASE_m(0);
@@ -311,8 +311,7 @@ int8_t rpp_eth_init()
 		return FAILURE;
 
 	/* Config each EMAC instance */
-	for (instNum = 0; instNum < MAX_EMAC_INSTANCE; instNum++)
-	{
+	for (instNum = 0; instNum < MAX_EMAC_INSTANCE; instNum++) {
 		struct hdkif *hdkif = &hdkif_data[instNum];
 
 		hdkif->inst_num = instNum;
@@ -376,12 +375,12 @@ int8_t rpp_eth_init_postInit(uint32_t instNum, uint8_t *macArray)
 	 * and initialize netif with specific function
 	 */
 	netif_tmp = netif_add(netif, &ip_addr, &net_mask, &gw_addr,
-			      &hdkif_data[instNum], rpp_eth_lwip_init,
-			      ethernet_input);
+						  &hdkif_data[instNum], rpp_eth_lwip_init,
+						  ethernet_input);
 #else
 	netif_tmp = netif_add(netif, &ip_addr, &net_mask, &gw_addr,
-			      &hdkif_data[instNum], rpp_eth_lwip_init,
-			      tcpip_input);
+						  &hdkif_data[instNum], rpp_eth_lwip_init,
+						  tcpip_input);
 #endif
 	if (netif_tmp == NULL)
 		return NETIF_ADD_ERR;
@@ -584,8 +583,8 @@ static err_t rpp_eth_hw_init(struct hdkif *hdkif)
 	 * when complete link register will be updated
 	 */
 	hdkif->phy_autoneg_start(hdkif->mdio_base, hdkif->phy_addr,
-			PHY_100BASETXDUPL_m | PHY_100BASETX_m |
-			PHY_10BASETDUPL_m | PHY_10BASET_m);
+							 PHY_100BASETXDUPL_m | PHY_100BASETX_m |
+							 PHY_10BASETDUPL_m | PHY_10BASET_m);
 
 	/*
 	 * TODO: you can implement init of receive flow control somewhere
@@ -731,9 +730,9 @@ static err_t rpp_eth_hw_init_postInit(struct netif *netif)
 
 #ifdef DEBUG
 	num_bd = (((uintptr_t)rxch->active_tail - (uintptr_t)rxch->active_head)
-			/ sizeof(struct emac_rx_bd)) + 1;
+			  / sizeof(struct emac_rx_bd)) + 1;
 	rpp_debug_printf("%d pbuf chains allocated for %d rx buffer descriptors\n",
-			 pbuf_cnt, num_bd);
+					 pbuf_cnt, num_bd);
 #endif
 
 	/* Set header descriptor pointers -- this shows EMAC which descriptor
@@ -764,7 +763,7 @@ static err_t rpp_eth_hw_init_postInit(struct netif *netif)
 	 */
 	for (regContent = 0; regContent < 8; regContent++) {
 		EMACMACAddrSet(hdkif->emac_base, regContent, hdkif->mac_addr,
-			       EMAC_MACADDR_NO_MATCH_NO_FILTER);
+					   EMAC_MACADDR_NO_MATCH_NO_FILTER);
 	}
 
 #if !PHY_LINK_MONITOR_INT
@@ -828,6 +827,7 @@ static err_t rpp_eth_hw_init_postInit(struct netif *netif)
 err_t rpp_eth_send(struct netif *netif, struct pbuf *p)
 {
 	err_t retVal = SUCCESS;
+
 	SYS_ARCH_DECL_PROTECT(lev);
 
 	/**
@@ -898,8 +898,8 @@ static err_t rpp_eth_send_raw(struct netif *netif, struct pbuf *pbuf)
 
 	/* First 'part' of packet flags */
 	curr_bd->flags_pktlen = pbuf->tot_len |
-				EMAC_DSC_FLAG_SOP |
-				EMAC_DSC_FLAG_OWNER;
+							EMAC_DSC_FLAG_SOP |
+							EMAC_DSC_FLAG_OWNER;
 
 	/* Copy pbuf information into TX BDs --
 	 * remember that the pbuf for a single packet might be chained!
@@ -957,7 +957,7 @@ static err_t rpp_eth_send_raw(struct netif *netif, struct pbuf *pbuf)
 			while (HWREG(hdkif->emac_base + EMAC_TXHDP(CHANNEL)) != 0)
 				;
 			EMACTxHdrDescPtrWrite(hdkif->emac_base,
-					(unsigned int)(active_head), CHANNEL);
+								  (unsigned int)(active_head), CHANNEL);
 		}
 	}
 	txch->active_tail = active_tail;
@@ -1012,7 +1012,7 @@ void rpp_eth_send_raw_thr(void *arg)
 
 			/* Ack the Interrupt in the EMAC peripheral */
 			EMACTxCPWrite(hdkif->emac_base, CHANNEL,
-				      (uint32_t)curr_bd);
+						  (uint32_t)curr_bd);
 
 			/* Free the corresponding pbuf
 			 * Sidenote: Each fragment of the single packet points
@@ -1268,11 +1268,11 @@ boolean_t HostPendErrHandler(void)
 	rpp_sci_printk("HOSTPEND err\n");
 	reg = HWREG(hdkif->emac_base + EMAC_MACSTATUS);
 	rpp_sci_printk("TXCHERR: %d at CH: %d\n",
-			((reg >> EMAC_MACSTATUS_TXERRCODE_SHIFT) & 0x7),
-			((reg >> EMAC_MACSTATUS_TXERRCH_SHIFT) & 0x7));
+				   ((reg >> EMAC_MACSTATUS_TXERRCODE_SHIFT) & 0x7),
+				   ((reg >> EMAC_MACSTATUS_TXERRCH_SHIFT) & 0x7));
 	rpp_sci_printk("RXCHERR: %d at CH: %d\n",
-			((reg >> EMAC_MACSTATUS_RXERRCODE_SHIFT) & 0x7),
-			((reg >> EMAC_MACSTATUS_RXERRCH_SHIFT) & 0x7));
+				   ((reg >> EMAC_MACSTATUS_RXERRCODE_SHIFT) & 0x7),
+				   ((reg >> EMAC_MACSTATUS_RXERRCH_SHIFT) & 0x7));
 
 	{ /* Print out all the RX BDs */
 		struct rxch *rxch;
@@ -1289,16 +1289,16 @@ boolean_t HostPendErrHandler(void)
 			glob_len += curr_bd->pbuf->len;
 
 			rpp_sci_printk("[%p: buf: %p buffoff_len: 0x%x "
-					"\tflags: 0x%x pktlen: 0x%x]",
-					curr_bd,
-					curr_bd->bufptr,
-					curr_bd->bufoff_len,
-					(curr_bd->flags_pktlen >> 16) & 0xFFFF,
-					curr_bd->flags_pktlen & 0xFFFF);
+						   "\tflags: 0x%x pktlen: 0x%x]",
+						   curr_bd,
+						   curr_bd->bufptr,
+						   curr_bd->bufoff_len,
+						   (curr_bd->flags_pktlen >> 16) & 0xFFFF,
+						   curr_bd->flags_pktlen & 0xFFFF);
 			rpp_sci_printk(" pbuf: tot_len: 0x%x \tlen: 0x%x ref: 0x%x\n",
-					curr_bd->pbuf->tot_len,
-					curr_bd->pbuf->len,
-					curr_bd->pbuf->ref);
+						   curr_bd->pbuf->tot_len,
+						   curr_bd->pbuf->len,
+						   curr_bd->pbuf->ref);
 		}
 		rpp_sci_printk("glob_len: %d\n", glob_len);
 	}
@@ -1325,9 +1325,9 @@ boolean_t LinkIntHandler(void)
 	while (index) {
 		hdkif = &hdkif_data[--index];
 		if ((hdkif->phy_addr ==
-		     (HWREG(hdkif->mdio_base + MDIO_USERPHYSEL0) & 0x1f)) &&
-		    (EMACIntVectorGet(hdkif->emac_base) &
-		     EMAC_MACINVECTOR_LINKINT0))
+			 (HWREG(hdkif->mdio_base + MDIO_USERPHYSEL0) & 0x1f)) &&
+			(EMACIntVectorGet(hdkif->emac_base) &
+			 EMAC_MACINVECTOR_LINKINT0))
 			phyFound = TRUE;
 	}
 	if (!phyFound)
@@ -1374,9 +1374,9 @@ boolean_t LinkIntHandler(void)
 #if STATIC_IP_ADDRESS
 		netif_set_up(netif);
 #elif LWIP_DHCP /* STATIC_IP_ADDRESS-LWIP_DHCP */
-		if (dhcp_start(netif) != ERR_OK) { /* XXX: can't be used from ISR (mem_malloc()) */
+		if (dhcp_start(netif) != ERR_OK)   /* XXX: can't be used from ISR (mem_malloc()) */
 			return DHCP_MEM_ERR;
-		}
+
 #if ONCE_LINK_SETUP
 		while (netif->dhcp->state != DHCP_BOUND)
 			;