#include "sys/sys_pinmux.h"
#define PINMUX_SET(REG, BALLID, MUX) \
- pinMuxReg->PINMUX##REG## = (pinMuxReg->PINMUX##REG## & PINMUX_BALL_##BALLID##_MASK) | (PINMUX_BALL_##BALLID##_##MUX##)
+ pinMuxReg->PINMUX##REG = (pinMuxReg->PINMUX##REG & PINMUX_BALL_##BALLID##_MASK) | (PINMUX_BALL_##BALLID##_##MUX)
#define PINMUX_GATE_EMIF_CLK_ENABLE \
pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_GATE_EMIF_CLK_MASK) | PINMUX_GATE_EMIF_CLK
-#define PINMUX_GIOB_DISABLE_HET2_ENABLE \
- pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_GIOB_DISABLE_HET2_MASK) | PINMUX_GIOB_DISABLE_HET2
+#define PINMUX_GIOB_DISABLE_HET2_ENABLE(state) \
+ (pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_GIOB_DISABLE_HET2_MASK) | (PINMUX_GIOB_DISABLE_HET2_##state))
#define PINMUX_ALT_ADC_TRIGGER_SELECT(num) \
- pinMuxReg->PINMUX30 = (pinMuxReg->PINMUX30 & PINMUX_ALT_ADC_TRIGGER_MASK) | (PINMUX_ALT_ADC_TRIGGER_##num##)
+ pinMuxReg->PINMUX30 = (pinMuxReg->PINMUX30 & PINMUX_ALT_ADC_TRIGGER_MASK) | (PINMUX_ALT_ADC_TRIGGER_##num)
#define PINMUX_ETHERNET_SELECT(interface) \
- pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_ETHERNET_MASK) | (PINMUX_ETHERNET_##interface##)
-
-/* USER CODE BEGIN (0) */
-/* USER CODE END */
+ pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_ETHERNET_MASK) | (PINMUX_ETHERNET_##interface)
void muxInit(void){
-/* USER CODE BEGIN (1) */
-/* USER CODE END */
-
/* Enable Pin Muxing */
kickerReg->KICKER0 = 0x83E70B13;
kickerReg->KICKER1 = 0x95A4F1E0;
-/* USER CODE BEGIN (2) */
-/* USER CODE END */
+ pinMuxReg->PINMUX0 = PINMUX_BALL_W10_GIOB_3 | PINMUX_BALL_A5_GIOA_0;
- pinMuxReg->PINMUX0 = PINMUX_BALL_C3_I2C_SCL | PINMUX_BALL_B2_I2C_SDA;
+ pinMuxReg->PINMUX1 = PINMUX_BALL_C2_GIOA_1 | PINMUX_BALL_E3_HET1_11 | PINMUX_BALL_E5_EMIF_DATA_4 | PINMUX_BALL_F5_EMIF_DATA_5;
- pinMuxReg->PINMUX1 = PINMUX_BALL_E3_MIBSPI3NCS_4 | PINMUX_BALL_E5_EMIF_DATA_4 | PINMUX_BALL_F5_EMIF_DATA_5;
+ pinMuxReg->PINMUX2 = PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_G5_EMIF_DATA_6 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5;
- pinMuxReg->PINMUX2 = PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_G5_EMIF_DATA_6 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5;
+ pinMuxReg->PINMUX3 = PINMUX_BALL_K5_EMIF_DATA_7 | PINMUX_BALL_B3_HET1_22 | PINMUX_BALL_H3_GIOA_6 | PINMUX_BALL_L5_EMIF_DATA_8;
- pinMuxReg->PINMUX3 = PINMUX_BALL_K5_EMIF_DATA_7 | PINMUX_BALL_H3_GIOA_6 | PINMUX_BALL_L5_EMIF_DATA_8;
+ pinMuxReg->PINMUX4 = PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_M5_EMIF_DATA_9 | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_HET1_03;
- pinMuxReg->PINMUX4 = PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_M5_EMIF_DATA_9 | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_SPI4NCS_0;
+ pinMuxReg->PINMUX5 = PINMUX_BALL_K18_HET1_0 | PINMUX_BALL_W5_HET1_02 | PINMUX_BALL_V6_HET1_05 | PINMUX_BALL_N5_EMIF_DATA_10;
- pinMuxReg->PINMUX5 = PINMUX_BALL_K18_SPI4CLK | PINMUX_BALL_W5_SPI4SIMO | PINMUX_BALL_V6_SPI4SOMI | PINMUX_BALL_N5_EMIF_DATA_10;
+ pinMuxReg->PINMUX6 = PINMUX_BALL_T1_HET1_07 | PINMUX_BALL_P5_EMIF_DATA_11 | PINMUX_BALL_V7_HET1_09 | PINMUX_BALL_R5_EMIF_DATA_12;
- pinMuxReg->PINMUX6 = PINMUX_BALL_T1_HET1_07 | PINMUX_BALL_P5_EMIF_DATA_11 | PINMUX_BALL_V7_HET1_09 | PINMUX_BALL_R5_EMIF_DATA_12;
+ pinMuxReg->PINMUX7 = PINMUX_BALL_R6_EMIF_DATA_13 | PINMUX_BALL_W3_HET1_06 | PINMUX_BALL_R7_EMIF_DATA_14;
- pinMuxReg->PINMUX7 = PINMUX_BALL_R6_EMIF_DATA_13 | PINMUX_BALL_V5_MDCLK | PINMUX_BALL_W3_SCIRX | PINMUX_BALL_R7_EMIF_DATA_14;
+ pinMuxReg->PINMUX8 = PINMUX_BALL_N2_HET1_13 | PINMUX_BALL_N1_HET1_15 | PINMUX_BALL_R8_EMIF_DATA_15;
- pinMuxReg->PINMUX8 = PINMUX_BALL_N2_SCITX | PINMUX_BALL_G3_MDIO | PINMUX_BALL_N1_MIBSPI1NCS_4 | PINMUX_BALL_R8_EMIF_DATA_15;
+ pinMuxReg->PINMUX9 = ((~(pinMuxReg->PINMUX9 >> 18U) & 0x00000001U ) << 18U) | PINMUX_BALL_R9_ETMTRACECLKIN | PINMUX_BALL_V10_GIOB_2;
- pinMuxReg->PINMUX9 = PINMUX_BALL_R9_ETMTRACECLKIN | PINMUX_BALL_W9_MIBSPI3NCS_5 | PINMUX_BALL_V10_MIBSPI3NCS_0 | PINMUX_BALL_J3_MIBSPI1NCS_3;
+ pinMuxReg->PINMUX10 = PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_N15_EMIF_DATA_3 | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_M15_EMIF_DATA_2;
- pinMuxReg->PINMUX10 = PINMUX_BALL_N19_MII_RX_ER | PINMUX_BALL_N15_EMIF_DATA_3 | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_M15_EMIF_DATA_2;
+ pinMuxReg->PINMUX11 = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_EMIF_DATA_1 | PINMUX_BALL_P1_HET1_24;
- pinMuxReg->PINMUX11 = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_EMIF_DATA_1 | PINMUX_BALL_P1_MII_RXD_0;
+ pinMuxReg->PINMUX12 = PINMUX_BALL_A14_HET1_26 | PINMUX_BALL_K15_EMIF_DATA_0 | PINMUX_BALL_H18_MIBSPI5NENA;
- pinMuxReg->PINMUX12 = PINMUX_BALL_A14_MII_RXD_1 | PINMUX_BALL_K15_EMIF_DATA_0 | PINMUX_BALL_G19_MII_RXD_2 | PINMUX_BALL_H18_MII_RXD_3;
+ pinMuxReg->PINMUX13 = PINMUX_BALL_J18_MIBSPI5SOMI_0 | PINMUX_BALL_J19_MIBSPI5SIMO_0 | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_R2_MIBSPI1NCS_0;
- pinMuxReg->PINMUX13 = PINMUX_BALL_J18_MII_TXD_0 | PINMUX_BALL_J19_MII_TXD_1 | PINMUX_BALL_H19_MII_TXEN | PINMUX_BALL_R2_MII_TXD_2;
+ pinMuxReg->PINMUX14 = PINMUX_BALL_E18_HET1_08 | PINMUX_BALL_K19_HET1_28 | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1;
- pinMuxReg->PINMUX14 = PINMUX_BALL_E18_MII_TXD_3 | PINMUX_BALL_K19_MII_RXCLK | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1;
+ pinMuxReg->PINMUX15 = PINMUX_BALL_C17_EMIF_ADDR_21 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_D15_EMIF_ADDR_18;
- pinMuxReg->PINMUX15 = PINMUX_BALL_C17_EMIF_ADDR_21 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_D15_EMIF_ADDR_18;
+ pinMuxReg->PINMUX16 = PINMUX_BALL_E13_EMIF_BA_0 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_E12_EMIF_nOE;
- pinMuxReg->PINMUX16 = PINMUX_BALL_E13_EMIF_BA_0 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_E12_EMIF_nOE;
+ pinMuxReg->PINMUX17 = PINMUX_BALL_D19_HET1_10 | PINMUX_BALL_E11_EMIF_nDQM_1 | PINMUX_BALL_B4_HET1_12 | PINMUX_BALL_E9_EMIF_ADDR_5;
- pinMuxReg->PINMUX17 = PINMUX_BALL_D19_MII_TX_CLK | PINMUX_BALL_E11_EMIF_nDQM_1 | PINMUX_BALL_B4_MII_CRS | PINMUX_BALL_E9_EMIF_ADDR_5;
+ pinMuxReg->PINMUX18 = PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_A11_HET1_14 | PINMUX_BALL_C12_EMIF_ADDR_14 | PINMUX_BALL_M2_GIOB_0;
- pinMuxReg->PINMUX18 = PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_C12_EMIF_ADDR_14 | PINMUX_BALL_M2_GIOB_0;
+ pinMuxReg->PINMUX19 = PINMUX_BALL_E8_EMIF_ADDR_4 | PINMUX_BALL_B11_HET1_30 | PINMUX_BALL_E10_EMIF_nDQM_0 | PINMUX_BALL_E7_EMIF_ADDR_3;
- pinMuxReg->PINMUX19 = PINMUX_BALL_E8_EMIF_ADDR_4 | PINMUX_BALL_B11_MII_RX_DV | PINMUX_BALL_E10_EMIF_nDQM_0 | PINMUX_BALL_E7_EMIF_ADDR_3;
+ pinMuxReg->PINMUX20 = PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_C9_EMIF_ADDR_11;
- pinMuxReg->PINMUX20 = PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_F3_MII_COL | PINMUX_BALL_C9_EMIF_ADDR_11;
+ pinMuxReg->PINMUX21 = PINMUX_BALL_D5_EMIF_ADDR_1 | PINMUX_BALL_K2_GIOB_1 | PINMUX_BALL_C8_EMIF_ADDR_10 | PINMUX_BALL_C7_EMIF_ADDR_9;
- pinMuxReg->PINMUX21 = PINMUX_BALL_D5_EMIF_ADDR_1 | PINMUX_BALL_C8_EMIF_ADDR_10 | PINMUX_BALL_C7_EMIF_ADDR_9;
+ pinMuxReg->PINMUX22 = PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6 | PINMUX_BALL_E6_EMIF_ADDR_2;
- pinMuxReg->PINMUX22 = PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6 | PINMUX_BALL_E6_EMIF_ADDR_2;
+ pinMuxReg->PINMUX23 = ((~(pinMuxReg->PINMUX5 >> 1U) & 0x00000001U ) << 8U) | ((~(pinMuxReg->PINMUX5 >> 9U) & 0x00000001U ) << 16U) | ((~(pinMuxReg->PINMUX5 >> 17U) & 0x00000001U ) << 24U) | PINMUX_BALL_C6_EMIF_ADDR_8;
- pinMuxReg->PINMUX23 = 0x00010100| /* SPI4SOMI is on ball W6 */
- PINMUX_BALL_C6_EMIF_ADDR_8;
+ pinMuxReg->PINMUX24 = ((~(pinMuxReg->PINMUX4 >> 17U) & 0x00000001U ) << 0U) | ((~(pinMuxReg->PINMUX4 >> 25U) & 0x00000001U ) << 8U) | PINMUX_BALL_A13_HET1_17 | PINMUX_BALL_B13_HET1_19;
- pinMuxReg->PINMUX24 = 0x01010101;
+ pinMuxReg->PINMUX25 = PINMUX_BALL_H4_HET1_21 | PINMUX_BALL_J4_HET1_23 | PINMUX_BALL_M3_HET1_25 | PINMUX_BALL_B2_HET1_27;
- pinMuxReg->PINMUX25 = 0x01010101;
+ pinMuxReg->PINMUX26 = PINMUX_BALL_A3_HET1_29 | PINMUX_BALL_J17_HET1_31 | PINMUX_BALL_W6_MIBSPI5NCS_2 | PINMUX_BALL_T12_MIBSPI5NCS_3;
- /* Halcogen fix enabling N2HET1[29], N2HET1[31] */
- pinMuxReg->PINMUX26 = 0x0101 | PINMUX_BALL_W6_DMM_DATA_2 | PINMUX_BALL_T12_DMM_DATA_3;
+ pinMuxReg->PINMUX27 = PINMUX_BALL_E19_MIBSPI5NCS_0 | PINMUX_BALL_B6_MIBSPI5NCS_1 | PINMUX_BALL_E16_MIBSPI5SIMO_1 | PINMUX_BALL_H17_MIBSPI5SIMO_2;
- pinMuxReg->PINMUX27 = PINMUX_BALL_E19_DMM_DATA_5 | PINMUX_BALL_B6_DMM_DATA_6 | PINMUX_BALL_E16_DMM_DATA_9 | PINMUX_BALL_H17_DMM_DATA_10;
+ pinMuxReg->PINMUX28 = PINMUX_BALL_G17_MIBSPI5SIMO_3 | PINMUX_BALL_E17_MIBSPI5SOMI_1 | PINMUX_BALL_H16_MIBSPI5SOMI_2 | PINMUX_BALL_G16_MIBSPI5SOMI_3;
- pinMuxReg->PINMUX28 = PINMUX_BALL_G17_DMM_DATA_11 | PINMUX_BALL_E17_DMM_DATA_13 | PINMUX_BALL_H16_DMM_DATA_14 | PINMUX_BALL_G16_DMM_DATA_15;
+ pinMuxReg->PINMUX29 = PINMUX_BALL_D3_SPI2NENA;
- pinMuxReg->PINMUX29 = PINMUX_BALL_D3_SPI2NCS_1;
+ PINMUX_GATE_EMIF_CLK_ENABLE;
+ PINMUX_GIOB_DISABLE_HET2_ENABLE(OFF);
+ PINMUX_ALT_ADC_TRIGGER_SELECT(1);
+ PINMUX_ETHERNET_SELECT(RMII);
+ /* Disable Pin Muxing */
+ kickerReg->KICKER0 = 0x00000000U;
+ kickerReg->KICKER1 = 0x00000000U;
+ /* Bit 31 of register GPREG1 is used to gate off the
+ EMIF module outputs */
+ systemREG1->GPREG1 |= 0x80000;
+}
+/*
+ * This function explicitly enable/disable HET2 inputs for IRC module
+ * Parameters: irc - IRC number
+ * 1 for IRC is connected to DIN10 and DIN11
+ * 2 for IRC is connected to DIN14 and DIN15
+ * enable - TRUE for IRC, FALSE for normal usage as digital inputs
+ */
+void setMuxForIRC(int8_t irc, boolean_t enable) {
- PINMUX_ALT_ADC_TRIGGER_SELECT(1);
- PINMUX_ETHERNET_SELECT(MII);
+ /* Enable Pin Muxing */
+ kickerReg->KICKER0 = 0x83E70B13;
+ kickerReg->KICKER1 = 0x95A4F1E0;
+
+ if (enable) {
+ switch (irc) {
+ case 1: // set DIN10 and DIN11 to HET2
+ PINMUX_SET(2,C1,HET2_0);
+ PINMUX_SET(2,E1,HET2_2);
+ break;
+ case 2: // set DIN14 and DIN15 to HET2
+ PINMUX_SET(3,H3,HET2_4);
+ PINMUX_SET(4,M1,HET2_6);
+ break;
+ }
+ } else {
+ switch (irc) {
+ case 1: // set DIN10 and DIN11 back from HET2
+ PINMUX_SET(2,C1,GIOA_2);
+ PINMUX_SET(2,E1,GIOA_3);
+ break;
+ case 2: // set DIN14 and DIN15 back from HET2
+ PINMUX_SET(3,H3,GIOA_6);
+ PINMUX_SET(4,M1,GIOA_7);
+ break;
+ }
+ }
- PINMUX_SET(0,A5,GIOA_0);
- PINMUX_SET(18,A11,HET1_14);
- PINMUX_SET(3,B3,HET1_22);
- PINMUX_SET(1,C2,GIOA_1);
- PINMUX_SET(21,K2,GIOB_1);
- PINMUX_SET(0,W10,GIOB_3);
-/* USER CODE BEGIN (3) */
-/* USER CODE END */
/* Disable Pin Muxing */
kickerReg->KICKER0 = 0x00000000;
kickerReg->KICKER1 = 0x00000000;
-/* USER CODE BEGIN (4) */
-/* USER CODE END */
}
-
-/* USER CODE BEGIN (5) */
-/* USER CODE END */