ENA register is set even on SPI devices which do not have it --
this should not be an issue
*/
-void spiInit(spiBASE_compat_t *spiREG)
+static void spiInit(spiBASE_compat_t *spiREG)
{
/** bring SPI out of reset */
spiREG->GCR0 = 1U;
| 0; /* C2EDELAY */
/** - Data Format 0 */
+ /* TODO: Set the formats from spi_tms570_iface_t if we need different formats */
spiREG->FMT0 = (0 << 24) /* wdelay */
| (0 << 23) /* parity Polarity */
| (0 << 22) /* parity enable */
static boolean_t spi_initialized = FALSE;
-int spi_tms570_init(spi_tms570_drv_t *ifcs, int count)
+int spi_tms570_init(spi_tms570_iface_t *ifcs, int count)
{
if (spi_initialized == TRUE)
return FAILURE;
int i;
for (i = 0; i < count; i++) {
- spiInit(ifcs[i].spi);
+ spiInit(ifcs[i].reg);
ifcs[i].spi_drv.ctrl_fnc = spi_tms570_ctrl_fnc;
spi_rq_queue_init_head(&(ifcs[i].spi_drv));
ifcs[i].spi_drv.msg_act = NULL;
static int spi_tms570_ctrl_fnc(spi_drv_t *ifc, int ctrl, void *p)
{
- spi_tms570_drv_t *tms570_drv =
- UL_CONTAINEROF(ifc, spi_tms570_drv_t, spi_drv);
+ spi_tms570_iface_t *tms570_drv =
+ UL_CONTAINEROF(ifc, spi_tms570_iface_t, spi_drv);
switch (ctrl) {
case SPI_CTRL_WAKE_RQ:
if (spi_rq_queue_is_empty(ifc))
return 0;
- tms570_drv->spi->INT0 = SPI_INT0_TXINTENA_m;
+ tms570_drv->reg->INT0 = SPI_INT0_TXINTENA_m;
// Enable TXINT (Causes an interrupt
// to be generated every time data is written to the shift
// register, so that the next word can be written to TXBUF.
void spi_tms570_isr(int spi_ifc, uint32_t flags)
{
- spi_msg_head_t *msg;
- spi_tms570_drv_t *spi_tms570_drv = &spi_ifcs[spi_ifc];
+ spi_msg_t *msg;
+ spi_tms570_iface_t *iface = &spi_ifcs[spi_ifc];
spi_isr_lock_level_t saveif;
uint8_t val_to_wr;
uint32_t cs;
if (flags & SPI_FLG_TXINT_m) {
do {
- msg = spi_tms570_drv->spi_drv.msg_act;
+ msg = iface->spi_drv.msg_act;
if (!msg) { /* Is there any MSG being processed? */
/* If not, get one from a queue */
spi_isr_lock(saveif);
- msg = spi_tms570_drv->spi_drv.msg_act =
- spi_rq_queue_first(&spi_tms570_drv->spi_drv);
+ msg = iface->spi_drv.msg_act =
+ spi_rq_queue_first(&iface->spi_drv);
spi_isr_unlock(saveif);
if (!msg) { /* Nothing to process */
volatile unsigned int dummy_read;
/* Disable TXEMPTY IRQ */
- spi_tms570_drv->spi->INT0 = 0x00;
- spi_tms570_drv->spi->FLG = 0x00;
- dummy_read = spi_tms570_drv->spi->BUF;
+ iface->reg->INT0 = 0x00;
+ iface->reg->FLG = 0x00;
+ dummy_read = iface->reg->BUF;
// FIXME "INT |= " with disabled IRQ ??
return;
}
- spi_tms570_drv->txcnt = 0;
- spi_tms570_drv->rxcnt = 0;
- cs = spi_tms570_drv->spi_devs[msg->addr].cs;
- spi_tms570_drv->transfer_ctrl =
+ iface->txcnt = 0;
+ iface->rxcnt = 0;
+ cs = iface->spi_devs[msg->addr].cs;
+ iface->transfer_ctrl =
(cs & 0xff) << 16
- | (spi_tms570_drv->spi_devs[msg->addr].wdel & 0x1) << 26
- | (spi_tms570_drv->spi_devs[msg->addr].cshold & 0x1) << 28
- | (spi_tms570_drv->spi_devs[msg->addr].dfsel & 0x3) << 24;
+ | (iface->spi_devs[msg->addr].wdel & 0x1) << 26
+ | (iface->spi_devs[msg->addr].cshold & 0x1) << 28
+ | (iface->spi_devs[msg->addr].dfsel & 0x3) << 24;
/* GPIO CS -- setting the multiplexer */
if (cs > 0xff) {
}
rq_len = msg->rq_len;
- rxcnt = spi_tms570_drv->rxcnt;
- txcnt = spi_tms570_drv->txcnt;
+ rxcnt = iface->rxcnt;
+ txcnt = iface->txcnt;
/* RX/TX transfers */
do {
/* Receive all the incoming data */
- while (spi_tms570_drv->spi->FLG & SPI_FLG_RXINT_m) {
- rx_data = spi_tms570_drv->spi->BUF;
+ while (iface->reg->FLG & SPI_FLG_RXINT_m) {
+ rx_data = iface->reg->BUF;
- if (msg->rx_buf && (rxcnt < rq_len))
+ if (msg->rx_buf && (rxcnt < rq_len)) {
+ /* This relies on all FMTs having 8 bit CHARLEN */
msg->rx_buf[rxcnt++] = rx_data & 0xFF;
- //FIXME how to make sure we got only 8 bits
- else
+ } else
rxcnt++;
}
while (1) {
/* Tx buffer full or nothing to send */
stop_fl = ((txcnt >= rq_len) ||
- (!(spi_tms570_drv->spi->FLG & SPI_FLG_TXINT_m)));
+ (!(iface->reg->FLG & SPI_FLG_TXINT_m)));
if (stop_fl)
break;
/* Make it possible to write "empty data"
for "read transfers" */
- if (msg->tx_buf)
+ if (msg->tx_buf) {
+ /* This relies on all FMTs having 8 bit CHARLEN */
val_to_wr = msg->tx_buf[txcnt++];
- else {
+ } else {
val_to_wr = 0x00;
txcnt++;
}
- if (txcnt == rq_len) /* Disable CS for the last byte of the transfer */
- spi_tms570_drv->transfer_ctrl &= ~SPI_DAT1_CSHOLD_m;
+ if (txcnt == rq_len) /* Disable CS after last byte of the transfer */
+ iface->transfer_ctrl &= ~SPI_DAT1_CSHOLD_m;
- spi_tms570_drv->spi->DAT1 =
- (uint32_t)(spi_tms570_drv->transfer_ctrl | val_to_wr);
+ iface->reg->DAT1 =
+ (uint32_t)(iface->transfer_ctrl | val_to_wr);
/* We just received something */
- if (spi_tms570_drv->spi->FLG & SPI_FLG_RXINT_m)
+ if (iface->reg->FLG & SPI_FLG_RXINT_m)
break;
}
} while (!stop_fl);
- spi_tms570_drv->rxcnt = rxcnt;
- spi_tms570_drv->txcnt = txcnt;
+ iface->rxcnt = rxcnt;
+ iface->txcnt = txcnt;
if ((rxcnt >= rq_len) ||
(!msg->rx_buf && (txcnt >= rq_len) &&
- !(spi_tms570_drv->spi->FLG & SPI_FLG_RXINT_m))) { // FIXME
+ !(iface->reg->FLG & SPI_FLG_RXINT_m))) { // FIXME
/* Sending of the message successfully finished */
spi_isr_lock(saveif);
spi_rq_queue_del_item(msg);
msg->flags |= SPI_MSG_FINISHED;
- spi_tms570_drv->spi_drv.msg_act = NULL;
+ iface->spi_drv.msg_act = NULL;
spi_isr_unlock(saveif);
if (msg->callback)
- msg->callback(&spi_tms570_drv->spi_drv,
+ msg->callback(&iface->spi_drv,
SPI_MSG_FINISHED, msg);
continue;
}
if (txcnt < rq_len)
- spi_tms570_drv->spi->INT0 = SPI_INT0_TXINTENA_m;
+ iface->reg->INT0 = SPI_INT0_TXINTENA_m;
else
- spi_tms570_drv->spi->INT0 = SPI_INT0_RXINTENA_m;
+ iface->reg->INT0 = SPI_INT0_RXINTENA_m;
} while (1);
}