-/*
- * fray.c
+/* Copyright (C) 2012-2013 Czech Technical University in Prague
*
- * Created on: 12.2.2013
- * Author: Michal Horn
- * Martin Zeman
+ * Authors:
+ * - Michal Horn <hornmich@fel.cvut.cz>
+ * - Martin Zeman
*
- * This file contains function for getting fray status as spi respons
- * and functions for FlexRay initialization and usage.
- * FlexRay chips on SPI are read only.
- */
-
-//#include "drv_fray.h"
-#include "drv/drv.h"
-
-/** Prepared spi command */
-uint32_t fray_spi_cmd = FRAY_SPICMD_INIT_VAL;
-/** Shadow variable used during command sending */
-uint32_t fray_spi_cmd_sh;
-/** Array of responses for each fray driver */
-uint32_t fray_spi_resp[FRAY_NUM_PORTS];
-/** Array of port names to be easily accessible by indexing */
-const char* fray_port_names[FRAY_NUM_PORTS] = { PORT_NAME_FRAY1, PORT_NAME_FRAY2 };
-
-/**
- * @brief Function sends prepared command on SPI and stores response
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
*
- * @param[in] port Index of flexray 0 or 1
- * @return 0 when success, -1 when bad parameter
- */
-int fray_spi_transfer(uint8_t port) {
- uint32_t commands[2];
- port_desc_t* desc;
-
- if (port > FRAY_NUM_PORTS) return -1;
- desc = hal_port_get_dsc(fray_port_names[port], -1);
- fray_spi_cmd_sh = fray_spi_cmd;
- commands[0] = (fray_spi_cmd_sh & 0xFF00) >> 8;
- commands[1] = (fray_spi_cmd_sh & 0xFF);
-
- fray_spi_resp[port] = desc->port_setfnc_ptr(desc->config, desc->numValues, commands);
- return 0;
-}
-
-/**
- * @brief Returns last spi response of selected fray port
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
*
- * @param[in] port Index of flexray 0 or 1
- * @return spi response or -1 when bad parameter
- */
-int fray_spi_response(uint8_t port) {
- if (port > FRAY_NUM_PORTS) return -1;
- return fray_spi_resp[port];
-}
-
-/**
- * @brief Returns last spi command of selected fray port
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
*
- * @param[in] port Index of flexray 0 or 1
- * @return spi command or -1 when bad parameter
- */
-int fray_spi_get_cmd(uint8_t port) {
- if (port > FRAY_NUM_PORTS) return -1;
- return fray_spi_cmd;
-}
-
-/** @fn clear_msg_ram(void)
-* @brief Clears FRAY message RAMs
-*
-* Send command to POC to set all bits of message RAM to 0.
-* @return SUCCESS or FAILURE when command was not accepted
-*/
-int fray_clear_msg_ram() {
- fray_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_CLEAR_RAMS;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted) {
- return FAILURE;
- }
- fray_wait_for_POC_ready();
- return SUCCESS;
-}
-
-/** @fn wait_for_POC_ready(void)
-* @brief Wait until POC is not busy
-*/
-void fray_wait_for_POC_ready() {
- // Wait for PBSY bit to clear - POC not busy.
- // 1: Signals that the POC is busy and cannot accept a command from the host. CMD(3-0) is locked against write accesses.
- while(((frayREG->SUCC1_UN.SUCC1_UL) & 0x00000080) != 0);
-}
-
-/** @fn fray_init(cfg *Fr_ConfigPtr)
-* @brief Set global configuration
-*
-* Copy configuration filled in structure into config registers
-* @param Fr_ConfigPtr Pointer to structure with configuration
-*/
-void fray_init(const cfg *Fr_ConfigPtr)
-{
- frayREG->SUCC1_UN.SUCC1_UL = 0x0C401000; // Keep default value
- frayREG->MRC_UN.MRC_UL = Fr_ConfigPtr->mrc;
- frayREG->PRTC1_UN.PRTC1_UL = Fr_ConfigPtr->prtc1;
- frayREG->PRTC2_UN.PRTC2_UL = Fr_ConfigPtr->prtc2;
- frayREG->MHDC_UN.MHDC_UL = Fr_ConfigPtr->mhdc;
- frayREG->GTUC1_UN.GTUC1_UL = Fr_ConfigPtr->gtu1;
- frayREG->GTUC2_UN.GTUC2_UL = Fr_ConfigPtr->gtu2;
- frayREG->GTUC3_UN.GTUC3_UL = Fr_ConfigPtr->gtu3;
- frayREG->GTUC4_UN.GTUC4_UL = Fr_ConfigPtr->gtu4;
- frayREG->GTUC5_UN.GTUC5_UL = Fr_ConfigPtr->gtu5;
- frayREG->GTUC6_UN.GTUC6_UL = Fr_ConfigPtr->gtu6;
- frayREG->GTUC7_UN.GTUC7_UL = Fr_ConfigPtr->gtu7;
- frayREG->GTUC8_UN.GTUC8_UL = Fr_ConfigPtr->gtu8;
- frayREG->GTUC9_UN.GTUC9_UL = Fr_ConfigPtr->gtu9;
- frayREG->GTUC10_UN.GTUC10_UL = Fr_ConfigPtr->gtu10;
- frayREG->GTUC11_UN.GTUC11_UL = Fr_ConfigPtr->gtu11;
- frayREG->SUCC2_UN.SUCC2_UL = Fr_ConfigPtr->succ2;
- frayREG->SUCC3_UN.SUCC3_UL = Fr_ConfigPtr->succ3;
- frayREG->SUCC1_UN.SUCC1_ST.txst_B1 = 1;
- frayREG->SUCC1_UN.SUCC1_ST.txsy_B1 = 1;
-}
-
-/**
- * Fill buffer configuration data structure with given data and transfer it to the message RAM header.
- * @param[in] buf_num number of buffer to be configured (0-128)
- * @param[in] mode Flag array for buffer configuration. Flags are defined in header file with prefix FRAY_BUF_
- * @param[in] cyc_filter Setting for cycle filter. 0 - disabled
- * @param[in] frame_id Id of the frame to be associated with the buffer
- * @param[in] payload Maximum data size in half-word
- * @param[in] data_pointer Address of the first word of data in buffer
- */
-void fray_config_buffer(uint32_t buf_num, uint8_t mode, uint32_t cyc_filter, uint32_t frame_id, uint32_t payload, uint32_t data_pointer) {
- wrhs Fr_LPdu;
- bc Fr_LSdu;
- Fr_LPdu.mbi = (mode&FRAY_BUF_MBI_EN) ? 1 : 0; // message buffer interrupt
- Fr_LPdu.txm = (mode&FRAY_BUF_TX_MODE_CONTINUOUS) ? 1 : 0; // transmission mode(0=continuous mode, 1=single mode)
- Fr_LPdu.ppit = (mode&FRAY_BUF_NM_EN) ? 1 : 0; // network management Enable
- Fr_LPdu.cfg = (mode&FRAY_BUF_TX) ? 1 : 0; // message buffer configuration bit (0=RX, 1 = TX)
- Fr_LPdu.chb = (mode&FRAY_BUF_CHB_EN) ? 1 : 0; // Ch B
- Fr_LPdu.cha = (mode&FRAY_BUF_CHA_EN) ? 1 : 0; // Ch A
- Fr_LPdu.cyc = cyc_filter; // Cycle Filtering Code (no cycle filtering)
- Fr_LPdu.fid = frame_id; // Frame ID
-
- // Write Header Section 2 (WRHS2)
- Fr_LPdu.pl = payload; // Payload Length
-
- // Write Header Section 3 (WRHS3)
- Fr_LPdu.dp = data_pointer; // Pointer to start of data in message RAM
-
- Fr_LPdu.sfi = (mode&FRAY_BUF_SFI_EN) ? 1 : 0; // startup frame indicator
- Fr_LPdu.sync = (mode&FRAY_BUF_SYNC_EN) ? 1 : 0; // sync frame indicator
-
- // Write Header Section 2 (WRHS2)
- Fr_LPdu.crc = (mode&FRAY_BUF_TX) ? fray_header_crc_calc(&Fr_LPdu) : 0;
-
- // Input buffer configuration
- Fr_LSdu.ibrh = buf_num; // input buffer number
- Fr_LSdu.ibsyh = 1; // check for input buffer busy host
- Fr_LSdu.ibsys = 1; // check for input buffer busy shadow
-
- Fr_LSdu.stxrh= 0; // set transmission request
- Fr_LSdu.ldsh = 0; // load data section
- Fr_LSdu.lhsh = 1; // load header section
- Fr_LSdu.obrs = 0; // output buffer number
- Fr_LSdu.rdss = 0; // read data section
- Fr_LSdu.rhss = 0; // read header section
-
- fray_prepare_LPdu(&Fr_LPdu);
- fray_transmit_tx_LPdu(&Fr_LSdu);
-}
-
-/**
- * Initialize POC. At first go to CONFIG state, then run the unlock sequence
- * and at the end go to READY state
- * @return SUCCESS or FAILURE
- */
-int fray_controler_init() {
- int result = SUCCESS;
- // write SUCC1 configuration
- frayREG->SUCC1_UN.SUCC1_UL = 0x0F1FFB00 | CMD_CONFIG;
- // Check if POC has accepted last command
- if ((frayREG->SUCC1_UN.SUCC1_UL & 0xF) == 0x0) return 1;
- // Wait for PBSY bit to clear - POC not busy
- fray_wait_for_POC_ready();
-
- // unlock CONFIG and enter READY state
- frayREG->LCK_UN.LCK_ST.clk_B8=0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8=0x31;
- // write SUCC1 configuration
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4=(0xFB00 | CMD_READY);
- // Check if POC has accepted last command
- if ((frayREG->SUCC1_UN.SUCC1_UL & 0xF) == 0x0) {
- result = FAILURE;
- }
- // Wait for PBSY bit to clear - POC not busy
- fray_wait_for_POC_ready();
- return result;
-}
-
-/**
- * Enable IRQ on int1
- * Enable CYCSE interrupt
- * Clear Errors and statuses
- */
-void fray_init_irq() {
- frayREG->EIR_UN.EIR_UL = 0xFFFFFFFF; // Clear Error Int.
- frayREG->SIR_UN.SIR_UL = 0xFFFFFFFF; // Clear Status Int.
- frayREG->SILS_UN.SILS_UL = 0x00000000; // all Status Int. to eray_int0
- frayREG->SIER_UN.SIER_UL = 0xFFFFFFFF; // Disable all Status Int.
- frayREG->SIES_UN.SIES_UL = 0x00000004; // Enable CYCSE Int.
- frayREG->ILE_UN.ILE_UL = 0x00000002; // enable eray_int1
-}
-
-/**
- * Load data to message buffer.
- * @param[in] buf_num Number of buffer
- * @param[in] data Pointer to data array
- * @param[in] len Number of words to be loaded from data to buffer
- */
-void fray_buffer_set_data(uint32_t buf_num, const uint32_t* data, uint32_t len) {
- bc write_buffer;
- uint32_t i;
-
- write_buffer.ibrh = buf_num; // input buffer number
- write_buffer.stxrh= 1; // set transmission request
- write_buffer.ldsh = 1; // load data section
- write_buffer.lhsh = 0; // load header section
- write_buffer.ibsys = 0; // check for input buffer busy shadow
- write_buffer.ibsyh = 1; // check for input buffer busy host
- for (i = 0; i < len; i++) {
- frayREG->WRDS[i] = data[i];
- }
- fray_transmit_tx_LPdu(&write_buffer);
-}
-
-/**
- * Retrieve data from message buffer.
- * @param[in] buf_num Number of buffer
- * @param[out] data Pointer to array, where retrieved data will be stored.
- * @param[in] len Number of words to be loaded from data to buffer
- */
-void fray_buffer_get_data(uint32_t buf_num, uint32_t* data, uint32_t len) {
- bc read_buffer;
- uint32_t i;
-
- read_buffer.obrs=buf_num; // output buffer number
- read_buffer.rdss=1; // read data section
- read_buffer.rhss=0; // read header section
- fray_receive_rx_LPdu(&read_buffer);
- for (i = 0; i < len; i++) {
- data[i] = frayREG->RDDS[i];
- }
-}
-
-
-/**
- * Wait for interrupt flag, that new communication cycle started
- * Clears status flags
- */
-void fray_wait_for_new_cycle() {
- frayREG->SIR_UN.SIR_UL = 0xFFFFFFFF; // clear all status int. flags
- while ((frayREG->SIR_UN.SIR_UL & 0x4) == 0x0); // wait for CYCS interrupt flag
- frayREG->SIR_UN.SIR_UL = 0xFFFFFFFF; // clear all status int. flags
-}
-
-/**
- * Check if some new message was received to the message buffer.
- * @param[in] buf_num Number of the buffer to be checked
- * @return 1 when new message is available, otherwise 0
- */
-int fray_buffer_message_received(uint32_t buf_num) {
- uint32_t ndat;
- uint32_t offset = 0;
- if (buf_num < 32) {
- ndat = frayREG->NDAT1_UN.NDAT1_UL;
- offset = buf_num;
- }
- else if (buf_num < 64) {
- ndat = frayREG->NDAT2_UN.NDAT2_UL;
- offset = buf_num - 32;
- }
- else if (buf_num < 96) {
- ndat = frayREG->NDAT3_UN.NDAT3_UL;
- offset = buf_num - 64;
- }
- else if (buf_num < 128) {
- ndat = frayREG->NDAT4_UN.NDAT4_UL;
- offset = buf_num - 96;
- }
- else {
- return -1;
- }
-
- return (ndat&(1<<offset));
-}
-
-/**
- * Process the FlexRay startup procedure according diagrams in FlexRay protocol specification.
- * @param[in] is_coldstar Specifies if node is coldstart or if it can be just integrated to existing network
- * @return SUCCESS or error code
- */
-int fray_startup_procedure(int is_coldstart) {
- uint32_t counter;
- uint32_t state_value;
- uint32_t csa;
- int ok = SUCCESS;
-
- ok = fray_go_to_ready_state_from_config_state();
- if(ok == FAILURE) {
- return FRAY_ERR_SW_CFG_READY; // Switching to ready state error
- }
- else {
- // Cold start branch
- if (is_coldstart){
- // Start up loop
- while(1) {
- counter = 0;
- // try as following cold starter
- ok = fray_go_to_startup_state();
- if(ok == FAILURE){
- return FRAY_ERR_SW_STUP_FOLLOW; // Switch to run error
- }
- // Wait until NORMAL_ACTIVE state or timeout
- do {
- state_value = frayREG->CCSV_UN.CCSV_ST.pocs_B6;
- counter++;
- } while ((state_value != 0x02) && (counter < 10000000U));
-
- // No success in integration
- if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 == 0x27){
- csa = frayREG->CCSV_UN.CCSV_ST.rca_B5;
- // Some cold starts attempts remains
- if (csa != 0){
- // Try allow cold start
- ok = fray_allow_coldstart();
- if(ok == FAILURE){
- return FRAY_ERR_CSINH_DIS; // Cold start inhibit disabled error
- }
- }
- }
-
- // Wait until NORMAL_ACTIVE or INTEGRATION_LISTEN state
- do {
- state_value = frayREG->CCSV_UN.CCSV_ST.pocs_B6;
- } while ( (state_value != 0x02) && (state_value != 0x27));
-
- // Success, break the start up loop
- if (frayREG->CCSV_UN.CCSV_ST.pocs_B6 == 0x02)
- break;
-
- // No success. Switch back to READY state
- fray_delay();
- ok = fray_go_to_ready_state_from_startup_state();
- if (ok == FAILURE) {
- return FRAY_ERR_SW_STUP_READY; // Switch to READY failed
- }
- }
- }
- // Non-cold start branch
- else {
- ok = fray_go_to_startup_state();
- if(ok == FAILURE) {
- return FRAY_ERR_SW_STUP_AS_NCOLD; // Switching to startup state as non-cold start node
- }
- else {
- // Wait until NORMAL_ACTIVE
- do {
- state_value = frayREG->CCSV_UN.CCSV_ST.pocs_B6;
- } while (state_value != 0x02);
- }
- }
- }
- if (ok != SUCCESS)
- return FAILURE;
- return SUCCESS;
-}
-
-/** @fn go_to_ready_state_from_config_state(void)
-* @brief Set POC command
-*
-* Send command to POC to switch into READY state.
-* @return SUCCESS or FAILURE
-*/
-int fray_go_to_ready_state_from_config_state(void) {
- fray_wait_for_POC_ready();
-
- if (frayREG->SUCC1_UN.SUCC1_ST.ccha_B1 && frayREG->SUCC1_UN.SUCC1_ST.cchb_B1){
- //odemykaci sekvence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
- //odemykaci sekvence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.mtsa_B1 = 1U;
- //odemykaci sekvence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.mtsb_B1 = 1U;
- }
- else if(frayREG->SUCC1_UN.SUCC1_ST.ccha_B1){
- //odemykaci sekvence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
- //odemykaci sekvence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.mtsa_B1 = 1U;
- }
- else if (frayREG->SUCC1_UN.SUCC1_ST.cchb_B1){
- //odemykaci sekvence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
- //odemykaci sekvence
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0xCE;
- frayREG->LCK_UN.LCK_ST.clk_B8 = 0x31;
- frayREG->SUCC1_UN.SUCC1_ST.mtsb_B1 = 1U;
- }
- else frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
-
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return (FAILURE);
- while ((frayREG->CCSV_UN.CCSV_UL & 0x0000003F) != 0x01)
- ; //cekam dokud POC neni v ready stavu
- return (SUCCESS);
-}
-
-/** @fn go_to_ready_state_from_startup_state(void)
-* @brief Set POC command
-*
-* Send command to POC to switch into READY state.
-* @return SUCCESS or FAILURE
-*/
-int fray_go_to_ready_state_from_startup_state(void){
- fray_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_READY;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted) return (FAILURE);
- while ((frayREG->CCSV_UN.CCSV_UL & 0x0000003F) != 0x01); //cekam dokud POC neni v ready stavu
- return (SUCCESS);
-}
-
-/** @fn go_to_startup_state(void)
-* @brief Set POC command
-*
-* Send command to POC to switch into RUN state.
-* @return SUCCESS or FAILURE
-*/
-int fray_go_to_startup_state(void) {
- fray_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_RUN;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return (FAILURE);
- return (SUCCESS);
-}
-
-/** @fn allow_coldstart(void)
-* @brief Allows cold start
-*
-* Send command to erase coldstart inhibit flag.
-* This allows the node to start as coldstart node.
-* @return SUCCESS or FAILURE
-*/
-int fray_allow_coldstart(void) {
- fray_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = CMD_ALLOW_COLDSTART;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return (FAILURE);
- return (SUCCESS);
-}
-
-/**
- * FlexRay delay used while network initiation.
+ * File : fray.c
*
- * !This is busy waiting!
- */
-void fray_delay(void) {
- volatile uint32_t delayval;
-
- delayval = 375000; // 100000 are about 10ms
- while(delayval-- > 0 )
- ;
-}
-
-/** @fn send_halt_command
-* @brief Send HALT command
-*
-* Send command to the node to stop its activity after the end of
-* actual cycle.
-* @return SUCCESS or FAILURE
-*/
-int fray_halt(void) {
- fray_wait_for_POC_ready();
- frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 = 6U;
- if (frayREG->SUCC1_UN.SUCC1_ST.cmd_B4 == CMD_command_not_accepted)
- return (FAILURE);
- return (SUCCESS);
-}
-
-/**
- * Compute CRC for message RAM header data
- * @param[in] Fr_LPduPtr Pointer to header data
- * @return CRC code
+ * Abstract:
+ * This file contains function for getting fray status as spi respons
+ * and functions for FlexRay initialization and usage.
+ * FlexRay chips on SPI are read only.
*/
-int fray_header_crc_calc(const wrhs *Fr_LPduPtr) {
- unsigned int header;
- int CrcInit = 0x1A;
- int length = 20;
- int CrcNext;
- unsigned long CrcPoly = 0x385;
- unsigned long CrcReg_X = CrcInit;
- unsigned long header_temp, reg_temp;
-
- header = ((Fr_LPduPtr->sync & 0x1) << 19) | ((Fr_LPduPtr->sfi & 0x1) << 18);
- header |= ((Fr_LPduPtr->fid & 0x7FF) << 7) | (Fr_LPduPtr->pl & 0x7F);
-
- header <<= 11;
- CrcReg_X <<= 21;
- CrcPoly <<= 21;
-
- while(length--) {
- header <<= 1;
- header_temp = header & 0x80000000;
- reg_temp = CrcReg_X & 0x80000000;
-
- if(header_temp ^ reg_temp){ // Step 1
- CrcNext = 1;
- } else {
- CrcNext = 0;
- }
-
- CrcReg_X <<= 1; // Step 2
-
- if(CrcNext) {
- CrcReg_X ^= CrcPoly; // Step 3
- }
- }
-
- CrcReg_X >>= 21;
-
- return CrcReg_X;
-}
-
-/**
- * Prepare data to be transmitted to message RAM by input buffer,
- * @param[in] Fr_LPduPtr Pointer to data structure to be send
- */
-void fray_prepare_LPdu(const wrhs *Fr_LPduPtr) {
- int wrhs1;
- int wrhs2;
- wrhs1 = ((Fr_LPduPtr->mbi) & 0x1) <<29;
- wrhs1 |= (Fr_LPduPtr->txm & 0x1) << 28;
- wrhs1 |= (Fr_LPduPtr->ppit & 0x1) << 27;
- wrhs1 |= (Fr_LPduPtr->cfg & 0x1) << 26;
- wrhs1 |= (Fr_LPduPtr->chb & 0x1) << 25;
- wrhs1 |= (Fr_LPduPtr->cha & 0x1) << 24;
- wrhs1 |= (Fr_LPduPtr->cyc & 0x7F) << 16;
- wrhs1 |= (Fr_LPduPtr->fid & 0x7FF);
- frayREG->WRHS1_UN.WRHS1_UL = wrhs1;
-
- wrhs2 = ((Fr_LPduPtr->pl & 0x7F) << 16) | (Fr_LPduPtr->crc & 0x7FF);
- frayREG->WRHS2_UN.WRHS2_UL = wrhs2;
-
- frayREG->WRHS3_UN.WRHS3_UL = (Fr_LPduPtr->dp & 0x7FF);
-}
-
-/**
- * Transfer data from input buffer to message RAM
- * @param[in] Fr_LSduPtr Pointer to data structure with input buffer settings
- */
-void fray_transmit_tx_LPdu(const bc *Fr_LSduPtr) {
- // ensure nothing is pending
- while ((frayREG->IBCR_UN.IBCR_UL & 0x0008000) != 0);
- frayREG->IBCM_UN.IBCM_UL=((Fr_LSduPtr->stxrh & 0x1) << 2) | ((Fr_LSduPtr->ldsh & 0x1) << 1) | (Fr_LSduPtr->lhsh & 0x1);
- frayREG->IBCR_UN.IBCR_UL=(Fr_LSduPtr->ibrh & 0x3F);
- // optimization possible for future by not gating like below
- // wait for completion on host registers
- while ((Fr_LSduPtr->ibsyh != 0) && ((frayREG->IBCR_UN.IBCR_UL & 0x00008000) != 0));
- // wait for completion on shadow registers
- while ((Fr_LSduPtr->ibsys != 0) && ((frayREG->IBCR_UN.IBCR_UL & 0x80000000) != 0));
-}
-
-/**
- * Receive data from message buffer into output buffer.
- * @param[in] Fr_LSduPtr Pointer to data structure with output buffer settings
- */
-void fray_receive_rx_LPdu(const bc *Fr_LSduPtr) {
- // ensure no transfer in progress on shadow registers
- while (((frayREG->OBCR_UN.OBCR_UL) & 0x00008000) != 0);
- frayREG->OBCM_UN.OBCM_UL=(((Fr_LSduPtr->rdss & 0x1) << 1) | (Fr_LSduPtr->rhss & 0x1));
- frayREG->OBCR_UN.OBCR_UL=((1 << 9) | (Fr_LSduPtr->obrs & 0x3F)); //req=1, view=0
- // wait for completion on shadow registers
- while (((frayREG->OBCR_UN.OBCR_UL) & 0x00008000) != 0);
-
- frayREG->OBCM_UN.OBCM_UL=(((Fr_LSduPtr->rdss & 0x1) << 1) | (Fr_LSduPtr->rhss & 0x1));
- frayREG->OBCR_UN.OBCR_UL=((1 << 8) | (Fr_LSduPtr->obrs & 0x3F)); //req=0, view=1
-}
+//#include "drv_fray.h"
+#include "drv/drv.h"
projects / pes-rpp / rpp-lib.git / blobdiff