*
* @file spi_resp_transl.h
*
- * @copyright Copyright (C) 2012-2013 Czech Technical University in Prague
+ * @copyright Copyright (C) 2012-2013, 2015 Czech Technical University in Prague
*
* @author Michal Horn <hornmich@fel.cvut.cz>
+ *
+ * This document contains proprietary information belonging to Czech
+ * Technical University in Prague. Passing on and copying of this
+ * document, and communication of its contents is not permitted
+ * without prior written authorization.
*/
#ifndef _MYSPI_H_
#define _MYSPI_H_
-//#include "sys_common.h"
-//#include "drv_spi.h"
-#include "ul/ul_list.h"
#include "types.h"
#include "sys/cpu_def.h"
-
-#define SPI_IFC_ON 1
-#define SPI_CTRL_WAKE_RQ 1
+#include "drv/spi.h"
/* ------------------------------------------------------------------------- */
-#define SPI_MSG_FINISHED 0x040
-#define SPI_MSG_ABORT 0x020
-#define SPI_MSG_FAIL 0x010
-
#define SPI_BR_FORMAT0 1000000 /**< Clock rate for data format 0 in Hz. */
#define SPI_BR_FORMAT1 1000000 /**< Clock rate for data format 0 in Hz. */
#define SPI_BR_FORMAT2 1000000 /**< Clock rate for data format 0 in Hz. */
#define SPI_BR_FORMAT3 1000000 /**< Clock rate for data format 0 in Hz. */
-
-struct spi_drv;
-
-typedef int (spi_ctrl_fnc_t)(struct spi_drv *ifc, int ctrl, void *p);
-
-typedef struct spi_msg_head {
- uint16_t flags; // message flags
- uint16_t addr; // message destination address -- used as index into the "address translation table"*/
-
- //uint16_t size_mode; // message frame len and mode
- uint16_t rq_len; // requested transfer length
- const uint8_t *tx_buf; // pointer to TX data
- uint8_t *rx_buf; // pointer to RX data
-
- ul_list_node_t node;
- //struct spi_drv *ifc;
- int (*callback)(struct spi_drv *ifc, int code, struct spi_msg_head *msg); // Called when whole transfer is finished
- long private; // If set -- msg is processed by HW
-} spi_msg_head_t;
-
-typedef struct spi_drv {
- uint16_t flags; // Flags
- //uint16_t self_addr;
- ul_list_head_t rq_queue; // Queue containing MSG requests to process
- spi_msg_head_t *msg_act; // MSG being actually processed
- spi_ctrl_fnc_t *ctrl_fnc; // Device dependent function responsible for sending data
- //long private;
-} spi_drv_t;
-
/* ------------------------------------------------------------------------- */
typedef unsigned long spi_isr_lock_level_t;
/* ------------------------------------------------------------------------- */
-#define spi_compat_REG2 ((spiBASE_compat_t *)0xFFF7F600U)
-#define spi_compat_REG4 ((spiBASE_compat_t *)0xFFF7FA00U)
-#define mibspi_compat_REG1 ((spiBASE_compat_t *)0xFFF7F400U)
-#define mibspi_compat_REG3 ((spiBASE_compat_t *)0xFFF7F800U)
-#define mibspi_compat_REG5 ((spiBASE_compat_t *)0xFFF7FC00U) /* NOT USED ON RPP BOARD */
-
-
-#define SPI_FLG_TXINT_m (1 << 9)
-#define SPI_FLG_RXINT_m (1 << 8)
-
-#define SPI_INT0_TXINTENA_m (1 << 9)
-#define SPI_INT0_RXINTENA_m (1 << 8)
-
-#define SPI_DAT1_CSHOLD_m (1 << 28)
-
/* Used as CSNR in DATA1 reg */
enum spiChipSelect {
SPI_CS_NONE = 0x00FF,
SPI_CS_5 = 0x00DF,
SPI_CS_6 = 0x00BF,
SPI_CS_7 = 0x007F,
+#if defined(TARGET_TMS570_RPP)
SPI_CS_DMM0 = 0x0100,
SPI_CS_DMM1 = 0x0200,
SPI_CS_DMM2 = 0x0400
-};
-
-
-
-typedef volatile struct spiBase {
- uint32_t GCR0; /**< 0x0000: Global Control 0 */
-#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
- uint32_t GCR1 : 8U; /**< 0x0007: Global Control 1 */
- uint32_t PD : 1U; /**< 0x0006: Power down bit */
- uint32_t : 7U;
- uint32_t LB : 1U; /**< 0x0005: Loop back bit */
- uint32_t : 7U;
- uint32_t ENA : 1U; /**< 0x0004: SPI Enable bit */
- uint32_t : 7U;
- uint32_t INT0 : 16U; /**< 0x000A: Interrupt Enable bits */
- uint32_t DMAREQEN : 1U; /**< 0x0009: DMA Request enable */
- uint32_t : 7U;
- uint32_t ENAHIGHZ : 1U; /**< 0x0008: Enable HIGHZ outputs */
- uint32_t : 7U;
-#else
- uint32_t : 7U;
- uint32_t ENA : 1U; /**< 0x0004: SPI Enable bit */
- uint32_t : 7U;
- uint32_t LB : 1U; /**< 0x0005: Loop back bit */
- uint32_t : 7U;
- uint32_t PD : 1U; /**< 0x0006: Power down bit */
- uint32_t GCR1 : 8U; /**< 0x0007: Global Control 1 */
- uint32_t : 7U;
- uint32_t ENAHIGHZ : 1U; /**< 0x0008: Enable HIGHZ outputs */
- uint32_t : 7U;
- uint32_t DMAREQEN : 1U; /**< 0x0009: DMA Request enable */
- uint32_t INT0 : 16U; /**< 0x000A: Interrupt Enable bits */
#endif
- uint32_t LVL; /**< 0x000C: Interrupt Level */
-#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
- uint32_t FLG : 16U; /**< 0x0012: Interrupt flags */
- uint32_t : 8U;
- uint32_t BUFINIT : 1U; /**< 0x0010: Buffer initialization active flag */
- uint32_t : 7U;
-#else
- uint32_t : 7U;
- uint32_t BUFINIT : 1U; /**< 0x0010: Buffer initialization active flag */
- uint32_t : 8U;
- uint32_t FLG : 16U; /**< 0x0012: Interrupt flags */
-#endif
- uint32_t PCFUN; /**< 0x0014: Function Pin Enable */
- uint32_t PCDIR; /**< 0x0018: Pin Direction */
- uint32_t PCDIN; /**< 0x001C: Pin Input Latch */
- uint32_t PCDOUT; /**< 0x0020: Pin Output Latch */
- uint32_t PCSET; /**< 0x0024: Output Pin Set */
- uint32_t PCCLR; /**< 0x0028: Output Pin Clr */
- uint32_t PCPDR; /**< 0x002C: Open Drain Output Enable */
- uint32_t PCDIS; /**< 0x0030: Pullup/Pulldown Disable */
- uint32_t PCPSL; /**< 0x0034: Pullup/Pulldown Selection */
- uint32_t DAT0; /**< 0x0038: Transmit Data */
- uint32_t DAT1; /**< 0x003C: Transmit Data with Format and Chip Select */
- uint32_t BUF; /**< 0x0040: Receive Buffer */
- uint32_t EMU; /**< 0x0044: Emulation Receive Buffer */
- uint32_t DELAY; /**< 0x0048: Delays */
- uint32_t CSDEF; /**< 0x004C: Default Chip Select */
- uint32_t FMT0; /**< 0x0050: Data Format 0 */
- uint32_t FMT1; /**< 0x0054: Data Format 1 */
- uint32_t FMT2; /**< 0x0058: Data Format 2 */
- uint32_t FMT3; /**< 0x005C: Data Format 3 */
- uint32_t INTVECT0; /**< 0x0060: Interrupt Vector 0 */
- uint32_t INTVECT1; /**< 0x0064: Interrupt Vector 1 */
- uint32_t SRSEL; /**< 0x0068: Slew Rate Select */
-
- uint32_t PMCTRL; /**< 0x006C: Parallel Mode Control */
-#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
- uint32_t MIBSPIE : 16U; /**< 0x0072: MibSPI Enable */
- uint32_t RAMACCESS : 16U; /**< 0x0070: RX Ram Write Access Enable */
-#else
- uint32_t RAMACCESS : 16U; /**< 0x0070: RX Ram Write Access Enable */
- uint32_t MIBSPIE : 16U; /**< 0x0072: MibSPI Enable */
-#endif
-
- uint32_t RESERVED[48U]; /**< 0x006C to 0x0130: Reserved */
- uint32_t IOLPKTSTCR; /**< 0x0134: IO loopback */
-} spiBASE_compat_t;
+};
+enum spi_iface {
+ SPI_IFACE1,
+ SPI_IFACE2,
+ SPI_IFACE3,
+ SPI_IFACE4,
+ SPI_IFACE5,
+};
/* SPI devices connected to SPI interface */
typedef struct spi_dev {
+ enum spi_iface iface;
unsigned int cs; /* Combination of CS (+GPIO CS) necessary to enable the device */
- unsigned char dfsel; /* Data word format */
+ unsigned char dfsel; /* Data word format (FMTx registers) */
unsigned char wdel; /* Enable the delay counter at the end of the current transaction */
unsigned char cshold; /* Chip select hold mode */
unsigned int dlen; /* Data len needed for one complete transfer */
} spi_dev_t;
-/* SPI interface */
-typedef struct spi_tms570_drv {
- spi_drv_t spi_drv;
- spiBASE_compat_t *spi; /* Base Reg. for SPI device register array */
- unsigned txcnt; /* No. of transfered bytes for msg_act */
- unsigned rxcnt; /* No. of received bytes for msg_act */
- spi_dev_t *spi_devs; /* Pointer to table holding information about SPI devices bound to the interface */
- uint32_t transfer_ctrl; /* Transfer configuration -- upper 16 bits of SPIDAT1 register */
-} spi_tms570_drv_t;
+extern const spi_dev_t spi_devs[_SPIDEV_COUNT];
+
+typedef struct spi_tms570_iface spi_tms570_iface_t;
-//extern spi_tms570_drv_t spi_tms570_ifcs[4];
-//extern spi_dev_t spi_devs[];
-int spi_tms570_init(void);
+spi_drv_t *spi_tms570_get_iface(enum spi_device dev);
-spi_drv_t *spi_find_drv(char *name, int number);
+void spi_tms570_init();
+int spi_msg_rq_ins(spi_msg_t *msg);
#endif /* _MYSPI_H_ */
projects / pes-rpp / rpp-lib.git / blobdiff