- #if rppCONFIG_DRV == 1
- /// Setup pins
- if(config_changed) {
- uint16_t sp = 0x0;
- uint16_t sg = 0x0;
-
- // Set pull-type.
- // In DRV logic is inverted:
- // DRV: 1 - set pin as switch-to-battery. RPP: 0 - pull-down.
- // DRV: 0 - set pin as switch-to-ground. RPP: 1 - pull-up.
- // Also DRV is MSB and not LSB:
- // DRV: [SP0,...,SP7]. RPP: [SG7,...,SG0][SP7,...,SP0].
- din_set_pr(lsb_msb((uint8_t) ~(pull_cache & 0xFF)));
- din_spi_transfer();
-
- // Set state type, active or tri-stated.
- // In DRV logic is inverted:
- // DRV: 1 - tri-state. RPP: 0 - tri-state.
- // DRV: 0 - active. RPP: 1 - active.
- // Also DRV is MSB and not LSB:
- // DRV: SP - [SP0,...,SP7,X8,...,X15]. RPP: SG/SP - [SG7,...,SG0][SP7,...,SP0].
- // DRV: SG - [SG0,...,SG13,..., X15]. RPP: SG/SP - [SG7,...,SG0][SP7,...,SP0].
- sp = (((uint16_t) lsb_msb(~((uint8_t) (active_cache & 0xFF)))) << 8) | 0x00FF;
- sg = (((uint16_t) lsb_msb(~((uint8_t) (active_cache >> 8 )))) << 8) | 0x00FF;
- // Debug help (on sg):
- // 1) Extract the SG bits from active_cache by shifting 8 bits to the right.
- // 2) Convert that 0b00000000xyyyyyyz 16bits number to a 8 bits number 0bxyyyyyyz.
- // 3) Bit negate that 8 bit number to match inverted logic in DRV 0bijjjjjjk.
- // 4) Convert from LSB (as in RPP) to MSB (as in DRV) using lsb_msb.
- // 0bkjjjjjji
- // 5) Convert back this 8bit number to 16bits number and shift 8 bits to the left:
- // 0bkjjjjjji00000000
- // 6) SG8-SG13 should always be tri-stated ('1') as they are not connected on the board.
- // 0bkjjjjjji11111111
- din_set_stat(sp, sg);
- din_spi_transfer();
-
- // Set wake / interrupt.
- // IN DRV logic is not inverted.
- // DRV: 1 - can wake. RPP: 1 - can wake.
- // DRV: 0 - interrupt disabled. RPP: 0 - interrupt disabled.
- // But DRV is MSB and not LSB:
- // DRV: SP - [SP0,...,SP7,X8,...,X15]. RPP: SG/SP - [SG7,...,SG0][SP7,...,SP0].
- // DRV: SG - [SG0,...,SG13,..., X15]. RPP: SG/SP - [SG7,...,SG0][SP7,...,SP0].
- sp = (((uint16_t) lsb_msb((uint8_t) (can_wake_cache & 0xFF))) << 8) & 0xFF00;
- sg = (((uint16_t) lsb_msb((uint8_t) (can_wake_cache >> 8 ))) << 8) & 0xFF00;
- // Debug help (on sg):
- // 1) Extract the SG bits from active_cache by shifting 8 bits to the right.
- // 2) Convert that 0b00000000xyyyyyyz 16bits number to a 8 bits number 0bxyyyyyyz.
- // 3) Convert from LSB (as in RPP) to MSB (as in DRV) using lsb_msb.
- // 0bzyyyyyyx
- // 4) Convert back this 8bit number to 16bits number and shift 8 bits to the left:
- // 0bzyyyyyyx00000000
- // 5) SG8-SG13 should always be non-interrupt ('0') as they are not connected on the board.
- // 0bzyyyyyyx00000000
- din_set_int(sp, sg);
- din_spi_transfer();
-
- // Mark configuration as commited
- config_changed = FALSE;
- }
-
- // Update cached values
- din_switch_st();
- din_spi_transfer();
- in_cache = din_get_val_word();
-
- // FIXME: Implement. Dummy assign for now.
- diag_cache = in_cache;
-
- if(diag_cache != in_cache) {
- return FAILURE;
- }
- #else
- UNUSED(config_changed);
- UNUSED(lsb_msb);
- #endif
-
- return SUCCESS;
+ RPP_MUTEX_LOCK(mutex_din);
+#ifndef FREERTOS_POSIX
+ /// Setup pins
+ if (config_changed) {
+ uint16_t sp = 0x0;
+ uint16_t sg = 0x0;
+
+ // Reset chip
+ din_set_reg(DIN_RESET_CMD, 0, 0);
+ //rpp_sci_printf("din_reset()\r\n");
+
+ // Set pull-type.
+ // In DRV logic is inverted:
+ // DRV: 1 - set pin as switch-to-battery. RPP: 0 - pull-down.
+ // DRV: 0 - set pin as switch-to-ground. RPP: 1 - pull-up.
+ sp = (~pull_cache) & 0xFF;
+ din_set_reg(DIN_SETTINGS_CMD, 0xffff, sp);
+ //rpp_sci_printf("din_set_pr(%X)\r\n", sp);
+
+ // Set state type, active or tri-stated.
+ // In DRV logic is inverted:
+ // DRV: 1 - tri-state. RPP: 0 - tri-state.
+ // DRV: 0 - active. RPP: 1 - active.
+ sp = ((~active_cache) ) & 0xFF;
+ sg = ((~active_cache) >> 8) & 0xFF;
+ din_set_reg(DIN_TRI_STATE_CMD_YES, 0xffff, sp);
+ din_set_reg(DIN_TRI_STATE_CMD_NO, 0xffff, sg);
+ //rpp_sci_printf("din_set_stat(%X, %X)\r\n", sp, sg);
+
+ // Set wake / interrupt.
+ // IN DRV logic is not inverted.
+ // DRV: 1 - can wake. RPP: 1 - can wake.
+ // DRV: 0 - interrupt disabled. RPP: 0 - interrupt disabled.
+ sp = (can_wake_cache ) & 0xFF;
+ sg = (can_wake_cache >> 8) & 0xFF;
+
+ din_set_reg(DIN_WAKE_UP_CMD_ENB, 0xffff, sp);
+ din_set_reg(DIN_WAKE_UP_CMD_DIS, 0xffff, sg);
+ //rpp_sci_printf("din_set_int(%X, %X)\r\n", sp, sg);
+
+ // Mark configuration as commited
+ config_changed = FALSE;
+ }
+
+ // Update cached values
+ din_set_reg(DIN_SWITCH_STATUS_CMD, 0, 0);
+ in_cache = din_get_val_word();
+
+ // FIXME: Implement. Dummy assign for now.
+ diag_cache = in_cache;
+
+ if (diag_cache != in_cache) {
+ RPP_MUTEX_UNLOCK(mutex_din);
+ return FAILURE;
+ }
+
+ #else /* ifndef FREERTOS_POSIX */
+ UNUSED(config_changed);
+ #endif /* ifndef FREERTOS_POSIX */
+
+ RPP_MUTEX_UNLOCK(mutex_din);
+ return SUCCESS;