;---------------------------------------------------------------------------------
; To compile place hetp.exe to same folder as this file and run: `hetp.exe irc.het`
;---------------------------------------------------------------------------------
; Pseudocode:
;	function resolveIRC(Reg, bitSelect, IRC_data) {
;		if (Reg & bitSelect) == 0x0 {
;			IRC_data += 1
;		} else {
;			IRC_data -= 1
;		}
;	}
;
;	if IRC1 ENABLED {
;		if pin0 RISE {
;			RegA = RegA | 0x1  // set lowest bit to 1
;			resolveIRC(RegA, 0x2, IRC1_data)
;		} else if pin2 RISE {
;			RegA = RegA | 0x2 // set second lowest bit to 1
;			RegR = RegA ^ 0x1 // bit negation
;			resolveIRC(RegR, 0x1, IRC1_data)
;		} else if pin0 FALL {
;			RegA = RegA & 0x1FFFFFE // set lowest bit to 0
;			RegR = RegA ^ 0x2 // bit negation
;			resolveIRC(RegR, 0x2, IRC1_data)
;		} else if pin2 FALL {
;			RegA = RegA & 0x1FFFFFD // set second lowest bit to 0
;			resolveIRC(RegA, 0x1, IRC1_data)
;		}
;	}
;
;	if IRC2 ENABLED {
;		if pin4 RISE {
;			RegB = RegB | 0x1  // set lowest bit to 1
;			resolveIRC(RegB, 0x2, IRC2_data)
;		} else if pin6 RISE {
;			RegB = RegB | 0x2 // set second lowest bit to 1
;			RegR = RegB ^ 0x1 // bit negation
;			resolveIRC(RegR, 0x1, IRC2_data)
;		} else if pin4 FALL {
;			RegB = RegB & 0x1FFFFFE // set lowest bit to 0
;			RegR = RegB ^ 0x2 // bit negation
;			resolveIRC(RegR, 0x2, IRC2_data)
;		} else if pin6 FALL {
;			RegB = RegB & 0x1FFFFFD // set second lowest bit to 0
;			resolveIRC(RegB, 0x1, IRC2_data)
;		}
;	}
;---------------------------------------------------------------------------------
; Assembler option
;---------------------------------------------------------------------------------
-hc32
-n5
-v2
-AID1.7
;---------------------------------------------------------------------------------
;; IRC1 disable/enable jump, cond_addr is changed with ircEnable()/ircDisable() (to L01)
L00:	BR { next=L19, cond_addr=L19, event=NOCOND }
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; IRC1 input1 rising edge
L01: 	BR { next=L02, cond_addr=L05, pin=0, event=RISE }
;; IRC1 input2 rising edge
L02: 	BR { next=L03, cond_addr=L10, pin=2, event=RISE }
;; IRC1 input1 falling edge
L03:	BR { next=L04, cond_addr=L06, pin=0, event=FALL }
;; IRC1 input2 falling edge
L04:	BR { next=L19, cond_addr=L11, pin=2, event=FALL }
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; IRC1 input1 (rising) store value
L05:	OR { next=L09, src1=A, src2=IMM, dest=A, data=1h }
;; IRC1 input1 (falling) store value
L06:	AND{ next=L07, src1=A, src2=IMM, dest=A, data=1FFFFFEh }
;; IRC1 input1 (falling) virtual input2 negation to register R
L07:	XOR { next=L08, src1=A src2=IMM, dest=R, data=2h }
;; IRC1 input1 (falling) input2 select
L08:	AND { next=L15, src1=R, src2=IMM, dest=NONE, data=2h }
;; IRC1 input1 (rising) input2 select
L09:	AND { next=L15, src1=A, src2=IMM, dest=NONE, data=2h }
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; IRC1 input2 (rising) store value
L10:	OR { next=L12, src1=A, src2=IMM, dest=A, data=2h }
;; IRC1 input2 (falling) store value
L11:	AND { next=L14, src1=A, src2=IMM, dest=A, data=1FFFFFDh }
;; IRC1 input2 (rising) virtual input2 negation to register R
L12:	XOR{ next=L13, src1=A src2=IMM, dest=R, data=1h }
;; IRC1 input2 (rising) input2 select
L13:	AND { next=L15, src1=R, src2=IMM, dest=NONE, data=1h }
;; IRC1 input2 (falling) input2 select
L14:	AND { next=L15, src1=A, src2=IMM, dest=NONE, data=1h }
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; IRC1 value edit
L15:	BR { next=L16, cond_addr=L17, event=ZERO }
L16:	SUB{ next=L19, src1=REM, src2=IMM, dest=NONE, rdest=REM, remote=L18,
		data=0, hr_data=1 }
L17:	ADD { next=L19, src1=REM, src2=IMM, dest=NONE, rdest=REM, remote=L18,
		data=0, hr_data=1 }

;; This should newer be executed. This is data reservation for IRC1
L18:	BR { next=L00, cond_addr=L00, event=NOCOND }
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; IRC2 disable/enable jump, cond_addr is changed with ircEnable()/ircDisable() (to L20)
L19:	BR { next=L00, cond_addr=L00, event=NOCOND }
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; IRC2 input1 rising edge
L20: 	BR { next=L21, cond_addr=L24, pin=4, event=RISE }
;; IRC2 input2 rising edge
L21: 	BR { next=L22, cond_addr=L29, pin=6, event=RISE }
;; IRC2 input1 falling edge
L22:	BR { next=L23, cond_addr=L25, pin=4, event=FALL }
;; IRC2 input2 falling edge
L23:	BR { next=L00, cond_addr=L30, pin=6, event=FALL }
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; IRC2 input1 (rising) store value
L24:	OR { next=L28, src1=B, src2=IMM, dest=B, data=1h }
;; IRC2 input1 (falling) store value
L25:	AND { next=L26, src1=B, src2=IMM, dest=B, data=1FFFFFEh }
;; IRC2 input1 (falling) virtual input2 negation to register R
L26:	XOR { next=L27, src1=B src2=IMM, dest=R, data=2h }
;; IRC2 input1 (falling) input2 select
L27:	AND { next=L34, src1=R, src2=IMM, dest=NONE, data=2h }
;; IRC1 input1 (rising) input2 select
L28:	AND { next=L34, src1=B, src2=IMM, dest=NONE, data=2h }
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; IRC2 input2 (rising) store value
L29:	OR { next=L31, src1=B, src2=IMM, dest=B, data=2h }
;; IRC2 input2 (falling) store value
L30:	AND { next=L33, src1=B, src2=IMM, dest=B, data=1FFFFFDh }
;; IRC2 input2 (rising) virtual input2 negation to register R
L31:	XOR { next=L32, src1=B src2=IMM, dest=R, data=1h }
;; IRC2 input2 (rising) input2 select
L32:	AND { next=L34, src1=R, src2=IMM, dest=NONE, data=1h }
;; IRC2 input2 (falling) input2 select
L33:	AND { next=L34, src1=B, src2=IMM, dest=NONE, data=1h }
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; IRC2 value edit
L34:	BR{ next=L35, cond_addr=L36, event=ZERO }
L35:	SUB { next=L00, src1=REM, src2=IMM, dest=NONE, rdest=REM, remote=L37,
		data=0, hr_data=1 }
L36:	ADD { next=L00, src1=REM, src2=IMM, dest=NONE, rdest=REM, remote=L37,
		data=0, hr_data=1 }

;; This should newer be executed. This is data reservation for IRC2
L37:	BR { next=L00, cond_addr=L00, event=NOCOND }