1 /* Copyright (C) 2013 Czech Technical University in Prague
4 * - Carlos Jenkins <carlos@jenkins.co.cr>
6 * This document contains proprietary information belonging to Czech
7 * Technical University in Prague. Passing on and copying of this
8 * document, and communication of its contents is not permitted
9 * without prior written authorization.
13 * Digital Input RPP API implementation file.
17 * RPP API documentation.
23 #ifndef FREERTOS_POSIX
27 static boolean_t initialized = FALSE;
34 #ifndef FREERTOS_POSIX
44 int8_t rpp_din_ref(uint16_t ref_a, uint16_t ref_b)
46 if ((ref_a > 4095) || (ref_b > 4095))
49 #ifndef FREERTOS_POSIX
50 drv_din_ref(ref_a, ref_b);
56 // Check for configuration changes to avoid SPI overhead
57 static boolean_t config_changed = FALSE;
59 // All cached values are 16 bits in the form [SG7,...,SG0][SP7,...,SP0]
60 static uint16_t pull_cache = 0x0; /* 0 - pull-down, 1 - pull-up */
61 static uint16_t active_cache = 0x0; /* 0 - tri-state, 1 - active */
62 static uint16_t can_wake_cache = 0x0;
64 static boolean_t check_pin_busy(uint8_t pin)
66 if (rpp_irc1_enabled && (pin == 10 || pin == 11))
68 if (rpp_irc2_enabled && (pin == 14 || pin == 15))
73 int8_t rpp_din_setup(uint8_t pin, boolean_t pull_up,
74 boolean_t active, boolean_t can_wake)
80 // Check programmable feature
81 if (!pull_up && (pin > 7))
84 // Check blockade of specific pins
85 if (check_pin_busy(pin))
90 bit_set(pull_cache, pin);
92 bit_clear(pull_cache, pin);
95 bit_set(active_cache, pin);
97 bit_clear(active_cache, pin);
100 bit_set(can_wake_cache, pin);
102 bit_clear(can_wake_cache, pin);
104 config_changed = TRUE;
109 static uint16_t in_cache = 0x0;
111 int8_t rpp_din_get(uint8_t pin)
117 // Check blockade of specific pins
118 if (check_pin_busy(pin))
122 if (is_bit_set(in_cache, pin))
127 int8_t rpp_din_get_tr(uint8_t pin)
130 if (pin < 8 || pin > 15)
133 // Check blockade of specific pins
134 if (check_pin_busy(pin))
138 #ifndef FREERTOS_POSIX
139 if (drv_din_get_varthr(pin) == 1)
148 static uint16_t diag_cache = 0x0;
150 int8_t rpp_din_diag(uint8_t pin)
156 // Check blockade of specific pins
157 if (check_pin_busy(pin))
161 if (is_bit_set(diag_cache, pin))
167 * pouzivat din_mod s pouzivanim enumu
169 int8_t rpp_din_update()
171 #ifndef FREERTOS_POSIX
173 if (config_changed) {
178 din_set_reg(DIN_RESET_CMD, 0, 0);
179 //rpp_sci_printf("din_reset()\r\n");
182 // In DRV logic is inverted:
183 // DRV: 1 - set pin as switch-to-battery. RPP: 0 - pull-down.
184 // DRV: 0 - set pin as switch-to-ground. RPP: 1 - pull-up.
185 sp = (~pull_cache) & 0xFF;
186 din_set_reg(DIN_SETTINGS_CMD, 0xffff, sp);
187 //rpp_sci_printf("din_set_pr(%X)\r\n", sp);
189 // Set state type, active or tri-stated.
190 // In DRV logic is inverted:
191 // DRV: 1 - tri-state. RPP: 0 - tri-state.
192 // DRV: 0 - active. RPP: 1 - active.
193 sp = ((~active_cache) ) & 0xFF;
194 sg = ((~active_cache) >> 8) & 0xFF;
195 din_set_reg(DIN_TRI_STATE_CMD_YES, 0xffff, sp);
196 din_set_reg(DIN_TRI_STATE_CMD_NO, 0xffff, sg);
197 //rpp_sci_printf("din_set_stat(%X, %X)\r\n", sp, sg);
199 // Set wake / interrupt.
200 // IN DRV logic is not inverted.
201 // DRV: 1 - can wake. RPP: 1 - can wake.
202 // DRV: 0 - interrupt disabled. RPP: 0 - interrupt disabled.
203 sp = (can_wake_cache ) & 0xFF;
204 sg = (can_wake_cache >> 8) & 0xFF;
206 din_set_reg(DIN_WAKE_UP_CMD_ENB, 0xffff, sp);
207 din_set_reg(DIN_WAKE_UP_CMD_DIS, 0xffff, sg);
208 //rpp_sci_printf("din_set_int(%X, %X)\r\n", sp, sg);
210 // Mark configuration as commited
211 config_changed = FALSE;
214 // Update cached values
215 din_set_reg(DIN_SWITCH_STATUS_CMD, 0, 0);
216 in_cache = din_get_val_word();
218 // FIXME: Implement. Dummy assign for now.
219 diag_cache = in_cache;
221 if (diag_cache != in_cache)
224 #else /* ifndef FREERTOS_POSIX */
225 UNUSED(config_changed);
226 #endif /* ifndef FREERTOS_POSIX */