From ebb0a2c2326148b8e9ec17579ee620df7b9ea993 Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Mon, 17 Oct 2011 19:12:40 +0200 Subject: [PATCH] mf624 QEMU hardware emulation updated to compile with version above 0.15. To compile with new QEMU version the define QEMU_VER_ABOVE_015 has to be enabled. Signed-off-by: Pavel Pisa --- src/qemu/hw/mf624.c | 93 +++++++++++++++++++++++++++++++++++++++------ 1 file changed, 81 insertions(+), 12 deletions(-) mode change 100755 => 100644 src/qemu/hw/mf624.c diff --git a/src/qemu/hw/mf624.c b/src/qemu/hw/mf624.c old mode 100755 new mode 100644 index 621e4bf..ebbc58c --- a/src/qemu/hw/mf624.c +++ b/src/qemu/hw/mf624.c @@ -7,7 +7,7 @@ */ #include "hw.h" #include "pci.h" -#include "../qemu-thread.c" +#include "qemu-thread.h" #include #include #include @@ -15,6 +15,8 @@ #include #include +/* #define QEMU_VER_ABOVE_015 */ + #define PCI_VENDOR_ID_HUMUSOFT 0x186c #define PCI_DEVICE_ID_MF624 0x0624 #define PCI_CLASS_SIGNAL_PROCESSING_CONTROLLER 0x1180 @@ -93,6 +95,11 @@ typedef struct { typedef struct { PCIDevice dev; + #ifdef QEMU_VER_ABOVE_015 + MemoryRegion mmio_bar0; + MemoryRegion mmio_bar2; + MemoryRegion mmio_bar4; + #endif /*QEMU_VER_ABOVE_015*/ int socket_srv; int socket_tmp; @@ -120,6 +127,7 @@ typedef struct { BAR2_t BAR2; BAR4_t BAR4; + int ADDATA_FIFO[8]; //this array tells us which ADCs are being converted unsigned int ADDATA_FIFO_POSITION; //ADDATA is FIFO register; //We need to know, position in this FIFO = @@ -363,7 +371,7 @@ static void mf624_BAR0_write32(void *opaque, target_phys_addr_t addr, uint32_t v break; default: - printf("mf624_BAR0_write32(): addr = %d; value = %d\n", addr, value); + printf("mf624_BAR0_write32(): addr = " TARGET_FMT_plx "; value = %d\n", addr, value); break; } } @@ -381,7 +389,7 @@ static uint32_t mf624_BAR0_read32(void *opaque, target_phys_addr_t addr) return s->BAR0.GPIOC; default: - printf("mf624_BAR0_read32(): addr = %d\n", addr); + printf("mf624_BAR0_read32(): addr = " TARGET_FMT_plx "\n", addr); return 0x0; } } @@ -475,7 +483,7 @@ static uint32_t mf624_BAR2_read16(void *opaque, target_phys_addr_t addr) return 0xFFFF; // Semirandom value default: - printf("mf624_BAR2_read16(): addr = %d\n", addr); + printf("mf624_BAR2_read16(): addr = " TARGET_FMT_plx "\n", addr); return 0x0; } } @@ -562,7 +570,7 @@ static void mf624_BAR2_write16(void *opaque, target_phys_addr_t addr, uint32_t v break; default: - printf("mf624_BAR2_write16(): addr = %d; value = %d\n", addr, value); + printf("mf624_BAR2_write16(): addr = " TARGET_FMT_plx "; value = %d\n", addr, value); break; } } @@ -570,15 +578,68 @@ static void mf624_BAR2_write16(void *opaque, target_phys_addr_t addr, uint32_t v static void mf624_BAR4_write32(void *opaque, target_phys_addr_t addr, uint32_t value) { - printf("mf624_BAR4_write32(): addr = %d; value = %d\n", addr, value); + printf("mf624_BAR4_write32(): addr = " TARGET_FMT_plx "; value = %d\n", addr, value); } static uint32_t mf624_BAR4_read32(void *opaque, target_phys_addr_t addr) { - printf("mf624_BAR4_read32(): addr = %d\n", addr); + printf("mf624_BAR4_read32(): addr = " TARGET_FMT_plx "\n", addr); return 0x0; } +//----------------------------------------------------------------------------- + +#ifdef QEMU_VER_ABOVE_015 + +static const MemoryRegionOps mf624_BAR0_mmio_ops = { + .old_mmio = { + .read = { + NULL, + NULL, + mf624_BAR0_read32, + }, + .write = { + NULL, + NULL, + mf624_BAR0_write32, + }, + }, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static const MemoryRegionOps mf624_BAR2_mmio_ops = { + .old_mmio = { + .read = { + NULL, + mf624_BAR2_read16, + NULL, + }, + .write = { + NULL, + mf624_BAR2_write16, + NULL, + }, + }, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static const MemoryRegionOps mf624_BAR4_mmio_ops = { + .old_mmio = { + .read = { + NULL, + NULL, + mf624_BAR4_read32, + }, + .write = { + NULL, + NULL, + mf624_BAR4_write32, + }, + }, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +#else /*QEMU_VER_ABOVE_015*/ static CPUReadMemoryFunc * const mf624_BAR0_read[3] = { NULL, /* read8 */ @@ -615,6 +676,8 @@ static CPUWriteMemoryFunc * const mf624_BAR4_write[3] = { NULL, /* write16 */ mf624_BAR4_write32, }; + + //----------------------------------------------------------------------------- static void mf624_map(PCIDevice *pci_dev, int region_num, @@ -641,6 +704,8 @@ static void mf624_map(PCIDevice *pci_dev, int region_num, } +#endif /*QEMU_VER_ABOVE_015*/ + #define DEFAULT_PORT 55555 static int pci_mf624_init(PCIDevice *pci_dev) { @@ -669,7 +734,14 @@ static int pci_mf624_init(PCIDevice *pci_dev) pci_conf[PCI_INTERRUPT_PIN] = 0x1; // interrupt pin 0 - + #ifdef QEMU_VER_ABOVE_015 + memory_region_init_io(&s->mmio_bar0, &mf624_BAR0_mmio_ops, s, "mf624_bar0", BAR0_size); + memory_region_init_io(&s->mmio_bar2, &mf624_BAR2_mmio_ops, s, "mf624_bar2", BAR2_size); + memory_region_init_io(&s->mmio_bar4, &mf624_BAR4_mmio_ops, s, "mf624_bar4", BAR4_size); + pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio_bar0); + pci_register_bar(&s->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio_bar2); + pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio_bar4); + #else QEMU_VER_ABOVE_015 s->BAR0_mem_table_index = cpu_register_io_memory(mf624_BAR0_read, mf624_BAR0_write, s, @@ -685,13 +757,10 @@ static int pci_mf624_init(PCIDevice *pci_dev) s, DEVICE_NATIVE_ENDIAN); - //printf("BAR0: %d\n", s->BAR0_offset); - //printf("BAR2: %d\n", s->BAR2_offset); - //printf("BAR4: %d\n", s->BAR4_offset); - pci_register_bar(&s->dev, 0, BAR0_size, PCI_BASE_ADDRESS_SPACE_MEMORY, mf624_map); pci_register_bar(&s->dev, 2, BAR2_size, PCI_BASE_ADDRESS_SPACE_MEMORY, mf624_map); pci_register_bar(&s->dev, 4, BAR4_size, PCI_BASE_ADDRESS_SPACE_MEMORY, mf624_map); + #endif QEMU_VER_ABOVE_015 //Create thread, which will be blocked on reading from socket (connected to "I/O GUI") qemu_thread_create(&socket_thread, init_socket, (void*) s); -- 2.39.2