From: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Date: Sat, 15 Feb 2014 10:44:48 +0000 (+0100)
Subject: Add _reg suffix to MF624 counter subsystem registers.
X-Git-Url: http://rtime.felk.cvut.cz/gitweb/mf624-simulink.git/commitdiff_plain/daee816a81348bea6b13c6054832051f7d420e3e

Add _reg suffix to MF624 counter subsystem registers.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
---

diff --git a/mf624_SIMULINK.h b/mf624_SIMULINK.h
index c369410..b29cc6e 100644
--- a/mf624_SIMULINK.h
+++ b/mf624_SIMULINK.h
@@ -43,17 +43,17 @@
 #define DA7_reg			0x2E
 
 /* BAR4 */
-#define CTR0MODE     0x00
-#define CTR1MODE     0x10
-#define CTR2MODE     0x20
-#define CTR3MODE     0x30
-#define CTR4MODE     0x40
-#define CTR0         0x04
-#define CTR1         0x14
-#define CTR2         0x24
-#define CTR3         0x34
-#define CTR4         0x44
-#define CTRXCTRL     0x60
+#define CTR0MODE_reg		0x00
+#define CTR1MODE_reg		0x10
+#define CTR2MODE_reg		0x20
+#define CTR3MODE_reg		0x30
+#define CTR4MODE_reg		0x40
+#define CTR0_reg		0x04
+#define CTR1_reg		0x14
+#define CTR2_reg		0x24
+#define CTR3_reg		0x34
+#define CTR4_reg		0x44
+#define CTRXCTRL_reg		0x60
 
 #define IRCSTATUS_reg		0x6C
 #define IRCCTRL_reg		0x6C
diff --git a/sfReadPWM.c b/sfReadPWM.c
index fcd406e..da79c92 100644
--- a/sfReadPWM.c
+++ b/sfReadPWM.c
@@ -134,25 +134,25 @@ static void mdlInitializeSampleTimes(SimStruct *S)
 	return;
             
     /*Configuration of desired counter modes*/
-    mf624_write32(CTRX_MODE,MFST2REG(mfst,4,CTR0MODE));
-    mf624_write32(CTRX_MODE,MFST2REG(mfst,4,CTR1MODE));
-    mf624_write32(CTRX_MODE,MFST2REG(mfst,4,CTR2MODE));
-    mf624_write32(CTR4_MODE,MFST2REG(mfst,4,CTR4MODE));
+    mf624_write32(CTRX_MODE,MFST2REG(mfst,4,CTR0MODE_reg));
+    mf624_write32(CTRX_MODE,MFST2REG(mfst,4,CTR1MODE_reg));
+    mf624_write32(CTRX_MODE,MFST2REG(mfst,4,CTR2MODE_reg));
+    mf624_write32(CTR4_MODE,MFST2REG(mfst,4,CTR4MODE_reg));
     
     /*Set reload values of ctrs 0,1,2,4 to 0 just to be sure*/
-    mf624_write32(0,MFST2REG(mfst,4,CTR0));
-    mf624_write32(0,MFST2REG(mfst,4,CTR1));
-    mf624_write32(0,MFST2REG(mfst,4,CTR2));
-    mf624_write32(0,MFST2REG(mfst,4,CTR4));
+    mf624_write32(0,MFST2REG(mfst,4,CTR0_reg));
+    mf624_write32(0,MFST2REG(mfst,4,CTR1_reg));
+    mf624_write32(0,MFST2REG(mfst,4,CTR2_reg));
+    mf624_write32(0,MFST2REG(mfst,4,CTR4_reg));
     
     /*Read values from counters and initialize IWork values with them*/
-    ssSetIWorkValue(S,0,(unsigned int)mf624_read32(MFST2REG(mfst,4,CTR0)));
-    ssSetIWorkValue(S,1,(unsigned int)mf624_read32(MFST2REG(mfst,4,CTR1)));
-    ssSetIWorkValue(S,2,(unsigned int)mf624_read32(MFST2REG(mfst,4,CTR2)));
-    ssSetIWorkValue(S,3,(unsigned int)mf624_read32(MFST2REG(mfst,4,CTR4)));
+    ssSetIWorkValue(S,0,(unsigned int)mf624_read32(MFST2REG(mfst,4,CTR0_reg)));
+    ssSetIWorkValue(S,1,(unsigned int)mf624_read32(MFST2REG(mfst,4,CTR1_reg)));
+    ssSetIWorkValue(S,2,(unsigned int)mf624_read32(MFST2REG(mfst,4,CTR2_reg)));
+    ssSetIWorkValue(S,3,(unsigned int)mf624_read32(MFST2REG(mfst,4,CTR4_reg)));
     
     /*Start counters 0,1,2, tehy are gated with their inputs so no worries about premature start*/
-    mf624_write32(CTR_START,MFST2REG(mfst,4,CTRXCTRL));
+    mf624_write32(CTR_START,MFST2REG(mfst,4,CTRXCTRL_reg));
             
     
   }
@@ -176,10 +176,10 @@ static void mdlOutputs(SimStruct *S, int_T tid)
     if (mf624_check(S) != 0)
 	    return;
 	
-    c0 = mf624_read32(MFST2REG(mfst,4,CTR0));
-    c1 = mf624_read32(MFST2REG(mfst,4,CTR1));
-    c2 = mf624_read32(MFST2REG(mfst,4,CTR2));
-    c4 = mf624_read32(MFST2REG(mfst,4,CTR4));
+    c0 = mf624_read32(MFST2REG(mfst,4,CTR0_reg));
+    c1 = mf624_read32(MFST2REG(mfst,4,CTR1_reg));
+    c2 = mf624_read32(MFST2REG(mfst,4,CTR2_reg));
+    c4 = mf624_read32(MFST2REG(mfst,4,CTR4_reg));
     
     period = (unsigned int)(c4-(unsigned int)ssGetIWorkValue(S,3));
     
@@ -236,7 +236,7 @@ static void mdlTerminate(SimStruct *S)
     if (mf624_check(NULL) != 0)
 	    return;
 
-    mf624_write32(CTR_STOP,MFST2REG(mfst,4,CTRXCTRL));
+    mf624_write32(CTR_STOP,MFST2REG(mfst,4,CTRXCTRL_reg));
     mf624_done();
 }