]> rtime.felk.cvut.cz Git - lisovros/qemu_apohw.git/commit
target-mips: add user-mode FR switch support for MIPS32r5
authorPetar Jovanovic <petar.jovanovic@imgtec.com>
Wed, 22 Jan 2014 17:35:32 +0000 (18:35 +0100)
committerPetar Jovanovic <petar.jovanovic@imgtec.com>
Mon, 10 Feb 2014 15:46:38 +0000 (16:46 +0100)
commit736d120af4bf5f3e13b2f90c464b3a24847f78f0
tree01cb88023c2ee383af3dcde2793e756d13b1833e
parentb4dd99a3636f5a3044dfd9dba7653ca377a9aeba
target-mips: add user-mode FR switch support for MIPS32r5

Description of UFR feature:

Required in MIPS32r5 if floating point is implemented and user-mode FR
switching is supported. The UFR register allows user-mode to clear StatusFR
by executing a CTC1 to UFR with GPR[0] as input, and read StatusFR by
executing a CFC1 to UFR.

helper_ctc1 has been extended with an additional parameter rt to check
requirements for UFR feature.
Definition of mips32r5-generic has been modified to include support for UFR.

Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
target-mips/helper.h
target-mips/op_helper.c
target-mips/translate.c
target-mips/translate_init.c