target-arm: Define exception record for AArch64 exceptions

[lisovros/qemu_apohw.git] / target-arm / cpu.h

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 695a1e21f5d222edff0b6017c3bcdcec43ff61b7..7a48241fde9275c39e5e312ae63f700d8ec2c171 100644 (file)
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -233,6 +233,21 @@ typedef struct CPUARMState {
         int pending_exception;
     } v7m;
 
+    /* Information associated with an exception about to be taken:
+     * code which raises an exception must set cs->exception_index and
+     * the relevant parts of this structure; the cpu_do_interrupt function
+     * will then set the guest-visible registers as part of the exception
+     * entry process.
+     */
+    struct {
+        uint32_t syndrome; /* AArch64 format syndrome register */
+        uint32_t fsr; /* AArch32 format fault status register info */
+        uint64_t vaddress; /* virtual addr associated with exception, if any */
+        /* If we implement EL2 we will also need to store information
+         * about the intermediate physical address for stage 2 faults.
+         */
+    } exception;
+
     /* Thumb-2 EE state.  */
     uint32_t teecr;
     uint32_t teehbr;