2 * Copyright (C) 2010 Red Hat, Inc.
4 * written by Gerd Hoffmann <kraxel@redhat.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu-timer.h"
25 #include "intel-hda.h"
26 #include "intel-hda-defs.h"
29 /* --------------------------------------------------------------------- */
32 static struct BusInfo hda_codec_bus_info = {
34 .size = sizeof(HDACodecBus),
35 .props = (Property[]) {
36 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1),
37 DEFINE_PROP_END_OF_LIST()
41 void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus,
42 hda_codec_response_func response,
43 hda_codec_xfer_func xfer)
45 qbus_create_inplace(&bus->qbus, &hda_codec_bus_info, dev, NULL);
46 bus->response = response;
50 static int hda_codec_dev_init(DeviceState *qdev, DeviceInfo *base)
52 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, qdev->parent_bus);
53 HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
54 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
57 dev->cad = bus->next_cad;
62 bus->next_cad = dev->cad + 1;
63 return cdc->init(dev);
66 static int hda_codec_dev_exit(DeviceState *qdev)
68 HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
69 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
77 void hda_codec_register(DeviceInfo *info)
79 info->init = hda_codec_dev_init;
80 info->exit = hda_codec_dev_exit;
81 info->bus_info = &hda_codec_bus_info;
85 HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad)
90 QTAILQ_FOREACH(qdev, &bus->qbus.children, sibling) {
91 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
92 if (cdev->cad == cad) {
99 void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response)
101 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
102 bus->response(dev, solicited, response);
105 bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
106 uint8_t *buf, uint32_t len)
108 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
109 return bus->xfer(dev, stnr, output, buf, len);
112 /* --------------------------------------------------------------------- */
113 /* intel hda emulation */
115 typedef struct IntelHDAStream IntelHDAStream;
116 typedef struct IntelHDAState IntelHDAState;
117 typedef struct IntelHDAReg IntelHDAReg;
125 struct IntelHDAStream {
138 uint32_t bsize, be, bp;
141 struct IntelHDAState {
178 IntelHDAStream st[8];
183 int64_t wall_base_ns;
186 const IntelHDAReg *last_reg;
190 uint32_t repeat_count;
198 const char *name; /* register name */
199 uint32_t size; /* size in bytes */
200 uint32_t reset; /* reset value */
201 uint32_t wmask; /* write mask */
202 uint32_t wclear; /* write 1 to clear bits */
203 uint32_t offset; /* location in IntelHDAState */
204 uint32_t shift; /* byte access entries for dwords */
206 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old);
207 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg);
210 static void intel_hda_reset(DeviceState *dev);
212 /* --------------------------------------------------------------------- */
214 static target_phys_addr_t intel_hda_addr(uint32_t lbase, uint32_t ubase)
216 target_phys_addr_t addr;
218 #if TARGET_PHYS_ADDR_BITS == 32
228 static void intel_hda_update_int_sts(IntelHDAState *d)
233 /* update controller status */
234 if (d->rirb_sts & ICH6_RBSTS_IRQ) {
237 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) {
240 if (d->state_sts & d->wake_en) {
244 /* update stream status */
245 for (i = 0; i < 8; i++) {
246 /* buffer completion interrupt */
247 if (d->st[i].ctl & (1 << 26)) {
252 /* update global status */
253 if (sts & d->int_ctl) {
260 static void intel_hda_update_irq(IntelHDAState *d)
262 int msi = d->msi && msi_enabled(&d->pci);
265 intel_hda_update_int_sts(d);
266 if (d->int_sts & (1 << 31) && d->int_ctl & (1 << 31)) {
271 dprint(d, 2, "%s: level %d [%s]\n", __FUNCTION__,
272 level, msi ? "msi" : "intx");
275 msi_notify(&d->pci, 0);
278 qemu_set_irq(d->pci.irq[0], level);
282 static int intel_hda_send_command(IntelHDAState *d, uint32_t verb)
284 uint32_t cad, nid, data;
285 HDACodecDevice *codec;
286 HDACodecDeviceClass *cdc;
288 cad = (verb >> 28) & 0x0f;
289 if (verb & (1 << 27)) {
290 /* indirect node addressing, not specified in HDA 1.0 */
291 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__);
294 nid = (verb >> 20) & 0x7f;
295 data = verb & 0xfffff;
297 codec = hda_codec_find(&d->codecs, cad);
299 dprint(d, 1, "%s: addressed non-existing codec\n", __FUNCTION__);
302 cdc = HDA_CODEC_DEVICE_GET_CLASS(codec);
303 cdc->command(codec, nid, data);
307 static void intel_hda_corb_run(IntelHDAState *d)
309 target_phys_addr_t addr;
312 if (d->ics & ICH6_IRS_BUSY) {
313 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__, d->icw);
314 intel_hda_send_command(d, d->icw);
319 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) {
320 dprint(d, 2, "%s: !run\n", __FUNCTION__);
323 if ((d->corb_rp & 0xff) == d->corb_wp) {
324 dprint(d, 2, "%s: corb ring empty\n", __FUNCTION__);
327 if (d->rirb_count == d->rirb_cnt) {
328 dprint(d, 2, "%s: rirb count reached\n", __FUNCTION__);
332 rp = (d->corb_rp + 1) & 0xff;
333 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase);
334 verb = ldl_le_pci_dma(&d->pci, addr + 4*rp);
337 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__, rp, verb);
338 intel_hda_send_command(d, verb);
342 static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response)
344 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
345 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
346 target_phys_addr_t addr;
349 if (d->ics & ICH6_IRS_BUSY) {
350 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
351 __FUNCTION__, response, dev->cad);
353 d->ics &= ~(ICH6_IRS_BUSY | 0xf0);
354 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4));
358 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) {
359 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__);
363 ex = (solicited ? 0 : (1 << 4)) | dev->cad;
364 wp = (d->rirb_wp + 1) & 0xff;
365 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase);
366 stl_le_pci_dma(&d->pci, addr + 8*wp, response);
367 stl_le_pci_dma(&d->pci, addr + 8*wp + 4, ex);
370 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
371 __FUNCTION__, wp, response, ex);
374 if (d->rirb_count == d->rirb_cnt) {
375 dprint(d, 2, "%s: rirb count reached (%d)\n", __FUNCTION__, d->rirb_count);
376 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
377 d->rirb_sts |= ICH6_RBSTS_IRQ;
378 intel_hda_update_irq(d);
380 } else if ((d->corb_rp & 0xff) == d->corb_wp) {
381 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__,
382 d->rirb_count, d->rirb_cnt);
383 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
384 d->rirb_sts |= ICH6_RBSTS_IRQ;
385 intel_hda_update_irq(d);
390 static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
391 uint8_t *buf, uint32_t len)
393 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
394 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
395 target_phys_addr_t addr;
396 uint32_t s, copy, left;
400 st = output ? d->st + 4 : d->st;
401 for (s = 0; s < 4; s++) {
402 if (stnr == ((st[s].ctl >> 20) & 0x0f)) {
410 if (st->bpl == NULL) {
413 if (st->ctl & (1 << 26)) {
415 * Wait with the next DMA xfer until the guest
416 * has acked the buffer completion interrupt
424 if (copy > st->bsize - st->lpib)
425 copy = st->bsize - st->lpib;
426 if (copy > st->bpl[st->be].len - st->bp)
427 copy = st->bpl[st->be].len - st->bp;
429 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n",
430 st->be, st->bp, st->bpl[st->be].len, copy);
432 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output);
438 if (st->bpl[st->be].len == st->bp) {
439 /* bpl entry filled */
440 if (st->bpl[st->be].flags & 0x01) {
445 if (st->be == st->bentries) {
446 /* bpl wrap around */
452 if (d->dp_lbase & 0x01) {
453 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
454 stl_le_pci_dma(&d->pci, addr + 8*s, st->lpib);
456 dprint(d, 3, "dma: --\n");
459 st->ctl |= (1 << 26); /* buffer completion interrupt */
460 intel_hda_update_irq(d);
465 static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st)
467 target_phys_addr_t addr;
471 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase);
472 st->bentries = st->lvi +1;
474 st->bpl = g_malloc(sizeof(bpl) * st->bentries);
475 for (i = 0; i < st->bentries; i++, addr += 16) {
476 pci_dma_read(&d->pci, addr, buf, 16);
477 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf);
478 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8));
479 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12));
480 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n",
481 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags);
490 static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output)
493 HDACodecDevice *cdev;
495 QTAILQ_FOREACH(qdev, &d->codecs.qbus.children, sibling) {
496 HDACodecDeviceClass *cdc;
498 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
499 cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev);
501 cdc->stream(cdev, stream, running, output);
506 /* --------------------------------------------------------------------- */
508 static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
510 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) {
511 intel_hda_reset(&d->pci.qdev);
515 static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
517 intel_hda_update_irq(d);
520 static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
522 intel_hda_update_irq(d);
525 static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
527 intel_hda_update_irq(d);
530 static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg)
534 ns = qemu_get_clock_ns(vm_clock) - d->wall_base_ns;
535 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */
538 static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
540 intel_hda_corb_run(d);
543 static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
545 intel_hda_corb_run(d);
548 static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
550 if (d->rirb_wp & ICH6_RIRBWP_RST) {
555 static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
557 intel_hda_update_irq(d);
559 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) {
560 /* cleared ICH6_RBSTS_IRQ */
562 intel_hda_corb_run(d);
566 static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
568 if (d->ics & ICH6_IRS_BUSY) {
569 intel_hda_corb_run(d);
573 static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
575 bool output = reg->stream >= 4;
576 IntelHDAStream *st = d->st + reg->stream;
578 if (st->ctl & 0x01) {
580 dprint(d, 1, "st #%d: reset\n", reg->stream);
583 if ((st->ctl & 0x02) != (old & 0x02)) {
584 uint32_t stnr = (st->ctl >> 20) & 0x0f;
585 /* run bit flipped */
586 if (st->ctl & 0x02) {
588 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n",
589 reg->stream, stnr, st->cbl);
590 intel_hda_parse_bdl(d, st);
591 intel_hda_notify_codecs(d, stnr, true, output);
594 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr);
595 intel_hda_notify_codecs(d, stnr, false, output);
598 intel_hda_update_irq(d);
601 /* --------------------------------------------------------------------- */
603 #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
605 static const struct IntelHDAReg regtab[] = {
607 [ ICH6_REG_GCAP ] = {
612 [ ICH6_REG_VMIN ] = {
616 [ ICH6_REG_VMAJ ] = {
621 [ ICH6_REG_OUTPAY ] = {
626 [ ICH6_REG_INPAY ] = {
631 [ ICH6_REG_GCTL ] = {
635 .offset = offsetof(IntelHDAState, g_ctl),
636 .whandler = intel_hda_set_g_ctl,
638 [ ICH6_REG_WAKEEN ] = {
642 .offset = offsetof(IntelHDAState, wake_en),
643 .whandler = intel_hda_set_wake_en,
645 [ ICH6_REG_STATESTS ] = {
650 .offset = offsetof(IntelHDAState, state_sts),
651 .whandler = intel_hda_set_state_sts,
655 [ ICH6_REG_INTCTL ] = {
659 .offset = offsetof(IntelHDAState, int_ctl),
660 .whandler = intel_hda_set_int_ctl,
662 [ ICH6_REG_INTSTS ] = {
666 .wclear = 0xc00000ff,
667 .offset = offsetof(IntelHDAState, int_sts),
671 [ ICH6_REG_WALLCLK ] = {
674 .offset = offsetof(IntelHDAState, wall_clk),
675 .rhandler = intel_hda_get_wall_clk,
677 [ ICH6_REG_WALLCLK + 0x2000 ] = {
678 .name = "WALLCLK(alias)",
680 .offset = offsetof(IntelHDAState, wall_clk),
681 .rhandler = intel_hda_get_wall_clk,
685 [ ICH6_REG_CORBLBASE ] = {
689 .offset = offsetof(IntelHDAState, corb_lbase),
691 [ ICH6_REG_CORBUBASE ] = {
695 .offset = offsetof(IntelHDAState, corb_ubase),
697 [ ICH6_REG_CORBWP ] = {
701 .offset = offsetof(IntelHDAState, corb_wp),
702 .whandler = intel_hda_set_corb_wp,
704 [ ICH6_REG_CORBRP ] = {
708 .offset = offsetof(IntelHDAState, corb_rp),
710 [ ICH6_REG_CORBCTL ] = {
714 .offset = offsetof(IntelHDAState, corb_ctl),
715 .whandler = intel_hda_set_corb_ctl,
717 [ ICH6_REG_CORBSTS ] = {
722 .offset = offsetof(IntelHDAState, corb_sts),
724 [ ICH6_REG_CORBSIZE ] = {
728 .offset = offsetof(IntelHDAState, corb_size),
730 [ ICH6_REG_RIRBLBASE ] = {
734 .offset = offsetof(IntelHDAState, rirb_lbase),
736 [ ICH6_REG_RIRBUBASE ] = {
740 .offset = offsetof(IntelHDAState, rirb_ubase),
742 [ ICH6_REG_RIRBWP ] = {
746 .offset = offsetof(IntelHDAState, rirb_wp),
747 .whandler = intel_hda_set_rirb_wp,
749 [ ICH6_REG_RINTCNT ] = {
753 .offset = offsetof(IntelHDAState, rirb_cnt),
755 [ ICH6_REG_RIRBCTL ] = {
759 .offset = offsetof(IntelHDAState, rirb_ctl),
761 [ ICH6_REG_RIRBSTS ] = {
766 .offset = offsetof(IntelHDAState, rirb_sts),
767 .whandler = intel_hda_set_rirb_sts,
769 [ ICH6_REG_RIRBSIZE ] = {
773 .offset = offsetof(IntelHDAState, rirb_size),
776 [ ICH6_REG_DPLBASE ] = {
780 .offset = offsetof(IntelHDAState, dp_lbase),
782 [ ICH6_REG_DPUBASE ] = {
786 .offset = offsetof(IntelHDAState, dp_ubase),
793 .offset = offsetof(IntelHDAState, icw),
798 .offset = offsetof(IntelHDAState, irr),
805 .offset = offsetof(IntelHDAState, ics),
806 .whandler = intel_hda_set_ics,
809 #define HDA_STREAM(_t, _i) \
810 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \
812 .name = _t stringify(_i) " CTL", \
814 .wmask = 0x1cff001f, \
815 .offset = offsetof(IntelHDAState, st[_i].ctl), \
816 .whandler = intel_hda_set_st_ctl, \
818 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
820 .name = _t stringify(_i) " CTL(stnr)", \
823 .wmask = 0x00ff0000, \
824 .offset = offsetof(IntelHDAState, st[_i].ctl), \
825 .whandler = intel_hda_set_st_ctl, \
827 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \
829 .name = _t stringify(_i) " CTL(sts)", \
832 .wmask = 0x1c000000, \
833 .wclear = 0x1c000000, \
834 .offset = offsetof(IntelHDAState, st[_i].ctl), \
835 .whandler = intel_hda_set_st_ctl, \
837 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \
839 .name = _t stringify(_i) " LPIB", \
841 .offset = offsetof(IntelHDAState, st[_i].lpib), \
843 [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \
845 .name = _t stringify(_i) " LPIB(alias)", \
847 .offset = offsetof(IntelHDAState, st[_i].lpib), \
849 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \
851 .name = _t stringify(_i) " CBL", \
853 .wmask = 0xffffffff, \
854 .offset = offsetof(IntelHDAState, st[_i].cbl), \
856 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \
858 .name = _t stringify(_i) " LVI", \
861 .offset = offsetof(IntelHDAState, st[_i].lvi), \
863 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \
865 .name = _t stringify(_i) " FIFOS", \
867 .reset = HDA_BUFFER_SIZE, \
869 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \
871 .name = _t stringify(_i) " FMT", \
874 .offset = offsetof(IntelHDAState, st[_i].fmt), \
876 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \
878 .name = _t stringify(_i) " BDLPL", \
880 .wmask = 0xffffff80, \
881 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \
883 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \
885 .name = _t stringify(_i) " BDLPU", \
887 .wmask = 0xffffffff, \
888 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \
903 static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, target_phys_addr_t addr)
905 const IntelHDAReg *reg;
907 if (addr >= sizeof(regtab)/sizeof(regtab[0])) {
911 if (reg->name == NULL) {
917 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr);
921 static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg)
923 uint8_t *addr = (void*)d;
926 return (uint32_t*)addr;
929 static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val,
940 time_t now = time(NULL);
941 if (d->last_write && d->last_reg == reg && d->last_val == val) {
943 if (d->last_sec != now) {
944 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
949 if (d->repeat_count) {
950 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
952 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask);
960 assert(reg->offset != 0);
962 addr = intel_hda_reg_addr(d, reg);
967 wmask <<= reg->shift;
971 *addr |= wmask & val;
972 *addr &= ~(val & reg->wclear);
975 reg->whandler(d, reg, old);
979 static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg,
989 reg->rhandler(d, reg);
992 if (reg->offset == 0) {
993 /* constant read-only register */
996 addr = intel_hda_reg_addr(d, reg);
1004 time_t now = time(NULL);
1005 if (!d->last_write && d->last_reg == reg && d->last_val == ret) {
1007 if (d->last_sec != now) {
1008 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1010 d->repeat_count = 0;
1013 if (d->repeat_count) {
1014 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1016 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask);
1021 d->repeat_count = 0;
1027 static void intel_hda_regs_reset(IntelHDAState *d)
1032 for (i = 0; i < sizeof(regtab)/sizeof(regtab[0]); i++) {
1033 if (regtab[i].name == NULL) {
1036 if (regtab[i].offset == 0) {
1039 addr = intel_hda_reg_addr(d, regtab + i);
1040 *addr = regtab[i].reset;
1044 /* --------------------------------------------------------------------- */
1046 static void intel_hda_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1048 IntelHDAState *d = opaque;
1049 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1051 intel_hda_reg_write(d, reg, val, 0xff);
1054 static void intel_hda_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1056 IntelHDAState *d = opaque;
1057 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1059 intel_hda_reg_write(d, reg, val, 0xffff);
1062 static void intel_hda_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1064 IntelHDAState *d = opaque;
1065 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1067 intel_hda_reg_write(d, reg, val, 0xffffffff);
1070 static uint32_t intel_hda_mmio_readb(void *opaque, target_phys_addr_t addr)
1072 IntelHDAState *d = opaque;
1073 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1075 return intel_hda_reg_read(d, reg, 0xff);
1078 static uint32_t intel_hda_mmio_readw(void *opaque, target_phys_addr_t addr)
1080 IntelHDAState *d = opaque;
1081 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1083 return intel_hda_reg_read(d, reg, 0xffff);
1086 static uint32_t intel_hda_mmio_readl(void *opaque, target_phys_addr_t addr)
1088 IntelHDAState *d = opaque;
1089 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1091 return intel_hda_reg_read(d, reg, 0xffffffff);
1094 static const MemoryRegionOps intel_hda_mmio_ops = {
1097 intel_hda_mmio_readb,
1098 intel_hda_mmio_readw,
1099 intel_hda_mmio_readl,
1102 intel_hda_mmio_writeb,
1103 intel_hda_mmio_writew,
1104 intel_hda_mmio_writel,
1107 .endianness = DEVICE_NATIVE_ENDIAN,
1110 /* --------------------------------------------------------------------- */
1112 static void intel_hda_reset(DeviceState *dev)
1114 IntelHDAState *d = DO_UPCAST(IntelHDAState, pci.qdev, dev);
1116 HDACodecDevice *cdev;
1118 intel_hda_regs_reset(d);
1119 d->wall_base_ns = qemu_get_clock_ns(vm_clock);
1122 QTAILQ_FOREACH(qdev, &d->codecs.qbus.children, sibling) {
1123 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
1124 device_reset(DEVICE(cdev));
1125 d->state_sts |= (1 << cdev->cad);
1127 intel_hda_update_irq(d);
1130 static int intel_hda_init(PCIDevice *pci)
1132 IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1133 uint8_t *conf = d->pci.config;
1135 d->name = object_get_typename(OBJECT(d));
1137 pci_config_set_interrupt_pin(conf, 1);
1139 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1142 memory_region_init_io(&d->mmio, &intel_hda_mmio_ops, d,
1143 "intel-hda", 0x4000);
1144 pci_register_bar(&d->pci, 0, 0, &d->mmio);
1146 msi_init(&d->pci, 0x50, 1, true, false);
1149 hda_codec_bus_init(&d->pci.qdev, &d->codecs,
1150 intel_hda_response, intel_hda_xfer);
1155 static int intel_hda_exit(PCIDevice *pci)
1157 IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1159 msi_uninit(&d->pci);
1160 memory_region_destroy(&d->mmio);
1164 static void intel_hda_write_config(PCIDevice *pci, uint32_t addr,
1165 uint32_t val, int len)
1167 IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1169 pci_default_write_config(pci, addr, val, len);
1171 msi_write_config(pci, addr, val, len);
1175 static int intel_hda_post_load(void *opaque, int version)
1177 IntelHDAState* d = opaque;
1180 dprint(d, 1, "%s\n", __FUNCTION__);
1181 for (i = 0; i < ARRAY_SIZE(d->st); i++) {
1182 if (d->st[i].ctl & 0x02) {
1183 intel_hda_parse_bdl(d, &d->st[i]);
1186 intel_hda_update_irq(d);
1190 static const VMStateDescription vmstate_intel_hda_stream = {
1191 .name = "intel-hda-stream",
1193 .fields = (VMStateField []) {
1194 VMSTATE_UINT32(ctl, IntelHDAStream),
1195 VMSTATE_UINT32(lpib, IntelHDAStream),
1196 VMSTATE_UINT32(cbl, IntelHDAStream),
1197 VMSTATE_UINT32(lvi, IntelHDAStream),
1198 VMSTATE_UINT32(fmt, IntelHDAStream),
1199 VMSTATE_UINT32(bdlp_lbase, IntelHDAStream),
1200 VMSTATE_UINT32(bdlp_ubase, IntelHDAStream),
1201 VMSTATE_END_OF_LIST()
1205 static const VMStateDescription vmstate_intel_hda = {
1206 .name = "intel-hda",
1208 .post_load = intel_hda_post_load,
1209 .fields = (VMStateField []) {
1210 VMSTATE_PCI_DEVICE(pci, IntelHDAState),
1213 VMSTATE_UINT32(g_ctl, IntelHDAState),
1214 VMSTATE_UINT32(wake_en, IntelHDAState),
1215 VMSTATE_UINT32(state_sts, IntelHDAState),
1216 VMSTATE_UINT32(int_ctl, IntelHDAState),
1217 VMSTATE_UINT32(int_sts, IntelHDAState),
1218 VMSTATE_UINT32(wall_clk, IntelHDAState),
1219 VMSTATE_UINT32(corb_lbase, IntelHDAState),
1220 VMSTATE_UINT32(corb_ubase, IntelHDAState),
1221 VMSTATE_UINT32(corb_rp, IntelHDAState),
1222 VMSTATE_UINT32(corb_wp, IntelHDAState),
1223 VMSTATE_UINT32(corb_ctl, IntelHDAState),
1224 VMSTATE_UINT32(corb_sts, IntelHDAState),
1225 VMSTATE_UINT32(corb_size, IntelHDAState),
1226 VMSTATE_UINT32(rirb_lbase, IntelHDAState),
1227 VMSTATE_UINT32(rirb_ubase, IntelHDAState),
1228 VMSTATE_UINT32(rirb_wp, IntelHDAState),
1229 VMSTATE_UINT32(rirb_cnt, IntelHDAState),
1230 VMSTATE_UINT32(rirb_ctl, IntelHDAState),
1231 VMSTATE_UINT32(rirb_sts, IntelHDAState),
1232 VMSTATE_UINT32(rirb_size, IntelHDAState),
1233 VMSTATE_UINT32(dp_lbase, IntelHDAState),
1234 VMSTATE_UINT32(dp_ubase, IntelHDAState),
1235 VMSTATE_UINT32(icw, IntelHDAState),
1236 VMSTATE_UINT32(irr, IntelHDAState),
1237 VMSTATE_UINT32(ics, IntelHDAState),
1238 VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0,
1239 vmstate_intel_hda_stream,
1242 /* additional state info */
1243 VMSTATE_UINT32(rirb_count, IntelHDAState),
1244 VMSTATE_INT64(wall_base_ns, IntelHDAState),
1246 VMSTATE_END_OF_LIST()
1250 static PCIDeviceInfo intel_hda_info = {
1251 .qdev.name = "intel-hda",
1252 .qdev.desc = "Intel HD Audio Controller",
1253 .qdev.size = sizeof(IntelHDAState),
1254 .qdev.vmsd = &vmstate_intel_hda,
1255 .qdev.reset = intel_hda_reset,
1256 .init = intel_hda_init,
1257 .exit = intel_hda_exit,
1258 .config_write = intel_hda_write_config,
1259 .vendor_id = PCI_VENDOR_ID_INTEL,
1260 .device_id = 0x2668,
1262 .class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO,
1263 .qdev.props = (Property[]) {
1264 DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0),
1265 DEFINE_PROP_UINT32("msi", IntelHDAState, msi, 1),
1266 DEFINE_PROP_END_OF_LIST(),
1270 static void intel_hda_register(void)
1272 pci_qdev_register(&intel_hda_info);
1274 device_init(intel_hda_register);
1277 * create intel hda controller with codec attached to it,
1278 * so '-soundhw hda' works.
1280 int intel_hda_and_codec_init(PCIBus *bus)
1282 PCIDevice *controller;
1286 controller = pci_create_simple(bus, -1, "intel-hda");
1287 hdabus = QLIST_FIRST(&controller->qdev.child_bus);
1288 codec = qdev_create(hdabus, "hda-duplex");
1289 qdev_init_nofail(codec);