target-xtensa/translate.c

   1 /*
   2  * Xtensa ISA:
   3  * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
   4  *
   5  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions are met:
  10  *     * Redistributions of source code must retain the above copyright
  11  *       notice, this list of conditions and the following disclaimer.
  12  *     * Redistributions in binary form must reproduce the above copyright
  13  *       notice, this list of conditions and the following disclaimer in the
  14  *       documentation and/or other materials provided with the distribution.
  15  *     * Neither the name of the Open Source and Linux Lab nor the
  16  *       names of its contributors may be used to endorse or promote products
  17  *       derived from this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  23  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  25  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  26  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 #include <stdio.h>
  32
  33 #include "cpu.h"
  34 #include "exec/exec-all.h"
  35 #include "disas/disas.h"
  36 #include "tcg-op.h"
  37 #include "qemu/log.h"
  38 #include "sysemu/sysemu.h"
  39
  40 #include "helper.h"
  41 #define GEN_HELPER 1
  42 #include "helper.h"
  43
  44 typedef struct DisasContext {
  45     const XtensaConfig *config;
  46     TranslationBlock *tb;
  47     uint32_t pc;
  48     uint32_t next_pc;
  49     int cring;
  50     int ring;
  51     uint32_t lbeg;
  52     uint32_t lend;
  53     TCGv_i32 litbase;
  54     int is_jmp;
  55     int singlestep_enabled;
  56
  57     bool sar_5bit;
  58     bool sar_m32_5bit;
  59     bool sar_m32_allocated;
  60     TCGv_i32 sar_m32;
  61
  62     uint32_t ccount_delta;
  63     unsigned used_window;
  64
  65     bool debug;
  66     bool icount;
  67     TCGv_i32 next_icount;
  68
  69     unsigned cpenable;
  70 } DisasContext;
  71
  72 static TCGv_ptr cpu_env;
  73 static TCGv_i32 cpu_pc;
  74 static TCGv_i32 cpu_R[16];
  75 static TCGv_i32 cpu_FR[16];
  76 static TCGv_i32 cpu_SR[256];
  77 static TCGv_i32 cpu_UR[256];
  78
  79 #include "exec/gen-icount.h"
  80
  81 typedef struct XtensaReg {
  82     const char *name;
  83     uint64_t opt_bits;
  84     enum {
  85         SR_R = 1,
  86         SR_W = 2,
  87         SR_X = 4,
  88         SR_RW = 3,
  89         SR_RWX = 7,
  90     } access;
  91 } XtensaReg;
  92
  93 #define XTENSA_REG_ACCESS(regname, opt, acc) { \
  94         .name = (regname), \
  95         .opt_bits = XTENSA_OPTION_BIT(opt), \
  96         .access = (acc), \
  97     }
  98
  99 #define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX)
 100
 101 #define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \
 102         .name = (regname), \
 103         .opt_bits = (opt), \
 104         .access = (acc), \
 105     }
 106
 107 #define XTENSA_REG_BITS(regname, opt) \
 108     XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX)
 109
 110 static const XtensaReg sregnames[256] = {
 111     [LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP),
 112     [LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP),
 113     [LCOUNT] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP),
 114     [SAR] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL),
 115     [BR] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN),
 116     [LITBASE] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R),
 117     [SCOMPARE1] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE),
 118     [ACCLO] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16),
 119     [ACCHI] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16),
 120     [MR] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16),
 121     [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16),
 122     [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16),
 123     [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16),
 124     [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER),
 125     [WINDOW_START] = XTENSA_REG("WINDOW_START",
 126             XTENSA_OPTION_WINDOWED_REGISTER),
 127     [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU),
 128     [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU),
 129     [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU),
 130     [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU),
 131     [IBREAKENABLE] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG),
 132     [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR),
 133     [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL),
 134     [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG),
 135     [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG),
 136     [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG),
 137     [DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG),
 138     [DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG),
 139     [DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG),
 140     [CONFIGID0] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL, SR_R),
 141     [EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION),
 142     [EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 143     [EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 144     [EPC1 + 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 145     [EPC1 + 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 146     [EPC1 + 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 147     [EPC1 + 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 148     [DEPC] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION),
 149     [EPS2] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 150     [EPS2 + 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 151     [EPS2 + 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 152     [EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 153     [EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 154     [EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 155     [CONFIGID1] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL, SR_R),
 156     [EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION),
 157     [EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2",
 158             XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 159     [EXCSAVE1 + 2] = XTENSA_REG("EXCSAVE3",
 160             XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 161     [EXCSAVE1 + 3] = XTENSA_REG("EXCSAVE4",
 162             XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 163     [EXCSAVE1 + 4] = XTENSA_REG("EXCSAVE5",
 164             XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 165     [EXCSAVE1 + 5] = XTENSA_REG("EXCSAVE6",
 166             XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 167     [EXCSAVE1 + 6] = XTENSA_REG("EXCSAVE7",
 168             XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
 169     [CPENABLE] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR),
 170     [INTSET] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT, SR_RW),
 171     [INTCLEAR] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT, SR_W),
 172     [INTENABLE] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT),
 173     [PS] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL),
 174     [VECBASE] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR),
 175     [EXCCAUSE] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION),
 176     [DEBUGCAUSE] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG, SR_R),
 177     [CCOUNT] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT),
 178     [PRID] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID, SR_R),
 179     [ICOUNT] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG),
 180     [ICOUNTLEVEL] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG),
 181     [EXCVADDR] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION),
 182     [CCOMPARE] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT),
 183     [CCOMPARE + 1] = XTENSA_REG("CCOMPARE1",
 184             XTENSA_OPTION_TIMER_INTERRUPT),
 185     [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2",
 186             XTENSA_OPTION_TIMER_INTERRUPT),
 187     [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR),
 188     [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR),
 189     [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR),
 190     [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR),
 191 };
 192
 193 static const XtensaReg uregnames[256] = {
 194     [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER),
 195     [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR),
 196     [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR),
 197 };
 198
 199 void xtensa_translate_init(void)
 200 {
 201     static const char * const regnames[] = {
 202         "ar0", "ar1", "ar2", "ar3",
 203         "ar4", "ar5", "ar6", "ar7",
 204         "ar8", "ar9", "ar10", "ar11",
 205         "ar12", "ar13", "ar14", "ar15",
 206     };
 207     static const char * const fregnames[] = {
 208         "f0", "f1", "f2", "f3",
 209         "f4", "f5", "f6", "f7",
 210         "f8", "f9", "f10", "f11",
 211         "f12", "f13", "f14", "f15",
 212     };
 213     int i;
 214
 215     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
 216     cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
 217             offsetof(CPUXtensaState, pc), "pc");
 218
 219     for (i = 0; i < 16; i++) {
 220         cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
 221                 offsetof(CPUXtensaState, regs[i]),
 222                 regnames[i]);
 223     }
 224
 225     for (i = 0; i < 16; i++) {
 226         cpu_FR[i] = tcg_global_mem_new_i32(TCG_AREG0,
 227                 offsetof(CPUXtensaState, fregs[i]),
 228                 fregnames[i]);
 229     }
 230
 231     for (i = 0; i < 256; ++i) {
 232         if (sregnames[i].name) {
 233             cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
 234                     offsetof(CPUXtensaState, sregs[i]),
 235                     sregnames[i].name);
 236         }
 237     }
 238
 239     for (i = 0; i < 256; ++i) {
 240         if (uregnames[i].name) {
 241             cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
 242                     offsetof(CPUXtensaState, uregs[i]),
 243                     uregnames[i].name);
 244         }
 245     }
 246 }
 247
 248 static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt)
 249 {
 250     return xtensa_option_bits_enabled(dc->config, opt);
 251 }
 252
 253 static inline bool option_enabled(DisasContext *dc, int opt)
 254 {
 255     return xtensa_option_enabled(dc->config, opt);
 256 }
 257
 258 static void init_litbase(DisasContext *dc)
 259 {
 260     if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
 261         dc->litbase = tcg_temp_local_new_i32();
 262         tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
 263     }
 264 }
 265
 266 static void reset_litbase(DisasContext *dc)
 267 {
 268     if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
 269         tcg_temp_free(dc->litbase);
 270     }
 271 }
 272
 273 static void init_sar_tracker(DisasContext *dc)
 274 {
 275     dc->sar_5bit = false;
 276     dc->sar_m32_5bit = false;
 277     dc->sar_m32_allocated = false;
 278 }
 279
 280 static void reset_sar_tracker(DisasContext *dc)
 281 {
 282     if (dc->sar_m32_allocated) {
 283         tcg_temp_free(dc->sar_m32);
 284     }
 285 }
 286
 287 static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
 288 {
 289     tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
 290     if (dc->sar_m32_5bit) {
 291         tcg_gen_discard_i32(dc->sar_m32);
 292     }
 293     dc->sar_5bit = true;
 294     dc->sar_m32_5bit = false;
 295 }
 296
 297 static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
 298 {
 299     TCGv_i32 tmp = tcg_const_i32(32);
 300     if (!dc->sar_m32_allocated) {
 301         dc->sar_m32 = tcg_temp_local_new_i32();
 302         dc->sar_m32_allocated = true;
 303     }
 304     tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
 305     tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
 306     dc->sar_5bit = false;
 307     dc->sar_m32_5bit = true;
 308     tcg_temp_free(tmp);
 309 }
 310
 311 static void gen_advance_ccount_cond(DisasContext *dc)
 312 {
 313     if (dc->ccount_delta > 0) {
 314         TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);
 315         gen_helper_advance_ccount(cpu_env, tmp);
 316         tcg_temp_free(tmp);
 317     }
 318 }
 319
 320 static void gen_advance_ccount(DisasContext *dc)
 321 {
 322     gen_advance_ccount_cond(dc);
 323     dc->ccount_delta = 0;
 324 }
 325
 326 static void reset_used_window(DisasContext *dc)
 327 {
 328     dc->used_window = 0;
 329 }
 330
 331 static void gen_exception(DisasContext *dc, int excp)
 332 {
 333     TCGv_i32 tmp = tcg_const_i32(excp);
 334     gen_advance_ccount(dc);
 335     gen_helper_exception(cpu_env, tmp);
 336     tcg_temp_free(tmp);
 337 }
 338
 339 static void gen_exception_cause(DisasContext *dc, uint32_t cause)
 340 {
 341     TCGv_i32 tpc = tcg_const_i32(dc->pc);
 342     TCGv_i32 tcause = tcg_const_i32(cause);
 343     gen_advance_ccount(dc);
 344     gen_helper_exception_cause(cpu_env, tpc, tcause);
 345     tcg_temp_free(tpc);
 346     tcg_temp_free(tcause);
 347     if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
 348             cause == SYSCALL_CAUSE) {
 349         dc->is_jmp = DISAS_UPDATE;
 350     }
 351 }
 352
 353 static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
 354         TCGv_i32 vaddr)
 355 {
 356     TCGv_i32 tpc = tcg_const_i32(dc->pc);
 357     TCGv_i32 tcause = tcg_const_i32(cause);
 358     gen_advance_ccount(dc);
 359     gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr);
 360     tcg_temp_free(tpc);
 361     tcg_temp_free(tcause);
 362 }
 363
 364 static void gen_debug_exception(DisasContext *dc, uint32_t cause)
 365 {
 366     TCGv_i32 tpc = tcg_const_i32(dc->pc);
 367     TCGv_i32 tcause = tcg_const_i32(cause);
 368     gen_advance_ccount(dc);
 369     gen_helper_debug_exception(cpu_env, tpc, tcause);
 370     tcg_temp_free(tpc);
 371     tcg_temp_free(tcause);
 372     if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
 373         dc->is_jmp = DISAS_UPDATE;
 374     }
 375 }
 376
 377 static void gen_check_privilege(DisasContext *dc)
 378 {
 379     if (dc->cring) {
 380         gen_exception_cause(dc, PRIVILEGED_CAUSE);
 381         dc->is_jmp = DISAS_UPDATE;
 382     }
 383 }
 384
 385 static void gen_check_cpenable(DisasContext *dc, unsigned cp)
 386 {
 387     if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) &&
 388             !(dc->cpenable & (1 << cp))) {
 389         gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp);
 390         dc->is_jmp = DISAS_UPDATE;
 391     }
 392 }
 393
 394 static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
 395 {
 396     tcg_gen_mov_i32(cpu_pc, dest);
 397     gen_advance_ccount(dc);
 398     if (dc->icount) {
 399         tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
 400     }
 401     if (dc->singlestep_enabled) {
 402         gen_exception(dc, EXCP_DEBUG);
 403     } else {
 404         if (slot >= 0) {
 405             tcg_gen_goto_tb(slot);
 406             tcg_gen_exit_tb((uintptr_t)dc->tb + slot);
 407         } else {
 408             tcg_gen_exit_tb(0);
 409         }
 410     }
 411     dc->is_jmp = DISAS_UPDATE;
 412 }
 413
 414 static void gen_jump(DisasContext *dc, TCGv dest)
 415 {
 416     gen_jump_slot(dc, dest, -1);
 417 }
 418
 419 static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
 420 {
 421     TCGv_i32 tmp = tcg_const_i32(dest);
 422     if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
 423         slot = -1;
 424     }
 425     gen_jump_slot(dc, tmp, slot);
 426     tcg_temp_free(tmp);
 427 }
 428
 429 static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
 430         int slot)
 431 {
 432     TCGv_i32 tcallinc = tcg_const_i32(callinc);
 433
 434     tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
 435             tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
 436     tcg_temp_free(tcallinc);
 437     tcg_gen_movi_i32(cpu_R[callinc << 2],
 438             (callinc << 30) | (dc->next_pc & 0x3fffffff));
 439     gen_jump_slot(dc, dest, slot);
 440 }
 441
 442 static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
 443 {
 444     gen_callw_slot(dc, callinc, dest, -1);
 445 }
 446
 447 static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
 448 {
 449     TCGv_i32 tmp = tcg_const_i32(dest);
 450     if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
 451         slot = -1;
 452     }
 453     gen_callw_slot(dc, callinc, tmp, slot);
 454     tcg_temp_free(tmp);
 455 }
 456
 457 static bool gen_check_loop_end(DisasContext *dc, int slot)
 458 {
 459     if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
 460             !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
 461             dc->next_pc == dc->lend) {
 462         int label = gen_new_label();
 463
 464         gen_advance_ccount(dc);
 465         tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
 466         tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
 467         gen_jumpi(dc, dc->lbeg, slot);
 468         gen_set_label(label);
 469         gen_jumpi(dc, dc->next_pc, -1);
 470         return true;
 471     }
 472     return false;
 473 }
 474
 475 static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
 476 {
 477     if (!gen_check_loop_end(dc, slot)) {
 478         gen_jumpi(dc, dc->next_pc, slot);
 479     }
 480 }
 481
 482 static void gen_brcond(DisasContext *dc, TCGCond cond,
 483         TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
 484 {
 485     int label = gen_new_label();
 486
 487     gen_advance_ccount(dc);
 488     tcg_gen_brcond_i32(cond, t0, t1, label);
 489     gen_jumpi_check_loop_end(dc, 0);
 490     gen_set_label(label);
 491     gen_jumpi(dc, dc->pc + offset, 1);
 492 }
 493
 494 static void gen_brcondi(DisasContext *dc, TCGCond cond,
 495         TCGv_i32 t0, uint32_t t1, uint32_t offset)
 496 {
 497     TCGv_i32 tmp = tcg_const_i32(t1);
 498     gen_brcond(dc, cond, t0, tmp, offset);
 499     tcg_temp_free(tmp);
 500 }
 501
 502 static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
 503 {
 504     if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {
 505         if (sregnames[sr].name) {
 506             qemu_log("SR %s is not configured\n", sregnames[sr].name);
 507         } else {
 508             qemu_log("SR %d is not implemented\n", sr);
 509         }
 510         gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
 511         return false;
 512     } else if (!(sregnames[sr].access & access)) {
 513         static const char * const access_text[] = {
 514             [SR_R] = "rsr",
 515             [SR_W] = "wsr",
 516             [SR_X] = "xsr",
 517         };
 518         assert(access < ARRAY_SIZE(access_text) && access_text[access]);
 519         qemu_log("SR %s is not available for %s\n", sregnames[sr].name,
 520                 access_text[access]);
 521         gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
 522         return false;
 523     }
 524     return true;
 525 }
 526
 527 static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
 528 {
 529     gen_advance_ccount(dc);
 530     tcg_gen_mov_i32(d, cpu_SR[sr]);
 531 }
 532
 533 static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
 534 {
 535     tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
 536     tcg_gen_or_i32(d, d, cpu_SR[sr]);
 537     tcg_gen_andi_i32(d, d, 0xfffffffc);
 538 }
 539
 540 static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
 541 {
 542     static void (* const rsr_handler[256])(DisasContext *dc,
 543             TCGv_i32 d, uint32_t sr) = {
 544         [CCOUNT] = gen_rsr_ccount,
 545         [PTEVADDR] = gen_rsr_ptevaddr,
 546     };
 547
 548     if (rsr_handler[sr]) {
 549         rsr_handler[sr](dc, d, sr);
 550     } else {
 551         tcg_gen_mov_i32(d, cpu_SR[sr]);
 552     }
 553 }
 554
 555 static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
 556 {
 557     gen_helper_wsr_lbeg(cpu_env, s);
 558     gen_jumpi_check_loop_end(dc, 0);
 559 }
 560
 561 static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
 562 {
 563     gen_helper_wsr_lend(cpu_env, s);
 564     gen_jumpi_check_loop_end(dc, 0);
 565 }
 566
 567 static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
 568 {
 569     tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
 570     if (dc->sar_m32_5bit) {
 571         tcg_gen_discard_i32(dc->sar_m32);
 572     }
 573     dc->sar_5bit = false;
 574     dc->sar_m32_5bit = false;
 575 }
 576
 577 static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
 578 {
 579     tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
 580 }
 581
 582 static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
 583 {
 584     tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
 585     /* This can change tb->flags, so exit tb */
 586     gen_jumpi_check_loop_end(dc, -1);
 587 }
 588
 589 static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
 590 {
 591     tcg_gen_ext8s_i32(cpu_SR[sr], s);
 592 }
 593
 594 static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 595 {
 596     gen_helper_wsr_windowbase(cpu_env, v);
 597     reset_used_window(dc);
 598 }
 599
 600 static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 601 {
 602     tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1);
 603     reset_used_window(dc);
 604 }
 605
 606 static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 607 {
 608     tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
 609 }
 610
 611 static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 612 {
 613     gen_helper_wsr_rasid(cpu_env, v);
 614     /* This can change tb->flags, so exit tb */
 615     gen_jumpi_check_loop_end(dc, -1);
 616 }
 617
 618 static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 619 {
 620     tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
 621 }
 622
 623 static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 624 {
 625     gen_helper_wsr_ibreakenable(cpu_env, v);
 626     gen_jumpi_check_loop_end(dc, 0);
 627 }
 628
 629 static void gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 630 {
 631     tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f);
 632 }
 633
 634 static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 635 {
 636     unsigned id = sr - IBREAKA;
 637
 638     if (id < dc->config->nibreak) {
 639         TCGv_i32 tmp = tcg_const_i32(id);
 640         gen_helper_wsr_ibreaka(cpu_env, tmp, v);
 641         tcg_temp_free(tmp);
 642         gen_jumpi_check_loop_end(dc, 0);
 643     }
 644 }
 645
 646 static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 647 {
 648     unsigned id = sr - DBREAKA;
 649
 650     if (id < dc->config->ndbreak) {
 651         TCGv_i32 tmp = tcg_const_i32(id);
 652         gen_helper_wsr_dbreaka(cpu_env, tmp, v);
 653         tcg_temp_free(tmp);
 654     }
 655 }
 656
 657 static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 658 {
 659     unsigned id = sr - DBREAKC;
 660
 661     if (id < dc->config->ndbreak) {
 662         TCGv_i32 tmp = tcg_const_i32(id);
 663         gen_helper_wsr_dbreakc(cpu_env, tmp, v);
 664         tcg_temp_free(tmp);
 665     }
 666 }
 667
 668 static void gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 669 {
 670     tcg_gen_andi_i32(cpu_SR[sr], v, 0xff);
 671     /* This can change tb->flags, so exit tb */
 672     gen_jumpi_check_loop_end(dc, -1);
 673 }
 674
 675 static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 676 {
 677     tcg_gen_andi_i32(cpu_SR[sr], v,
 678             dc->config->inttype_mask[INTTYPE_SOFTWARE]);
 679     gen_helper_check_interrupts(cpu_env);
 680     gen_jumpi_check_loop_end(dc, 0);
 681 }
 682
 683 static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 684 {
 685     TCGv_i32 tmp = tcg_temp_new_i32();
 686
 687     tcg_gen_andi_i32(tmp, v,
 688             dc->config->inttype_mask[INTTYPE_EDGE] |
 689             dc->config->inttype_mask[INTTYPE_NMI] |
 690             dc->config->inttype_mask[INTTYPE_SOFTWARE]);
 691     tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
 692     tcg_temp_free(tmp);
 693     gen_helper_check_interrupts(cpu_env);
 694 }
 695
 696 static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 697 {
 698     tcg_gen_mov_i32(cpu_SR[sr], v);
 699     gen_helper_check_interrupts(cpu_env);
 700     gen_jumpi_check_loop_end(dc, 0);
 701 }
 702
 703 static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 704 {
 705     uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
 706         PS_UM | PS_EXCM | PS_INTLEVEL;
 707
 708     if (option_enabled(dc, XTENSA_OPTION_MMU)) {
 709         mask |= PS_RING;
 710     }
 711     tcg_gen_andi_i32(cpu_SR[sr], v, mask);
 712     reset_used_window(dc);
 713     gen_helper_check_interrupts(cpu_env);
 714     /* This can change mmu index and tb->flags, so exit tb */
 715     gen_jumpi_check_loop_end(dc, -1);
 716 }
 717
 718 static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 719 {
 720     if (dc->icount) {
 721         tcg_gen_mov_i32(dc->next_icount, v);
 722     } else {
 723         tcg_gen_mov_i32(cpu_SR[sr], v);
 724     }
 725 }
 726
 727 static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 728 {
 729     tcg_gen_andi_i32(cpu_SR[sr], v, 0xf);
 730     /* This can change tb->flags, so exit tb */
 731     gen_jumpi_check_loop_end(dc, -1);
 732 }
 733
 734 static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
 735 {
 736     uint32_t id = sr - CCOMPARE;
 737     if (id < dc->config->nccompare) {
 738         uint32_t int_bit = 1 << dc->config->timerint[id];
 739         gen_advance_ccount(dc);
 740         tcg_gen_mov_i32(cpu_SR[sr], v);
 741         tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
 742         gen_helper_check_interrupts(cpu_env);
 743     }
 744 }
 745
 746 static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
 747 {
 748     static void (* const wsr_handler[256])(DisasContext *dc,
 749             uint32_t sr, TCGv_i32 v) = {
 750         [LBEG] = gen_wsr_lbeg,
 751         [LEND] = gen_wsr_lend,
 752         [SAR] = gen_wsr_sar,
 753         [BR] = gen_wsr_br,
 754         [LITBASE] = gen_wsr_litbase,
 755         [ACCHI] = gen_wsr_acchi,
 756         [WINDOW_BASE] = gen_wsr_windowbase,
 757         [WINDOW_START] = gen_wsr_windowstart,
 758         [PTEVADDR] = gen_wsr_ptevaddr,
 759         [RASID] = gen_wsr_rasid,
 760         [ITLBCFG] = gen_wsr_tlbcfg,
 761         [DTLBCFG] = gen_wsr_tlbcfg,
 762         [IBREAKENABLE] = gen_wsr_ibreakenable,
 763         [ATOMCTL] = gen_wsr_atomctl,
 764         [IBREAKA] = gen_wsr_ibreaka,
 765         [IBREAKA + 1] = gen_wsr_ibreaka,
 766         [DBREAKA] = gen_wsr_dbreaka,
 767         [DBREAKA + 1] = gen_wsr_dbreaka,
 768         [DBREAKC] = gen_wsr_dbreakc,
 769         [DBREAKC + 1] = gen_wsr_dbreakc,
 770         [CPENABLE] = gen_wsr_cpenable,
 771         [INTSET] = gen_wsr_intset,
 772         [INTCLEAR] = gen_wsr_intclear,
 773         [INTENABLE] = gen_wsr_intenable,
 774         [PS] = gen_wsr_ps,
 775         [ICOUNT] = gen_wsr_icount,
 776         [ICOUNTLEVEL] = gen_wsr_icountlevel,
 777         [CCOMPARE] = gen_wsr_ccompare,
 778         [CCOMPARE + 1] = gen_wsr_ccompare,
 779         [CCOMPARE + 2] = gen_wsr_ccompare,
 780     };
 781
 782     if (wsr_handler[sr]) {
 783         wsr_handler[sr](dc, sr, s);
 784     } else {
 785         tcg_gen_mov_i32(cpu_SR[sr], s);
 786     }
 787 }
 788
 789 static void gen_wur(uint32_t ur, TCGv_i32 s)
 790 {
 791     switch (ur) {
 792     case FCR:
 793         gen_helper_wur_fcr(cpu_env, s);
 794         break;
 795
 796     case FSR:
 797         tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80);
 798         break;
 799
 800     default:
 801         tcg_gen_mov_i32(cpu_UR[ur], s);
 802         break;
 803     }
 804 }
 805
 806 static void gen_load_store_alignment(DisasContext *dc, int shift,
 807         TCGv_i32 addr, bool no_hw_alignment)
 808 {
 809     if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
 810         tcg_gen_andi_i32(addr, addr, ~0 << shift);
 811     } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
 812             no_hw_alignment) {
 813         int label = gen_new_label();
 814         TCGv_i32 tmp = tcg_temp_new_i32();
 815         tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
 816         tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
 817         gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
 818         gen_set_label(label);
 819         tcg_temp_free(tmp);
 820     }
 821 }
 822
 823 static void gen_waiti(DisasContext *dc, uint32_t imm4)
 824 {
 825     TCGv_i32 pc = tcg_const_i32(dc->next_pc);
 826     TCGv_i32 intlevel = tcg_const_i32(imm4);
 827     gen_advance_ccount(dc);
 828     gen_helper_waiti(cpu_env, pc, intlevel);
 829     tcg_temp_free(pc);
 830     tcg_temp_free(intlevel);
 831 }
 832
 833 static void gen_window_check1(DisasContext *dc, unsigned r1)
 834 {
 835     if (dc->tb->flags & XTENSA_TBFLAG_EXCM) {
 836         return;
 837     }
 838     if (option_enabled(dc, XTENSA_OPTION_WINDOWED_REGISTER) &&
 839             r1 / 4 > dc->used_window) {
 840         int label = gen_new_label();
 841         TCGv_i32 ws = tcg_temp_new_i32();
 842
 843         dc->used_window = r1 / 4;
 844         tcg_gen_deposit_i32(ws, cpu_SR[WINDOW_START], cpu_SR[WINDOW_START],
 845                 dc->config->nareg / 4, dc->config->nareg / 4);
 846         tcg_gen_shr_i32(ws, ws, cpu_SR[WINDOW_BASE]);
 847         tcg_gen_andi_i32(ws, ws, (2 << (r1 / 4)) - 2);
 848         tcg_gen_brcondi_i32(TCG_COND_EQ, ws, 0, label);
 849         {
 850             TCGv_i32 pc = tcg_const_i32(dc->pc);
 851             TCGv_i32 w = tcg_const_i32(r1 / 4);
 852
 853             gen_advance_ccount_cond(dc);
 854             gen_helper_window_check(cpu_env, pc, w);
 855
 856             tcg_temp_free(w);
 857             tcg_temp_free(pc);
 858         }
 859         gen_set_label(label);
 860         tcg_temp_free(ws);
 861     }
 862 }
 863
 864 static void gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)
 865 {
 866     gen_window_check1(dc, r1 > r2 ? r1 : r2);
 867 }
 868
 869 static void gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
 870         unsigned r3)
 871 {
 872     gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
 873 }
 874
 875 static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
 876 {
 877     TCGv_i32 m = tcg_temp_new_i32();
 878
 879     if (hi) {
 880         (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
 881     } else {
 882         (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
 883     }
 884     return m;
 885 }
 886
 887 static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
 888 {
 889 #define HAS_OPTION_BITS(opt) do { \
 890         if (!option_bits_enabled(dc, opt)) { \
 891             qemu_log("Option is not enabled %s:%d\n", \
 892                     __FILE__, __LINE__); \
 893             goto invalid_opcode; \
 894         } \
 895     } while (0)
 896
 897 #define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
 898
 899 #define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
 900 #define RESERVED() do { \
 901         qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
 902                 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
 903         goto invalid_opcode; \
 904     } while (0)
 905
 906
 907 #ifdef TARGET_WORDS_BIGENDIAN
 908 #define OP0 (((b0) & 0xf0) >> 4)
 909 #define OP1 (((b2) & 0xf0) >> 4)
 910 #define OP2 ((b2) & 0xf)
 911 #define RRR_R ((b1) & 0xf)
 912 #define RRR_S (((b1) & 0xf0) >> 4)
 913 #define RRR_T ((b0) & 0xf)
 914 #else
 915 #define OP0 (((b0) & 0xf))
 916 #define OP1 (((b2) & 0xf))
 917 #define OP2 (((b2) & 0xf0) >> 4)
 918 #define RRR_R (((b1) & 0xf0) >> 4)
 919 #define RRR_S (((b1) & 0xf))
 920 #define RRR_T (((b0) & 0xf0) >> 4)
 921 #endif
 922 #define RRR_X ((RRR_R & 0x4) >> 2)
 923 #define RRR_Y ((RRR_T & 0x4) >> 2)
 924 #define RRR_W (RRR_R & 0x3)
 925
 926 #define RRRN_R RRR_R
 927 #define RRRN_S RRR_S
 928 #define RRRN_T RRR_T
 929
 930 #define RRI4_R RRR_R
 931 #define RRI4_S RRR_S
 932 #define RRI4_T RRR_T
 933 #ifdef TARGET_WORDS_BIGENDIAN
 934 #define RRI4_IMM4 ((b2) & 0xf)
 935 #else
 936 #define RRI4_IMM4 (((b2) & 0xf0) >> 4)
 937 #endif
 938
 939 #define RRI8_R RRR_R
 940 #define RRI8_S RRR_S
 941 #define RRI8_T RRR_T
 942 #define RRI8_IMM8 (b2)
 943 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
 944
 945 #ifdef TARGET_WORDS_BIGENDIAN
 946 #define RI16_IMM16 (((b1) << 8) | (b2))
 947 #else
 948 #define RI16_IMM16 (((b2) << 8) | (b1))
 949 #endif
 950
 951 #ifdef TARGET_WORDS_BIGENDIAN
 952 #define CALL_N (((b0) & 0xc) >> 2)
 953 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
 954 #else
 955 #define CALL_N (((b0) & 0x30) >> 4)
 956 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
 957 #endif
 958 #define CALL_OFFSET_SE \
 959     (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
 960
 961 #define CALLX_N CALL_N
 962 #ifdef TARGET_WORDS_BIGENDIAN
 963 #define CALLX_M ((b0) & 0x3)
 964 #else
 965 #define CALLX_M (((b0) & 0xc0) >> 6)
 966 #endif
 967 #define CALLX_S RRR_S
 968
 969 #define BRI12_M CALLX_M
 970 #define BRI12_S RRR_S
 971 #ifdef TARGET_WORDS_BIGENDIAN
 972 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
 973 #else
 974 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
 975 #endif
 976 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
 977
 978 #define BRI8_M BRI12_M
 979 #define BRI8_R RRI8_R
 980 #define BRI8_S RRI8_S
 981 #define BRI8_IMM8 RRI8_IMM8
 982 #define BRI8_IMM8_SE RRI8_IMM8_SE
 983
 984 #define RSR_SR (b1)
 985
 986     uint8_t b0 = cpu_ldub_code(env, dc->pc);
 987     uint8_t b1 = cpu_ldub_code(env, dc->pc + 1);
 988     uint8_t b2 = 0;
 989
 990     static const uint32_t B4CONST[] = {
 991         0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
 992     };
 993
 994     static const uint32_t B4CONSTU[] = {
 995         32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
 996     };
 997
 998     if (OP0 >= 8) {
 999         dc->next_pc = dc->pc + 2;
1000         HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
1001     } else {
1002         dc->next_pc = dc->pc + 3;
1003         b2 = cpu_ldub_code(env, dc->pc + 2);
1004     }
1005
1006     switch (OP0) {
1007     case 0: /*QRST*/
1008         switch (OP1) {
1009         case 0: /*RST0*/
1010             switch (OP2) {
1011             case 0: /*ST0*/
1012                 if ((RRR_R & 0xc) == 0x8) {
1013                     HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1014                 }
1015
1016                 switch (RRR_R) {
1017                 case 0: /*SNM0*/
1018                     switch (CALLX_M) {
1019                     case 0: /*ILL*/
1020                         gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1021                         break;
1022
1023                     case 1: /*reserved*/
1024                         RESERVED();
1025                         break;
1026
1027                     case 2: /*JR*/
1028                         switch (CALLX_N) {
1029                         case 0: /*RET*/
1030                         case 2: /*JX*/
1031                             gen_window_check1(dc, CALLX_S);
1032                             gen_jump(dc, cpu_R[CALLX_S]);
1033                             break;
1034
1035                         case 1: /*RETWw*/
1036                             HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1037                             {
1038                                 TCGv_i32 tmp = tcg_const_i32(dc->pc);
1039                                 gen_advance_ccount(dc);
1040                                 gen_helper_retw(tmp, cpu_env, tmp);
1041                                 gen_jump(dc, tmp);
1042                                 tcg_temp_free(tmp);
1043                             }
1044                             break;
1045
1046                         case 3: /*reserved*/
1047                             RESERVED();
1048                             break;
1049                         }
1050                         break;
1051
1052                     case 3: /*CALLX*/
1053                         gen_window_check2(dc, CALLX_S, CALLX_N << 2);
1054                         switch (CALLX_N) {
1055                         case 0: /*CALLX0*/
1056                             {
1057                                 TCGv_i32 tmp = tcg_temp_new_i32();
1058                                 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1059                                 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
1060                                 gen_jump(dc, tmp);
1061                                 tcg_temp_free(tmp);
1062                             }
1063                             break;
1064
1065                         case 1: /*CALLX4w*/
1066                         case 2: /*CALLX8w*/
1067                         case 3: /*CALLX12w*/
1068                             HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1069                             {
1070                                 TCGv_i32 tmp = tcg_temp_new_i32();
1071
1072                                 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1073                                 gen_callw(dc, CALLX_N, tmp);
1074                                 tcg_temp_free(tmp);
1075                             }
1076                             break;
1077                         }
1078                         break;
1079                     }
1080                     break;
1081
1082                 case 1: /*MOVSPw*/
1083                     HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1084                     gen_window_check2(dc, RRR_T, RRR_S);
1085                     {
1086                         TCGv_i32 pc = tcg_const_i32(dc->pc);
1087                         gen_advance_ccount(dc);
1088                         gen_helper_movsp(cpu_env, pc);
1089                         tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
1090                         tcg_temp_free(pc);
1091                     }
1092                     break;
1093
1094                 case 2: /*SYNC*/
1095                     switch (RRR_T) {
1096                     case 0: /*ISYNC*/
1097                         break;
1098
1099                     case 1: /*RSYNC*/
1100                         break;
1101
1102                     case 2: /*ESYNC*/
1103                         break;
1104
1105                     case 3: /*DSYNC*/
1106                         break;
1107
1108                     case 8: /*EXCW*/
1109                         HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1110                         break;
1111
1112                     case 12: /*MEMW*/
1113                         break;
1114
1115                     case 13: /*EXTW*/
1116                         break;
1117
1118                     case 15: /*NOP*/
1119                         break;
1120
1121                     default: /*reserved*/
1122                         RESERVED();
1123                         break;
1124                     }
1125                     break;
1126
1127                 case 3: /*RFEIx*/
1128                     switch (RRR_T) {
1129                     case 0: /*RFETx*/
1130                         HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1131                         switch (RRR_S) {
1132                         case 0: /*RFEx*/
1133                             gen_check_privilege(dc);
1134                             tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1135                             gen_helper_check_interrupts(cpu_env);
1136                             gen_jump(dc, cpu_SR[EPC1]);
1137                             break;
1138
1139                         case 1: /*RFUEx*/
1140                             RESERVED();
1141                             break;
1142
1143                         case 2: /*RFDEx*/
1144                             gen_check_privilege(dc);
1145                             gen_jump(dc, cpu_SR[
1146                                     dc->config->ndepc ? DEPC : EPC1]);
1147                             break;
1148
1149                         case 4: /*RFWOw*/
1150                         case 5: /*RFWUw*/
1151                             HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1152                             gen_check_privilege(dc);
1153                             {
1154                                 TCGv_i32 tmp = tcg_const_i32(1);
1155
1156                                 tcg_gen_andi_i32(
1157                                         cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1158                                 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
1159
1160                                 if (RRR_S == 4) {
1161                                     tcg_gen_andc_i32(cpu_SR[WINDOW_START],
1162                                             cpu_SR[WINDOW_START], tmp);
1163                                 } else {
1164                                     tcg_gen_or_i32(cpu_SR[WINDOW_START],
1165                                             cpu_SR[WINDOW_START], tmp);
1166                                 }
1167
1168                                 gen_helper_restore_owb(cpu_env);
1169                                 gen_helper_check_interrupts(cpu_env);
1170                                 gen_jump(dc, cpu_SR[EPC1]);
1171
1172                                 tcg_temp_free(tmp);
1173                             }
1174                             break;
1175
1176                         default: /*reserved*/
1177                             RESERVED();
1178                             break;
1179                         }
1180                         break;
1181
1182                     case 1: /*RFIx*/
1183                         HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
1184                         if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) {
1185                             gen_check_privilege(dc);
1186                             tcg_gen_mov_i32(cpu_SR[PS],
1187                                     cpu_SR[EPS2 + RRR_S - 2]);
1188                             gen_helper_check_interrupts(cpu_env);
1189                             gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
1190                         } else {
1191                             qemu_log("RFI %d is illegal\n", RRR_S);
1192                             gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1193                         }
1194                         break;
1195
1196                     case 2: /*RFME*/
1197                         TBD();
1198                         break;
1199
1200                     default: /*reserved*/
1201                         RESERVED();
1202                         break;
1203
1204                     }
1205                     break;
1206
1207                 case 4: /*BREAKx*/
1208                     HAS_OPTION(XTENSA_OPTION_DEBUG);
1209                     if (dc->debug) {
1210                         gen_debug_exception(dc, DEBUGCAUSE_BI);
1211                     }
1212                     break;
1213
1214                 case 5: /*SYSCALLx*/
1215                     HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1216                     switch (RRR_S) {
1217                     case 0: /*SYSCALLx*/
1218                         gen_exception_cause(dc, SYSCALL_CAUSE);
1219                         break;
1220
1221                     case 1: /*SIMCALL*/
1222                         if (semihosting_enabled) {
1223                             gen_check_privilege(dc);
1224                             gen_helper_simcall(cpu_env);
1225                         } else {
1226                             qemu_log("SIMCALL but semihosting is disabled\n");
1227                             gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1228                         }
1229                         break;
1230
1231                     default:
1232                         RESERVED();
1233                         break;
1234                     }
1235                     break;
1236
1237                 case 6: /*RSILx*/
1238                     HAS_OPTION(XTENSA_OPTION_INTERRUPT);
1239                     gen_check_privilege(dc);
1240                     gen_window_check1(dc, RRR_T);
1241                     tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
1242                     tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
1243                     tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
1244                     gen_helper_check_interrupts(cpu_env);
1245                     gen_jumpi_check_loop_end(dc, 0);
1246                     break;
1247
1248                 case 7: /*WAITIx*/
1249                     HAS_OPTION(XTENSA_OPTION_INTERRUPT);
1250                     gen_check_privilege(dc);
1251                     gen_waiti(dc, RRR_S);
1252                     break;
1253
1254                 case 8: /*ANY4p*/
1255                 case 9: /*ALL4p*/
1256                 case 10: /*ANY8p*/
1257                 case 11: /*ALL8p*/
1258                     HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1259                     {
1260                         const unsigned shift = (RRR_R & 2) ? 8 : 4;
1261                         TCGv_i32 mask = tcg_const_i32(
1262                                 ((1 << shift) - 1) << RRR_S);
1263                         TCGv_i32 tmp = tcg_temp_new_i32();
1264
1265                         tcg_gen_and_i32(tmp, cpu_SR[BR], mask);
1266                         if (RRR_R & 1) { /*ALL*/
1267                             tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S);
1268                         } else { /*ANY*/
1269                             tcg_gen_add_i32(tmp, tmp, mask);
1270                         }
1271                         tcg_gen_shri_i32(tmp, tmp, RRR_S + shift);
1272                         tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR],
1273                                 tmp, RRR_T, 1);
1274                         tcg_temp_free(mask);
1275                         tcg_temp_free(tmp);
1276                     }
1277                     break;
1278
1279                 default: /*reserved*/
1280                     RESERVED();
1281                     break;
1282
1283                 }
1284                 break;
1285
1286             case 1: /*AND*/
1287                 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1288                 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1289                 break;
1290
1291             case 2: /*OR*/
1292                 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1293                 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1294                 break;
1295
1296             case 3: /*XOR*/
1297                 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1298                 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1299                 break;
1300
1301             case 4: /*ST1*/
1302                 switch (RRR_R) {
1303                 case 0: /*SSR*/
1304                     gen_window_check1(dc, RRR_S);
1305                     gen_right_shift_sar(dc, cpu_R[RRR_S]);
1306                     break;
1307
1308                 case 1: /*SSL*/
1309                     gen_window_check1(dc, RRR_S);
1310                     gen_left_shift_sar(dc, cpu_R[RRR_S]);
1311                     break;
1312
1313                 case 2: /*SSA8L*/
1314                     gen_window_check1(dc, RRR_S);
1315                     {
1316                         TCGv_i32 tmp = tcg_temp_new_i32();
1317                         tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1318                         gen_right_shift_sar(dc, tmp);
1319                         tcg_temp_free(tmp);
1320                     }
1321                     break;
1322
1323                 case 3: /*SSA8B*/
1324                     gen_window_check1(dc, RRR_S);
1325                     {
1326                         TCGv_i32 tmp = tcg_temp_new_i32();
1327                         tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1328                         gen_left_shift_sar(dc, tmp);
1329                         tcg_temp_free(tmp);
1330                     }
1331                     break;
1332
1333                 case 4: /*SSAI*/
1334                     {
1335                         TCGv_i32 tmp = tcg_const_i32(
1336                                 RRR_S | ((RRR_T & 1) << 4));
1337                         gen_right_shift_sar(dc, tmp);
1338                         tcg_temp_free(tmp);
1339                     }
1340                     break;
1341
1342                 case 6: /*RER*/
1343                     TBD();
1344                     break;
1345
1346                 case 7: /*WER*/
1347                     TBD();
1348                     break;
1349
1350                 case 8: /*ROTWw*/
1351                     HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1352                     gen_check_privilege(dc);
1353                     {
1354                         TCGv_i32 tmp = tcg_const_i32(
1355                                 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
1356                         gen_helper_rotw(cpu_env, tmp);
1357                         tcg_temp_free(tmp);
1358                         reset_used_window(dc);
1359                     }
1360                     break;
1361
1362                 case 14: /*NSAu*/
1363                     HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
1364                     gen_window_check2(dc, RRR_S, RRR_T);
1365                     gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
1366                     break;
1367
1368                 case 15: /*NSAUu*/
1369                     HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
1370                     gen_window_check2(dc, RRR_S, RRR_T);
1371                     gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
1372                     break;
1373
1374                 default: /*reserved*/
1375                     RESERVED();
1376                     break;
1377                 }
1378                 break;
1379
1380             case 5: /*TLB*/
1381                 HAS_OPTION_BITS(
1382                         XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
1383                         XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
1384                         XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION));
1385                 gen_check_privilege(dc);
1386                 gen_window_check2(dc, RRR_S, RRR_T);
1387                 {
1388                     TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0);
1389
1390                     switch (RRR_R & 7) {
1391                     case 3: /*RITLB0*/ /*RDTLB0*/
1392                         gen_helper_rtlb0(cpu_R[RRR_T],
1393                                 cpu_env, cpu_R[RRR_S], dtlb);
1394                         break;
1395
1396                     case 4: /*IITLB*/ /*IDTLB*/
1397                         gen_helper_itlb(cpu_env, cpu_R[RRR_S], dtlb);
1398                         /* This could change memory mapping, so exit tb */
1399                         gen_jumpi_check_loop_end(dc, -1);
1400                         break;
1401
1402                     case 5: /*PITLB*/ /*PDTLB*/
1403                         tcg_gen_movi_i32(cpu_pc, dc->pc);
1404                         gen_helper_ptlb(cpu_R[RRR_T],
1405                                 cpu_env, cpu_R[RRR_S], dtlb);
1406                         break;
1407
1408                     case 6: /*WITLB*/ /*WDTLB*/
1409                         gen_helper_wtlb(
1410                                 cpu_env, cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1411                         /* This could change memory mapping, so exit tb */
1412                         gen_jumpi_check_loop_end(dc, -1);
1413                         break;
1414
1415                     case 7: /*RITLB1*/ /*RDTLB1*/
1416                         gen_helper_rtlb1(cpu_R[RRR_T],
1417                                 cpu_env, cpu_R[RRR_S], dtlb);
1418                         break;
1419
1420                     default:
1421                         tcg_temp_free(dtlb);
1422                         RESERVED();
1423                         break;
1424                     }
1425                     tcg_temp_free(dtlb);
1426                 }
1427                 break;
1428
1429             case 6: /*RT0*/
1430                 gen_window_check2(dc, RRR_R, RRR_T);
1431                 switch (RRR_S) {
1432                 case 0: /*NEG*/
1433                     tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1434                     break;
1435
1436                 case 1: /*ABS*/
1437                     {
1438                         TCGv_i32 zero = tcg_const_i32(0);
1439                         TCGv_i32 neg = tcg_temp_new_i32();
1440
1441                         tcg_gen_neg_i32(neg, cpu_R[RRR_T]);
1442                         tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[RRR_R],
1443                                 cpu_R[RRR_T], zero, cpu_R[RRR_T], neg);
1444                         tcg_temp_free(neg);
1445                         tcg_temp_free(zero);
1446                     }
1447                     break;
1448
1449                 default: /*reserved*/
1450                     RESERVED();
1451                     break;
1452                 }
1453                 break;
1454
1455             case 7: /*reserved*/
1456                 RESERVED();
1457                 break;
1458
1459             case 8: /*ADD*/
1460                 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1461                 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1462                 break;
1463
1464             case 9: /*ADD**/
1465             case 10:
1466             case 11:
1467                 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1468                 {
1469                     TCGv_i32 tmp = tcg_temp_new_i32();
1470                     tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
1471                     tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1472                     tcg_temp_free(tmp);
1473                 }
1474                 break;
1475
1476             case 12: /*SUB*/
1477                 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1478                 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1479                 break;
1480
1481             case 13: /*SUB**/
1482             case 14:
1483             case 15:
1484                 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1485                 {
1486                     TCGv_i32 tmp = tcg_temp_new_i32();
1487                     tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
1488                     tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1489                     tcg_temp_free(tmp);
1490                 }
1491                 break;
1492             }
1493             break;
1494
1495         case 1: /*RST1*/
1496             switch (OP2) {
1497             case 0: /*SLLI*/
1498             case 1:
1499                 gen_window_check2(dc, RRR_R, RRR_S);
1500                 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
1501                         32 - (RRR_T | ((OP2 & 1) << 4)));
1502                 break;
1503
1504             case 2: /*SRAI*/
1505             case 3:
1506                 gen_window_check2(dc, RRR_R, RRR_T);
1507                 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
1508                         RRR_S | ((OP2 & 1) << 4));
1509                 break;
1510
1511             case 4: /*SRLI*/
1512                 gen_window_check2(dc, RRR_R, RRR_T);
1513                 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
1514                 break;
1515
1516             case 6: /*XSR*/
1517                 if (gen_check_sr(dc, RSR_SR, SR_X)) {
1518                     TCGv_i32 tmp = tcg_temp_new_i32();
1519
1520                     if (RSR_SR >= 64) {
1521                         gen_check_privilege(dc);
1522                     }
1523                     gen_window_check1(dc, RRR_T);
1524                     tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
1525                     gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1526                     gen_wsr(dc, RSR_SR, tmp);
1527                     tcg_temp_free(tmp);
1528                 }
1529                 break;
1530
1531                 /*
1532                  * Note: 64 bit ops are used here solely because SAR values
1533                  * have range 0..63
1534                  */
1535 #define gen_shift_reg(cmd, reg) do { \
1536                     TCGv_i64 tmp = tcg_temp_new_i64(); \
1537                     tcg_gen_extu_i32_i64(tmp, reg); \
1538                     tcg_gen_##cmd##_i64(v, v, tmp); \
1539                     tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
1540                     tcg_temp_free_i64(v); \
1541                     tcg_temp_free_i64(tmp); \
1542                 } while (0)
1543
1544 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1545
1546             case 8: /*SRC*/
1547                 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1548                 {
1549                     TCGv_i64 v = tcg_temp_new_i64();
1550                     tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
1551                     gen_shift(shr);
1552                 }
1553                 break;
1554
1555             case 9: /*SRL*/
1556                 gen_window_check2(dc, RRR_R, RRR_T);
1557                 if (dc->sar_5bit) {
1558                     tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1559                 } else {
1560                     TCGv_i64 v = tcg_temp_new_i64();
1561                     tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
1562                     gen_shift(shr);
1563                 }
1564                 break;
1565
1566             case 10: /*SLL*/
1567                 gen_window_check2(dc, RRR_R, RRR_S);
1568                 if (dc->sar_m32_5bit) {
1569                     tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
1570                 } else {
1571                     TCGv_i64 v = tcg_temp_new_i64();
1572                     TCGv_i32 s = tcg_const_i32(32);
1573                     tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
1574                     tcg_gen_andi_i32(s, s, 0x3f);
1575                     tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
1576                     gen_shift_reg(shl, s);
1577                     tcg_temp_free(s);
1578                 }
1579                 break;
1580
1581             case 11: /*SRA*/
1582                 gen_window_check2(dc, RRR_R, RRR_T);
1583                 if (dc->sar_5bit) {
1584                     tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1585                 } else {
1586                     TCGv_i64 v = tcg_temp_new_i64();
1587                     tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
1588                     gen_shift(sar);
1589                 }
1590                 break;
1591 #undef gen_shift
1592 #undef gen_shift_reg
1593
1594             case 12: /*MUL16U*/
1595                 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1596                 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1597                 {
1598                     TCGv_i32 v1 = tcg_temp_new_i32();
1599                     TCGv_i32 v2 = tcg_temp_new_i32();
1600                     tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
1601                     tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
1602                     tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1603                     tcg_temp_free(v2);
1604                     tcg_temp_free(v1);
1605                 }
1606                 break;
1607
1608             case 13: /*MUL16S*/
1609                 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1610                 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1611                 {
1612                     TCGv_i32 v1 = tcg_temp_new_i32();
1613                     TCGv_i32 v2 = tcg_temp_new_i32();
1614                     tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
1615                     tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
1616                     tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1617                     tcg_temp_free(v2);
1618                     tcg_temp_free(v1);
1619                 }
1620                 break;
1621
1622             default: /*reserved*/
1623                 RESERVED();
1624                 break;
1625             }
1626             break;
1627
1628         case 2: /*RST2*/
1629             if (OP2 >= 8) {
1630                 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1631             }
1632
1633             if (OP2 >= 12) {
1634                 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
1635                 int label = gen_new_label();
1636                 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
1637                 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
1638                 gen_set_label(label);
1639             }
1640
1641             switch (OP2) {
1642 #define BOOLEAN_LOGIC(fn, r, s, t) \
1643                 do { \
1644                     HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1645                     TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1646                     TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1647                     \
1648                     tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1649                     tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1650                     tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1651                     tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1652                     tcg_temp_free(tmp1); \
1653                     tcg_temp_free(tmp2); \
1654                 } while (0)
1655
1656             case 0: /*ANDBp*/
1657                 BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T);
1658                 break;
1659
1660             case 1: /*ANDBCp*/
1661                 BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T);
1662                 break;
1663
1664             case 2: /*ORBp*/
1665                 BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T);
1666                 break;
1667
1668             case 3: /*ORBCp*/
1669                 BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T);
1670                 break;
1671
1672             case 4: /*XORBp*/
1673                 BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T);
1674                 break;
1675
1676 #undef BOOLEAN_LOGIC
1677
1678             case 8: /*MULLi*/
1679                 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1680                 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1681                 break;
1682
1683             case 10: /*MULUHi*/
1684             case 11: /*MULSHi*/
1685                 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH);
1686                 {
1687                     TCGv lo = tcg_temp_new();
1688
1689                     if (OP2 == 10) {
1690                         tcg_gen_mulu2_i32(lo, cpu_R[RRR_R],
1691                                           cpu_R[RRR_S], cpu_R[RRR_T]);
1692                     } else {
1693                         tcg_gen_muls2_i32(lo, cpu_R[RRR_R],
1694                                           cpu_R[RRR_S], cpu_R[RRR_T]);
1695                     }
1696                     tcg_temp_free(lo);
1697                 }
1698                 break;
1699
1700             case 12: /*QUOUi*/
1701                 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1702                 break;
1703
1704             case 13: /*QUOSi*/
1705             case 15: /*REMSi*/
1706                 {
1707                     int label1 = gen_new_label();
1708                     int label2 = gen_new_label();
1709
1710                     tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1711                             label1);
1712                     tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1713                             label1);
1714                     tcg_gen_movi_i32(cpu_R[RRR_R],
1715                             OP2 == 13 ? 0x80000000 : 0);
1716                     tcg_gen_br(label2);
1717                     gen_set_label(label1);
1718                     if (OP2 == 13) {
1719                         tcg_gen_div_i32(cpu_R[RRR_R],
1720                                 cpu_R[RRR_S], cpu_R[RRR_T]);
1721                     } else {
1722                         tcg_gen_rem_i32(cpu_R[RRR_R],
1723                                 cpu_R[RRR_S], cpu_R[RRR_T]);
1724                     }
1725                     gen_set_label(label2);
1726                 }
1727                 break;
1728
1729             case 14: /*REMUi*/
1730                 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1731                 break;
1732
1733             default: /*reserved*/
1734                 RESERVED();
1735                 break;
1736             }
1737             break;
1738
1739         case 3: /*RST3*/
1740             switch (OP2) {
1741             case 0: /*RSR*/
1742                 if (gen_check_sr(dc, RSR_SR, SR_R)) {
1743                     if (RSR_SR >= 64) {
1744                         gen_check_privilege(dc);
1745                     }
1746                     gen_window_check1(dc, RRR_T);
1747                     gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1748                 }
1749                 break;
1750
1751             case 1: /*WSR*/
1752                 if (gen_check_sr(dc, RSR_SR, SR_W)) {
1753                     if (RSR_SR >= 64) {
1754                         gen_check_privilege(dc);
1755                     }
1756                     gen_window_check1(dc, RRR_T);
1757                     gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
1758                 }
1759                 break;
1760
1761             case 2: /*SEXTu*/
1762                 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT);
1763                 gen_window_check2(dc, RRR_R, RRR_S);
1764                 {
1765                     int shift = 24 - RRR_T;
1766
1767                     if (shift == 24) {
1768                         tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1769                     } else if (shift == 16) {
1770                         tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1771                     } else {
1772                         TCGv_i32 tmp = tcg_temp_new_i32();
1773                         tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1774                         tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1775                         tcg_temp_free(tmp);
1776                     }
1777                 }
1778                 break;
1779
1780             case 3: /*CLAMPSu*/
1781                 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS);
1782                 gen_window_check2(dc, RRR_R, RRR_S);
1783                 {
1784                     TCGv_i32 tmp1 = tcg_temp_new_i32();
1785                     TCGv_i32 tmp2 = tcg_temp_new_i32();
1786                     TCGv_i32 zero = tcg_const_i32(0);
1787
1788                     tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1789                     tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1790                     tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
1791
1792                     tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
1793                     tcg_gen_xori_i32(tmp1, tmp1, 0xffffffff >> (25 - RRR_T));
1794
1795                     tcg_gen_movcond_i32(TCG_COND_EQ, cpu_R[RRR_R], tmp2, zero,
1796                             cpu_R[RRR_S], tmp1);
1797                     tcg_temp_free(tmp1);
1798                     tcg_temp_free(tmp2);
1799                     tcg_temp_free(zero);
1800                 }
1801                 break;
1802
1803             case 4: /*MINu*/
1804             case 5: /*MAXu*/
1805             case 6: /*MINUu*/
1806             case 7: /*MAXUu*/
1807                 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX);
1808                 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1809                 {
1810                     static const TCGCond cond[] = {
1811                         TCG_COND_LE,
1812                         TCG_COND_GE,
1813                         TCG_COND_LEU,
1814                         TCG_COND_GEU
1815                     };
1816                     tcg_gen_movcond_i32(cond[OP2 - 4], cpu_R[RRR_R],
1817                             cpu_R[RRR_S], cpu_R[RRR_T],
1818                             cpu_R[RRR_S], cpu_R[RRR_T]);
1819                 }
1820                 break;
1821
1822             case 8: /*MOVEQZ*/
1823             case 9: /*MOVNEZ*/
1824             case 10: /*MOVLTZ*/
1825             case 11: /*MOVGEZ*/
1826                 gen_window_check3(dc, RRR_R, RRR_S, RRR_T);
1827                 {
1828                     static const TCGCond cond[] = {
1829                         TCG_COND_EQ,
1830                         TCG_COND_NE,
1831                         TCG_COND_LT,
1832                         TCG_COND_GE,
1833                     };
1834                     TCGv_i32 zero = tcg_const_i32(0);
1835
1836                     tcg_gen_movcond_i32(cond[OP2 - 8], cpu_R[RRR_R],
1837                             cpu_R[RRR_T], zero, cpu_R[RRR_S], cpu_R[RRR_R]);
1838                     tcg_temp_free(zero);
1839                 }
1840                 break;
1841
1842             case 12: /*MOVFp*/
1843             case 13: /*MOVTp*/
1844                 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1845                 gen_window_check2(dc, RRR_R, RRR_S);
1846                 {
1847                     TCGv_i32 zero = tcg_const_i32(0);
1848                     TCGv_i32 tmp = tcg_temp_new_i32();
1849
1850                     tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
1851                     tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ,
1852                             cpu_R[RRR_R], tmp, zero,
1853                             cpu_R[RRR_S], cpu_R[RRR_R]);
1854
1855                     tcg_temp_free(tmp);
1856                     tcg_temp_free(zero);
1857                 }
1858                 break;
1859
1860             case 14: /*RUR*/
1861                 gen_window_check1(dc, RRR_R);
1862                 {
1863                     int st = (RRR_S << 4) + RRR_T;
1864                     if (uregnames[st].name) {
1865                         tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1866                     } else {
1867                         qemu_log("RUR %d not implemented, ", st);
1868                         TBD();
1869                     }
1870                 }
1871                 break;
1872
1873             case 15: /*WUR*/
1874                 gen_window_check1(dc, RRR_T);
1875                 if (uregnames[RSR_SR].name) {
1876                     gen_wur(RSR_SR, cpu_R[RRR_T]);
1877                 } else {
1878                     qemu_log("WUR %d not implemented, ", RSR_SR);
1879                     TBD();
1880                 }
1881                 break;
1882
1883             }
1884             break;
1885
1886         case 4: /*EXTUI*/
1887         case 5:
1888             gen_window_check2(dc, RRR_R, RRR_T);
1889             {
1890                 int shiftimm = RRR_S | ((OP1 & 1) << 4);
1891                 int maskimm = (1 << (OP2 + 1)) - 1;
1892
1893                 TCGv_i32 tmp = tcg_temp_new_i32();
1894                 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1895                 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
1896                 tcg_temp_free(tmp);
1897             }
1898             break;
1899
1900         case 6: /*CUST0*/
1901             RESERVED();
1902             break;
1903
1904         case 7: /*CUST1*/
1905             RESERVED();
1906             break;
1907
1908         case 8: /*LSCXp*/
1909             switch (OP2) {
1910             case 0: /*LSXf*/
1911             case 1: /*LSXUf*/
1912             case 4: /*SSXf*/
1913             case 5: /*SSXUf*/
1914                 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1915                 gen_window_check2(dc, RRR_S, RRR_T);
1916                 gen_check_cpenable(dc, 0);
1917                 {
1918                     TCGv_i32 addr = tcg_temp_new_i32();
1919                     tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]);
1920                     gen_load_store_alignment(dc, 2, addr, false);
1921                     if (OP2 & 0x4) {
1922                         tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring);
1923                     } else {
1924                         tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring);
1925                     }
1926                     if (OP2 & 0x1) {
1927                         tcg_gen_mov_i32(cpu_R[RRR_S], addr);
1928                     }
1929                     tcg_temp_free(addr);
1930                 }
1931                 break;
1932
1933             default: /*reserved*/
1934                 RESERVED();
1935                 break;
1936             }
1937             break;
1938
1939         case 9: /*LSC4*/
1940             gen_window_check2(dc, RRR_S, RRR_T);
1941             switch (OP2) {
1942             case 0: /*L32E*/
1943                 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1944                 gen_check_privilege(dc);
1945                 {
1946                     TCGv_i32 addr = tcg_temp_new_i32();
1947                     tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1948                             (0xffffffc0 | (RRR_R << 2)));
1949                     tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
1950                     tcg_temp_free(addr);
1951                 }
1952                 break;
1953
1954             case 4: /*S32E*/
1955                 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1956                 gen_check_privilege(dc);
1957                 {
1958                     TCGv_i32 addr = tcg_temp_new_i32();
1959                     tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1960                             (0xffffffc0 | (RRR_R << 2)));
1961                     tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
1962                     tcg_temp_free(addr);
1963                 }
1964                 break;
1965
1966             default:
1967                 RESERVED();
1968                 break;
1969             }
1970             break;
1971
1972         case 10: /*FP0*/
1973             HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1974             switch (OP2) {
1975             case 0: /*ADD.Sf*/
1976                 gen_check_cpenable(dc, 0);
1977                 gen_helper_add_s(cpu_FR[RRR_R], cpu_env,
1978                         cpu_FR[RRR_S], cpu_FR[RRR_T]);
1979                 break;
1980
1981             case 1: /*SUB.Sf*/
1982                 gen_check_cpenable(dc, 0);
1983                 gen_helper_sub_s(cpu_FR[RRR_R], cpu_env,
1984                         cpu_FR[RRR_S], cpu_FR[RRR_T]);
1985                 break;
1986
1987             case 2: /*MUL.Sf*/
1988                 gen_check_cpenable(dc, 0);
1989                 gen_helper_mul_s(cpu_FR[RRR_R], cpu_env,
1990                         cpu_FR[RRR_S], cpu_FR[RRR_T]);
1991                 break;
1992
1993             case 4: /*MADD.Sf*/
1994                 gen_check_cpenable(dc, 0);
1995                 gen_helper_madd_s(cpu_FR[RRR_R], cpu_env,
1996                         cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]);
1997                 break;
1998
1999             case 5: /*MSUB.Sf*/
2000                 gen_check_cpenable(dc, 0);
2001                 gen_helper_msub_s(cpu_FR[RRR_R], cpu_env,
2002                         cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]);
2003                 break;
2004
2005             case 8: /*ROUND.Sf*/
2006             case 9: /*TRUNC.Sf*/
2007             case 10: /*FLOOR.Sf*/
2008             case 11: /*CEIL.Sf*/
2009             case 14: /*UTRUNC.Sf*/
2010                 gen_window_check1(dc, RRR_R);
2011                 gen_check_cpenable(dc, 0);
2012                 {
2013                     static const unsigned rounding_mode_const[] = {
2014                         float_round_nearest_even,
2015                         float_round_to_zero,
2016                         float_round_down,
2017                         float_round_up,
2018                         [6] = float_round_to_zero,
2019                     };
2020                     TCGv_i32 rounding_mode = tcg_const_i32(
2021                             rounding_mode_const[OP2 & 7]);
2022                     TCGv_i32 scale = tcg_const_i32(RRR_T);
2023
2024                     if (OP2 == 14) {
2025                         gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S],
2026                                 rounding_mode, scale);
2027                     } else {
2028                         gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S],
2029                                 rounding_mode, scale);
2030                     }
2031
2032                     tcg_temp_free(rounding_mode);
2033                     tcg_temp_free(scale);
2034                 }
2035                 break;
2036
2037             case 12: /*FLOAT.Sf*/
2038             case 13: /*UFLOAT.Sf*/
2039                 gen_window_check1(dc, RRR_S);
2040                 gen_check_cpenable(dc, 0);
2041                 {
2042                     TCGv_i32 scale = tcg_const_i32(-RRR_T);
2043
2044                     if (OP2 == 13) {
2045                         gen_helper_uitof(cpu_FR[RRR_R], cpu_env,
2046                                 cpu_R[RRR_S], scale);
2047                     } else {
2048                         gen_helper_itof(cpu_FR[RRR_R], cpu_env,
2049                                 cpu_R[RRR_S], scale);
2050                     }
2051                     tcg_temp_free(scale);
2052                 }
2053                 break;
2054
2055             case 15: /*FP1OP*/
2056                 switch (RRR_T) {
2057                 case 0: /*MOV.Sf*/
2058                     gen_check_cpenable(dc, 0);
2059                     tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2060                     break;
2061
2062                 case 1: /*ABS.Sf*/
2063                     gen_check_cpenable(dc, 0);
2064                     gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2065                     break;
2066
2067                 case 4: /*RFRf*/
2068                     gen_window_check1(dc, RRR_R);
2069                     gen_check_cpenable(dc, 0);
2070                     tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]);
2071                     break;
2072
2073                 case 5: /*WFRf*/
2074                     gen_window_check1(dc, RRR_S);
2075                     gen_check_cpenable(dc, 0);
2076                     tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]);
2077                     break;
2078
2079                 case 6: /*NEG.Sf*/
2080                     gen_check_cpenable(dc, 0);
2081                     gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2082                     break;
2083
2084                 default: /*reserved*/
2085                     RESERVED();
2086                     break;
2087                 }
2088                 break;
2089
2090             default: /*reserved*/
2091                 RESERVED();
2092                 break;
2093             }
2094             break;
2095
2096         case 11: /*FP1*/
2097             HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
2098
2099 #define gen_compare(rel, br, a, b) \
2100     do { \
2101         TCGv_i32 bit = tcg_const_i32(1 << br); \
2102         \
2103         gen_check_cpenable(dc, 0); \
2104         gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \
2105         tcg_temp_free(bit); \
2106     } while (0)
2107
2108             switch (OP2) {
2109             case 1: /*UN.Sf*/
2110                 gen_compare(un_s, RRR_R, RRR_S, RRR_T);
2111                 break;
2112
2113             case 2: /*OEQ.Sf*/
2114                 gen_compare(oeq_s, RRR_R, RRR_S, RRR_T);
2115                 break;
2116
2117             case 3: /*UEQ.Sf*/
2118                 gen_compare(ueq_s, RRR_R, RRR_S, RRR_T);
2119                 break;
2120
2121             case 4: /*OLT.Sf*/
2122                 gen_compare(olt_s, RRR_R, RRR_S, RRR_T);
2123                 break;
2124
2125             case 5: /*ULT.Sf*/
2126                 gen_compare(ult_s, RRR_R, RRR_S, RRR_T);
2127                 break;
2128
2129             case 6: /*OLE.Sf*/
2130                 gen_compare(ole_s, RRR_R, RRR_S, RRR_T);
2131                 break;
2132
2133             case 7: /*ULE.Sf*/
2134                 gen_compare(ule_s, RRR_R, RRR_S, RRR_T);
2135                 break;
2136
2137 #undef gen_compare
2138
2139             case 8: /*MOVEQZ.Sf*/
2140             case 9: /*MOVNEZ.Sf*/
2141             case 10: /*MOVLTZ.Sf*/
2142             case 11: /*MOVGEZ.Sf*/
2143                 gen_window_check1(dc, RRR_T);
2144                 gen_check_cpenable(dc, 0);
2145                 {
2146                     static const TCGCond cond[] = {
2147                         TCG_COND_EQ,
2148                         TCG_COND_NE,
2149                         TCG_COND_LT,
2150                         TCG_COND_GE,
2151                     };
2152                     TCGv_i32 zero = tcg_const_i32(0);
2153
2154                     tcg_gen_movcond_i32(cond[OP2 - 8], cpu_FR[RRR_R],
2155                             cpu_R[RRR_T], zero, cpu_FR[RRR_S], cpu_FR[RRR_R]);
2156                     tcg_temp_free(zero);
2157                 }
2158                 break;
2159
2160             case 12: /*MOVF.Sf*/
2161             case 13: /*MOVT.Sf*/
2162                 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
2163                 gen_check_cpenable(dc, 0);
2164                 {
2165                     TCGv_i32 zero = tcg_const_i32(0);
2166                     TCGv_i32 tmp = tcg_temp_new_i32();
2167
2168                     tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
2169                     tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ,
2170                             cpu_FR[RRR_R], tmp, zero,
2171                             cpu_FR[RRR_S], cpu_FR[RRR_R]);
2172
2173                     tcg_temp_free(tmp);
2174                     tcg_temp_free(zero);
2175                 }
2176                 break;
2177
2178             default: /*reserved*/
2179                 RESERVED();
2180                 break;
2181             }
2182             break;
2183
2184         default: /*reserved*/
2185             RESERVED();
2186             break;
2187         }
2188         break;
2189
2190     case 1: /*L32R*/
2191         gen_window_check1(dc, RRR_T);
2192         {
2193             TCGv_i32 tmp = tcg_const_i32(
2194                     ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
2195                      0 : ((dc->pc + 3) & ~3)) +
2196                     (0xfffc0000 | (RI16_IMM16 << 2)));
2197
2198             if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
2199                 tcg_gen_add_i32(tmp, tmp, dc->litbase);
2200             }
2201             tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
2202             tcg_temp_free(tmp);
2203         }
2204         break;
2205
2206     case 2: /*LSAI*/
2207 #define gen_load_store(type, shift) do { \
2208             TCGv_i32 addr = tcg_temp_new_i32(); \
2209             gen_window_check2(dc, RRI8_S, RRI8_T); \
2210             tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
2211             if (shift) { \
2212                 gen_load_store_alignment(dc, shift, addr, false); \
2213             } \
2214             tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2215             tcg_temp_free(addr); \
2216         } while (0)
2217
2218         switch (RRI8_R) {
2219         case 0: /*L8UI*/
2220             gen_load_store(ld8u, 0);
2221             break;
2222
2223         case 1: /*L16UI*/
2224             gen_load_store(ld16u, 1);
2225             break;
2226
2227         case 2: /*L32I*/
2228             gen_load_store(ld32u, 2);
2229             break;
2230
2231         case 4: /*S8I*/
2232             gen_load_store(st8, 0);
2233             break;
2234
2235         case 5: /*S16I*/
2236             gen_load_store(st16, 1);
2237             break;
2238
2239         case 6: /*S32I*/
2240             gen_load_store(st32, 2);
2241             break;
2242
2243 #define gen_dcache_hit_test(w, shift) do { \
2244             TCGv_i32 addr = tcg_temp_new_i32(); \
2245             TCGv_i32 res = tcg_temp_new_i32(); \
2246             gen_window_check1(dc, RRI##w##_S); \
2247             tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2248                              RRI##w##_IMM##w << shift); \
2249             tcg_gen_qemu_ld8u(res, addr, dc->cring); \
2250             tcg_temp_free(addr); \
2251             tcg_temp_free(res); \
2252         } while (0)
2253
2254 #define gen_dcache_hit_test4() gen_dcache_hit_test(4, 4)
2255 #define gen_dcache_hit_test8() gen_dcache_hit_test(8, 2)
2256
2257         case 7: /*CACHEc*/
2258             if (RRI8_T < 8) {
2259                 HAS_OPTION(XTENSA_OPTION_DCACHE);
2260             }
2261
2262             switch (RRI8_T) {
2263             case 0: /*DPFRc*/
2264                 gen_window_check1(dc, RRI8_S);
2265                 break;
2266
2267             case 1: /*DPFWc*/
2268                 gen_window_check1(dc, RRI8_S);
2269                 break;
2270
2271             case 2: /*DPFROc*/
2272                 gen_window_check1(dc, RRI8_S);
2273                 break;
2274
2275             case 3: /*DPFWOc*/
2276                 gen_window_check1(dc, RRI8_S);
2277                 break;
2278
2279             case 4: /*DHWBc*/
2280                 gen_dcache_hit_test8();
2281                 break;
2282
2283             case 5: /*DHWBIc*/
2284                 gen_dcache_hit_test8();
2285                 break;
2286
2287             case 6: /*DHIc*/
2288                 gen_check_privilege(dc);
2289                 gen_dcache_hit_test8();
2290                 break;
2291
2292             case 7: /*DIIc*/
2293                 gen_check_privilege(dc);
2294                 gen_window_check1(dc, RRI8_S);
2295                 break;
2296
2297             case 8: /*DCEc*/
2298                 switch (OP1) {
2299                 case 0: /*DPFLl*/
2300                     HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2301                     gen_check_privilege(dc);
2302                     gen_dcache_hit_test4();
2303                     break;
2304
2305                 case 2: /*DHUl*/
2306                     HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2307                     gen_check_privilege(dc);
2308                     gen_dcache_hit_test4();
2309                     break;
2310
2311                 case 3: /*DIUl*/
2312                     HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2313                     gen_check_privilege(dc);
2314                     gen_window_check1(dc, RRI4_S);
2315                     break;
2316
2317                 case 4: /*DIWBc*/
2318                     HAS_OPTION(XTENSA_OPTION_DCACHE);
2319                     gen_check_privilege(dc);
2320                     gen_window_check1(dc, RRI4_S);
2321                     break;
2322
2323                 case 5: /*DIWBIc*/
2324                     HAS_OPTION(XTENSA_OPTION_DCACHE);
2325                     gen_check_privilege(dc);
2326                     gen_window_check1(dc, RRI4_S);
2327                     break;
2328
2329                 default: /*reserved*/
2330                     RESERVED();
2331                     break;
2332
2333                 }
2334                 break;
2335
2336 #undef gen_dcache_hit_test
2337 #undef gen_dcache_hit_test4
2338 #undef gen_dcache_hit_test8
2339
2340 #define gen_icache_hit_test(w, shift) do { \
2341             TCGv_i32 addr = tcg_temp_new_i32(); \
2342             gen_window_check1(dc, RRI##w##_S); \
2343             tcg_gen_movi_i32(cpu_pc, dc->pc); \
2344             tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2345                              RRI##w##_IMM##w << shift); \
2346             gen_helper_itlb_hit_test(cpu_env, addr); \
2347             tcg_temp_free(addr); \
2348         } while (0)
2349
2350 #define gen_icache_hit_test4() gen_icache_hit_test(4, 4)
2351 #define gen_icache_hit_test8() gen_icache_hit_test(8, 2)
2352
2353             case 12: /*IPFc*/
2354                 HAS_OPTION(XTENSA_OPTION_ICACHE);
2355                 gen_window_check1(dc, RRI8_S);
2356                 break;
2357
2358             case 13: /*ICEc*/
2359                 switch (OP1) {
2360                 case 0: /*IPFLl*/
2361                     HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2362                     gen_check_privilege(dc);
2363                     gen_icache_hit_test4();
2364                     break;
2365
2366                 case 2: /*IHUl*/
2367                     HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2368                     gen_check_privilege(dc);
2369                     gen_icache_hit_test4();
2370                     break;
2371
2372                 case 3: /*IIUl*/
2373                     HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2374                     gen_check_privilege(dc);
2375                     gen_window_check1(dc, RRI4_S);
2376                     break;
2377
2378                 default: /*reserved*/
2379                     RESERVED();
2380                     break;
2381                 }
2382                 break;
2383
2384             case 14: /*IHIc*/
2385                 HAS_OPTION(XTENSA_OPTION_ICACHE);
2386                 gen_icache_hit_test8();
2387                 break;
2388
2389             case 15: /*IIIc*/
2390                 HAS_OPTION(XTENSA_OPTION_ICACHE);
2391                 gen_check_privilege(dc);
2392                 gen_window_check1(dc, RRI8_S);
2393                 break;
2394
2395             default: /*reserved*/
2396                 RESERVED();
2397                 break;
2398             }
2399             break;
2400
2401 #undef gen_icache_hit_test
2402 #undef gen_icache_hit_test4
2403 #undef gen_icache_hit_test8
2404
2405         case 9: /*L16SI*/
2406             gen_load_store(ld16s, 1);
2407             break;
2408 #undef gen_load_store
2409
2410         case 10: /*MOVI*/
2411             gen_window_check1(dc, RRI8_T);
2412             tcg_gen_movi_i32(cpu_R[RRI8_T],
2413                     RRI8_IMM8 | (RRI8_S << 8) |
2414                     ((RRI8_S & 0x8) ? 0xfffff000 : 0));
2415             break;
2416
2417 #define gen_load_store_no_hw_align(type) do { \
2418             TCGv_i32 addr = tcg_temp_local_new_i32(); \
2419             gen_window_check2(dc, RRI8_S, RRI8_T); \
2420             tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2421             gen_load_store_alignment(dc, 2, addr, true); \
2422             tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2423             tcg_temp_free(addr); \
2424         } while (0)
2425
2426         case 11: /*L32AIy*/
2427             HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
2428             gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/
2429             break;
2430
2431         case 12: /*ADDI*/
2432             gen_window_check2(dc, RRI8_S, RRI8_T);
2433             tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
2434             break;
2435
2436         case 13: /*ADDMI*/
2437             gen_window_check2(dc, RRI8_S, RRI8_T);
2438             tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE << 8);
2439             break;
2440
2441         case 14: /*S32C1Iy*/
2442             HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE);
2443             gen_window_check2(dc, RRI8_S, RRI8_T);
2444             {
2445                 int label = gen_new_label();
2446                 TCGv_i32 tmp = tcg_temp_local_new_i32();
2447                 TCGv_i32 addr = tcg_temp_local_new_i32();
2448                 TCGv_i32 tpc;
2449
2450                 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
2451                 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2452                 gen_load_store_alignment(dc, 2, addr, true);
2453
2454                 gen_advance_ccount(dc);
2455                 tpc = tcg_const_i32(dc->pc);
2456                 gen_helper_check_atomctl(cpu_env, tpc, addr);
2457                 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
2458                 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
2459                         cpu_SR[SCOMPARE1], label);
2460
2461                 tcg_gen_qemu_st32(tmp, addr, dc->cring);
2462
2463                 gen_set_label(label);
2464                 tcg_temp_free(tpc);
2465                 tcg_temp_free(addr);
2466                 tcg_temp_free(tmp);
2467             }
2468             break;
2469
2470         case 15: /*S32RIy*/
2471             HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
2472             gen_load_store_no_hw_align(st32); /*TODO release?*/
2473             break;
2474 #undef gen_load_store_no_hw_align
2475
2476         default: /*reserved*/
2477             RESERVED();
2478             break;
2479         }
2480         break;
2481
2482     case 3: /*LSCIp*/
2483         switch (RRI8_R) {
2484         case 0: /*LSIf*/
2485         case 4: /*SSIf*/
2486         case 8: /*LSIUf*/
2487         case 12: /*SSIUf*/
2488             HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
2489             gen_window_check1(dc, RRI8_S);
2490             gen_check_cpenable(dc, 0);
2491             {
2492                 TCGv_i32 addr = tcg_temp_new_i32();
2493                 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2494                 gen_load_store_alignment(dc, 2, addr, false);
2495                 if (RRI8_R & 0x4) {
2496                     tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring);
2497                 } else {
2498                     tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring);
2499                 }
2500                 if (RRI8_R & 0x8) {
2501                     tcg_gen_mov_i32(cpu_R[RRI8_S], addr);
2502                 }
2503                 tcg_temp_free(addr);
2504             }
2505             break;
2506
2507         default: /*reserved*/
2508             RESERVED();
2509             break;
2510         }
2511         break;
2512
2513     case 4: /*MAC16d*/
2514         HAS_OPTION(XTENSA_OPTION_MAC16);
2515         {
2516             enum {
2517                 MAC16_UMUL = 0x0,
2518                 MAC16_MUL  = 0x4,
2519                 MAC16_MULA = 0x8,
2520                 MAC16_MULS = 0xc,
2521                 MAC16_NONE = 0xf,
2522             } op = OP1 & 0xc;
2523             bool is_m1_sr = (OP2 & 0x3) == 2;
2524             bool is_m2_sr = (OP2 & 0xc) == 0;
2525             uint32_t ld_offset = 0;
2526
2527             if (OP2 > 9) {
2528                 RESERVED();
2529             }
2530
2531             switch (OP2 & 2) {
2532             case 0: /*MACI?/MACC?*/
2533                 is_m1_sr = true;
2534                 ld_offset = (OP2 & 1) ? -4 : 4;
2535
2536                 if (OP2 >= 8) { /*MACI/MACC*/
2537                     if (OP1 == 0) { /*LDINC/LDDEC*/
2538                         op = MAC16_NONE;
2539                     } else {
2540                         RESERVED();
2541                     }
2542                 } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/
2543                     RESERVED();
2544                 }
2545                 break;
2546
2547             case 2: /*MACD?/MACA?*/
2548                 if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/
2549                     RESERVED();
2550                 }
2551                 break;
2552             }
2553
2554             if (op != MAC16_NONE) {
2555                 if (!is_m1_sr) {
2556                     gen_window_check1(dc, RRR_S);
2557                 }
2558                 if (!is_m2_sr) {
2559                     gen_window_check1(dc, RRR_T);
2560                 }
2561             }
2562
2563             {
2564                 TCGv_i32 vaddr = tcg_temp_new_i32();
2565                 TCGv_i32 mem32 = tcg_temp_new_i32();
2566
2567                 if (ld_offset) {
2568                     gen_window_check1(dc, RRR_S);
2569                     tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset);
2570                     gen_load_store_alignment(dc, 2, vaddr, false);
2571                     tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
2572                 }
2573                 if (op != MAC16_NONE) {
2574                     TCGv_i32 m1 = gen_mac16_m(
2575                             is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S],
2576                             OP1 & 1, op == MAC16_UMUL);
2577                     TCGv_i32 m2 = gen_mac16_m(
2578                             is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T],
2579                             OP1 & 2, op == MAC16_UMUL);
2580
2581                     if (op == MAC16_MUL || op == MAC16_UMUL) {
2582                         tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
2583                         if (op == MAC16_UMUL) {
2584                             tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
2585                         } else {
2586                             tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
2587                         }
2588                     } else {
2589                         TCGv_i32 lo = tcg_temp_new_i32();
2590                         TCGv_i32 hi = tcg_temp_new_i32();
2591
2592                         tcg_gen_mul_i32(lo, m1, m2);
2593                         tcg_gen_sari_i32(hi, lo, 31);
2594                         if (op == MAC16_MULA) {
2595                             tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
2596                                              cpu_SR[ACCLO], cpu_SR[ACCHI],
2597                                              lo, hi);
2598                         } else {
2599                             tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
2600                                              cpu_SR[ACCLO], cpu_SR[ACCHI],
2601                                              lo, hi);
2602                         }
2603                         tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
2604
2605                         tcg_temp_free_i32(lo);
2606                         tcg_temp_free_i32(hi);
2607                     }
2608                     tcg_temp_free(m1);
2609                     tcg_temp_free(m2);
2610                 }
2611                 if (ld_offset) {
2612                     tcg_gen_mov_i32(cpu_R[RRR_S], vaddr);
2613                     tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32);
2614                 }
2615                 tcg_temp_free(vaddr);
2616                 tcg_temp_free(mem32);
2617             }
2618         }
2619         break;
2620
2621     case 5: /*CALLN*/
2622         switch (CALL_N) {
2623         case 0: /*CALL0*/
2624             tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
2625             gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2626             break;
2627
2628         case 1: /*CALL4w*/
2629         case 2: /*CALL8w*/
2630         case 3: /*CALL12w*/
2631             HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2632             gen_window_check1(dc, CALL_N << 2);
2633             gen_callwi(dc, CALL_N,
2634                     (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2635             break;
2636         }
2637         break;
2638
2639     case 6: /*SI*/
2640         switch (CALL_N) {
2641         case 0: /*J*/
2642             gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
2643             break;
2644
2645         case 1: /*BZ*/
2646             gen_window_check1(dc, BRI12_S);
2647             {
2648                 static const TCGCond cond[] = {
2649                     TCG_COND_EQ, /*BEQZ*/
2650                     TCG_COND_NE, /*BNEZ*/
2651                     TCG_COND_LT, /*BLTZ*/
2652                     TCG_COND_GE, /*BGEZ*/
2653                 };
2654
2655                 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
2656                         4 + BRI12_IMM12_SE);
2657             }
2658             break;
2659
2660         case 2: /*BI0*/
2661             gen_window_check1(dc, BRI8_S);
2662             {
2663                 static const TCGCond cond[] = {
2664                     TCG_COND_EQ, /*BEQI*/
2665                     TCG_COND_NE, /*BNEI*/
2666                     TCG_COND_LT, /*BLTI*/
2667                     TCG_COND_GE, /*BGEI*/
2668                 };
2669
2670                 gen_brcondi(dc, cond[BRI8_M & 3],
2671                         cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
2672             }
2673             break;
2674
2675         case 3: /*BI1*/
2676             switch (BRI8_M) {
2677             case 0: /*ENTRYw*/
2678                 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2679                 {
2680                     TCGv_i32 pc = tcg_const_i32(dc->pc);
2681                     TCGv_i32 s = tcg_const_i32(BRI12_S);
2682                     TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
2683                     gen_advance_ccount(dc);
2684                     gen_helper_entry(cpu_env, pc, s, imm);
2685                     tcg_temp_free(imm);
2686                     tcg_temp_free(s);
2687                     tcg_temp_free(pc);
2688                     reset_used_window(dc);
2689                 }
2690                 break;
2691
2692             case 1: /*B1*/
2693                 switch (BRI8_R) {
2694                 case 0: /*BFp*/
2695                 case 1: /*BTp*/
2696                     HAS_OPTION(XTENSA_OPTION_BOOLEAN);
2697                     {
2698                         TCGv_i32 tmp = tcg_temp_new_i32();
2699                         tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S);
2700                         gen_brcondi(dc,
2701                                 BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ,
2702                                 tmp, 0, 4 + RRI8_IMM8_SE);
2703                         tcg_temp_free(tmp);
2704                     }
2705                     break;
2706
2707                 case 8: /*LOOP*/
2708                 case 9: /*LOOPNEZ*/
2709                 case 10: /*LOOPGTZ*/
2710                     HAS_OPTION(XTENSA_OPTION_LOOP);
2711                     gen_window_check1(dc, RRI8_S);
2712                     {
2713                         uint32_t lend = dc->pc + RRI8_IMM8 + 4;
2714                         TCGv_i32 tmp = tcg_const_i32(lend);
2715
2716                         tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
2717                         tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
2718                         gen_helper_wsr_lend(cpu_env, tmp);
2719                         tcg_temp_free(tmp);
2720
2721                         if (BRI8_R > 8) {
2722                             int label = gen_new_label();
2723                             tcg_gen_brcondi_i32(
2724                                     BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
2725                                     cpu_R[RRI8_S], 0, label);
2726                             gen_jumpi(dc, lend, 1);
2727                             gen_set_label(label);
2728                         }
2729
2730                         gen_jumpi(dc, dc->next_pc, 0);
2731                     }
2732                     break;
2733
2734                 default: /*reserved*/
2735                     RESERVED();
2736                     break;
2737
2738                 }
2739                 break;
2740
2741             case 2: /*BLTUI*/
2742             case 3: /*BGEUI*/
2743                 gen_window_check1(dc, BRI8_S);
2744                 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
2745                         cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE);
2746                 break;
2747             }
2748             break;
2749
2750         }
2751         break;
2752
2753     case 7: /*B*/
2754         {
2755             TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
2756
2757             switch (RRI8_R & 7) {
2758             case 0: /*BNONE*/ /*BANY*/
2759                 gen_window_check2(dc, RRI8_S, RRI8_T);
2760                 {
2761                     TCGv_i32 tmp = tcg_temp_new_i32();
2762                     tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2763                     gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2764                     tcg_temp_free(tmp);
2765                 }
2766                 break;
2767
2768             case 1: /*BEQ*/ /*BNE*/
2769             case 2: /*BLT*/ /*BGE*/
2770             case 3: /*BLTU*/ /*BGEU*/
2771                 gen_window_check2(dc, RRI8_S, RRI8_T);
2772                 {
2773                     static const TCGCond cond[] = {
2774                         [1] = TCG_COND_EQ,
2775                         [2] = TCG_COND_LT,
2776                         [3] = TCG_COND_LTU,
2777                         [9] = TCG_COND_NE,
2778                         [10] = TCG_COND_GE,
2779                         [11] = TCG_COND_GEU,
2780                     };
2781                     gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
2782                             4 + RRI8_IMM8_SE);
2783                 }
2784                 break;
2785
2786             case 4: /*BALL*/ /*BNALL*/
2787                 gen_window_check2(dc, RRI8_S, RRI8_T);
2788                 {
2789                     TCGv_i32 tmp = tcg_temp_new_i32();
2790                     tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2791                     gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
2792                             4 + RRI8_IMM8_SE);
2793                     tcg_temp_free(tmp);
2794                 }
2795                 break;
2796
2797             case 5: /*BBC*/ /*BBS*/
2798                 gen_window_check2(dc, RRI8_S, RRI8_T);
2799                 {
2800 #ifdef TARGET_WORDS_BIGENDIAN
2801                     TCGv_i32 bit = tcg_const_i32(0x80000000);
2802 #else
2803                     TCGv_i32 bit = tcg_const_i32(0x00000001);
2804 #endif
2805                     TCGv_i32 tmp = tcg_temp_new_i32();
2806                     tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
2807 #ifdef TARGET_WORDS_BIGENDIAN
2808                     tcg_gen_shr_i32(bit, bit, tmp);
2809 #else
2810                     tcg_gen_shl_i32(bit, bit, tmp);
2811 #endif
2812                     tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
2813                     gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2814                     tcg_temp_free(tmp);
2815                     tcg_temp_free(bit);
2816                 }
2817                 break;
2818
2819             case 6: /*BBCI*/ /*BBSI*/
2820             case 7:
2821                 gen_window_check1(dc, RRI8_S);
2822                 {
2823                     TCGv_i32 tmp = tcg_temp_new_i32();
2824                     tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
2825 #ifdef TARGET_WORDS_BIGENDIAN
2826                             0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T));
2827 #else
2828                             0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T));
2829 #endif
2830                     gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2831                     tcg_temp_free(tmp);
2832                 }
2833                 break;
2834
2835             }
2836         }
2837         break;
2838
2839 #define gen_narrow_load_store(type) do { \
2840             TCGv_i32 addr = tcg_temp_new_i32(); \
2841             gen_window_check2(dc, RRRN_S, RRRN_T); \
2842             tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2843             gen_load_store_alignment(dc, 2, addr, false); \
2844             tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2845             tcg_temp_free(addr); \
2846         } while (0)
2847
2848     case 8: /*L32I.Nn*/
2849         gen_narrow_load_store(ld32u);
2850         break;
2851
2852     case 9: /*S32I.Nn*/
2853         gen_narrow_load_store(st32);
2854         break;
2855 #undef gen_narrow_load_store
2856
2857     case 10: /*ADD.Nn*/
2858         gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T);
2859         tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
2860         break;
2861
2862     case 11: /*ADDI.Nn*/
2863         gen_window_check2(dc, RRRN_R, RRRN_S);
2864         tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
2865         break;
2866
2867     case 12: /*ST2n*/
2868         gen_window_check1(dc, RRRN_S);
2869         if (RRRN_T < 8) { /*MOVI.Nn*/
2870             tcg_gen_movi_i32(cpu_R[RRRN_S],
2871                     RRRN_R | (RRRN_T << 4) |
2872                     ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
2873         } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
2874             TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
2875
2876             gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
2877                     4 + (RRRN_R | ((RRRN_T & 3) << 4)));
2878         }
2879         break;
2880
2881     case 13: /*ST3n*/
2882         switch (RRRN_R) {
2883         case 0: /*MOV.Nn*/
2884             gen_window_check2(dc, RRRN_S, RRRN_T);
2885             tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
2886             break;
2887
2888         case 15: /*S3*/
2889             switch (RRRN_T) {
2890             case 0: /*RET.Nn*/
2891                 gen_jump(dc, cpu_R[0]);
2892                 break;
2893
2894             case 1: /*RETW.Nn*/
2895                 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2896                 {
2897                     TCGv_i32 tmp = tcg_const_i32(dc->pc);
2898                     gen_advance_ccount(dc);
2899                     gen_helper_retw(tmp, cpu_env, tmp);
2900                     gen_jump(dc, tmp);
2901                     tcg_temp_free(tmp);
2902                 }
2903                 break;
2904
2905             case 2: /*BREAK.Nn*/
2906                 HAS_OPTION(XTENSA_OPTION_DEBUG);
2907                 if (dc->debug) {
2908                     gen_debug_exception(dc, DEBUGCAUSE_BN);
2909                 }
2910                 break;
2911
2912             case 3: /*NOP.Nn*/
2913                 break;
2914
2915             case 6: /*ILL.Nn*/
2916                 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
2917                 break;
2918
2919             default: /*reserved*/
2920                 RESERVED();
2921                 break;
2922             }
2923             break;
2924
2925         default: /*reserved*/
2926             RESERVED();
2927             break;
2928         }
2929         break;
2930
2931     default: /*reserved*/
2932         RESERVED();
2933         break;
2934     }
2935
2936     if (dc->is_jmp == DISAS_NEXT) {
2937         gen_check_loop_end(dc, 0);
2938     }
2939     dc->pc = dc->next_pc;
2940
2941     return;
2942
2943 invalid_opcode:
2944     qemu_log("INVALID(pc = %08x)\n", dc->pc);
2945     gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
2946 #undef HAS_OPTION
2947 }
2948
2949 static void check_breakpoint(CPUXtensaState *env, DisasContext *dc)
2950 {
2951     CPUBreakpoint *bp;
2952
2953     if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
2954         QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
2955             if (bp->pc == dc->pc) {
2956                 tcg_gen_movi_i32(cpu_pc, dc->pc);
2957                 gen_exception(dc, EXCP_DEBUG);
2958                 dc->is_jmp = DISAS_UPDATE;
2959              }
2960         }
2961     }
2962 }
2963
2964 static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
2965 {
2966     unsigned i;
2967
2968     for (i = 0; i < dc->config->nibreak; ++i) {
2969         if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
2970                 env->sregs[IBREAKA + i] == dc->pc) {
2971             gen_debug_exception(dc, DEBUGCAUSE_IB);
2972             break;
2973         }
2974     }
2975 }
2976
2977 static inline
2978 void gen_intermediate_code_internal(XtensaCPU *cpu,
2979                                     TranslationBlock *tb, bool search_pc)
2980 {
2981     CPUState *cs = CPU(cpu);
2982     CPUXtensaState *env = &cpu->env;
2983     DisasContext dc;
2984     int insn_count = 0;
2985     int j, lj = -1;
2986     uint16_t *gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
2987     int max_insns = tb->cflags & CF_COUNT_MASK;
2988     uint32_t pc_start = tb->pc;
2989     uint32_t next_page_start =
2990         (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2991
2992     if (max_insns == 0) {
2993         max_insns = CF_COUNT_MASK;
2994     }
2995
2996     dc.config = env->config;
2997     dc.singlestep_enabled = cs->singlestep_enabled;
2998     dc.tb = tb;
2999     dc.pc = pc_start;
3000     dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
3001     dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
3002     dc.lbeg = env->sregs[LBEG];
3003     dc.lend = env->sregs[LEND];
3004     dc.is_jmp = DISAS_NEXT;
3005     dc.ccount_delta = 0;
3006     dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG;
3007     dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT;
3008     dc.cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
3009         XTENSA_TBFLAG_CPENABLE_SHIFT;
3010
3011     init_litbase(&dc);
3012     init_sar_tracker(&dc);
3013     reset_used_window(&dc);
3014     if (dc.icount) {
3015         dc.next_icount = tcg_temp_local_new_i32();
3016     }
3017
3018     gen_tb_start();
3019
3020     if (tb->flags & XTENSA_TBFLAG_EXCEPTION) {
3021         tcg_gen_movi_i32(cpu_pc, dc.pc);
3022         gen_exception(&dc, EXCP_DEBUG);
3023     }
3024
3025     do {
3026         check_breakpoint(env, &dc);
3027
3028         if (search_pc) {
3029             j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
3030             if (lj < j) {
3031                 lj++;
3032                 while (lj < j) {
3033                     tcg_ctx.gen_opc_instr_start[lj++] = 0;
3034                 }
3035             }
3036             tcg_ctx.gen_opc_pc[lj] = dc.pc;
3037             tcg_ctx.gen_opc_instr_start[lj] = 1;
3038             tcg_ctx.gen_opc_icount[lj] = insn_count;
3039         }
3040
3041         if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
3042             tcg_gen_debug_insn_start(dc.pc);
3043         }
3044
3045         ++dc.ccount_delta;
3046
3047         if (insn_count + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
3048             gen_io_start();
3049         }
3050
3051         if (dc.icount) {
3052             int label = gen_new_label();
3053
3054             tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1);
3055             tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label);
3056             tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]);
3057             if (dc.debug) {
3058                 gen_debug_exception(&dc, DEBUGCAUSE_IC);
3059             }
3060             gen_set_label(label);
3061         }
3062
3063         if (dc.debug) {
3064             gen_ibreak_check(env, &dc);
3065         }
3066
3067         disas_xtensa_insn(env, &dc);
3068         ++insn_count;
3069         if (dc.icount) {
3070             tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
3071         }
3072         if (cs->singlestep_enabled) {
3073             tcg_gen_movi_i32(cpu_pc, dc.pc);
3074             gen_exception(&dc, EXCP_DEBUG);
3075             break;
3076         }
3077     } while (dc.is_jmp == DISAS_NEXT &&
3078             insn_count < max_insns &&
3079             dc.pc < next_page_start &&
3080             tcg_ctx.gen_opc_ptr < gen_opc_end);
3081
3082     reset_litbase(&dc);
3083     reset_sar_tracker(&dc);
3084     if (dc.icount) {
3085         tcg_temp_free(dc.next_icount);
3086     }
3087
3088     if (tb->cflags & CF_LAST_IO) {
3089         gen_io_end();
3090     }
3091
3092     if (dc.is_jmp == DISAS_NEXT) {
3093         gen_jumpi(&dc, dc.pc, 0);
3094     }
3095     gen_tb_end(tb, insn_count);
3096     *tcg_ctx.gen_opc_ptr = INDEX_op_end;
3097
3098 #ifdef DEBUG_DISAS
3099     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3100         qemu_log("----------------\n");
3101         qemu_log("IN: %s\n", lookup_symbol(pc_start));
3102         log_target_disas(env, pc_start, dc.pc - pc_start, 0);
3103         qemu_log("\n");
3104     }
3105 #endif
3106     if (search_pc) {
3107         j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
3108         memset(tcg_ctx.gen_opc_instr_start + lj + 1, 0,
3109                 (j - lj) * sizeof(tcg_ctx.gen_opc_instr_start[0]));
3110     } else {
3111         tb->size = dc.pc - pc_start;
3112         tb->icount = insn_count;
3113     }
3114 }
3115
3116 void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
3117 {
3118     gen_intermediate_code_internal(xtensa_env_get_cpu(env), tb, false);
3119 }
3120
3121 void gen_intermediate_code_pc(CPUXtensaState *env, TranslationBlock *tb)
3122 {
3123     gen_intermediate_code_internal(xtensa_env_get_cpu(env), tb, true);
3124 }
3125
3126 void xtensa_cpu_dump_state(CPUState *cs, FILE *f,
3127                            fprintf_function cpu_fprintf, int flags)
3128 {
3129     XtensaCPU *cpu = XTENSA_CPU(cs);
3130     CPUXtensaState *env = &cpu->env;
3131     int i, j;
3132
3133     cpu_fprintf(f, "PC=%08x\n\n", env->pc);
3134
3135     for (i = j = 0; i < 256; ++i) {
3136         if (xtensa_option_bits_enabled(env->config, sregnames[i].opt_bits)) {
3137             cpu_fprintf(f, "%12s=%08x%c", sregnames[i].name, env->sregs[i],
3138                     (j++ % 4) == 3 ? '\n' : ' ');
3139         }
3140     }
3141
3142     cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
3143
3144     for (i = j = 0; i < 256; ++i) {
3145         if (xtensa_option_bits_enabled(env->config, uregnames[i].opt_bits)) {
3146             cpu_fprintf(f, "%s=%08x%c", uregnames[i].name, env->uregs[i],
3147                     (j++ % 4) == 3 ? '\n' : ' ');
3148         }
3149     }
3150
3151     cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
3152
3153     for (i = 0; i < 16; ++i) {
3154         cpu_fprintf(f, " A%02d=%08x%c", i, env->regs[i],
3155                 (i % 4) == 3 ? '\n' : ' ');
3156     }
3157
3158     cpu_fprintf(f, "\n");
3159
3160     for (i = 0; i < env->config->nareg; ++i) {
3161         cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
3162                 (i % 4) == 3 ? '\n' : ' ');
3163     }
3164
3165     if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
3166         cpu_fprintf(f, "\n");
3167
3168         for (i = 0; i < 16; ++i) {
3169             cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i,
3170                     float32_val(env->fregs[i]),
3171                     *(float *)&env->fregs[i], (i % 2) == 1 ? '\n' : ' ');
3172         }
3173     }
3174 }
3175
3176 void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, int pc_pos)
3177 {
3178     env->pc = tcg_ctx.gen_opc_pc[pc_pos];
3179 }