hw/unin_pci.c

   1 /*
   2  * QEMU Uninorth PCI host (for all Mac99 and newer machines)
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "ppc_mac.h"
  26 #include "pci.h"
  27 #include "pci_host.h"
  28
  29 /* debug UniNorth */
  30 //#define DEBUG_UNIN
  31
  32 #ifdef DEBUG_UNIN
  33 #define UNIN_DPRINTF(fmt, ...)                                  \
  34     do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
  35 #else
  36 #define UNIN_DPRINTF(fmt, ...)
  37 #endif
  38
  39 static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
  40
  41 typedef struct UNINState {
  42     PCIHostState host_state;
  43     MemoryRegion pci_mmio;
  44     MemoryRegion pci_hole;
  45 } UNINState;
  46
  47 static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
  48 {
  49     int retval;
  50     int devfn = pci_dev->devfn & 0x00FFFFFF;
  51
  52     retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;
  53
  54     return retval;
  55 }
  56
  57 static void pci_unin_set_irq(void *opaque, int irq_num, int level)
  58 {
  59     qemu_irq *pic = opaque;
  60
  61     UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
  62                  unin_irq_line[irq_num], level);
  63     qemu_set_irq(pic[unin_irq_line[irq_num]], level);
  64 }
  65
  66 static void pci_unin_reset(void *opaque)
  67 {
  68 }
  69
  70 static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
  71 {
  72     uint32_t retval;
  73
  74     if (reg & (1u << 31)) {
  75         /* XXX OpenBIOS compatibility hack */
  76         retval = reg | (addr & 3);
  77     } else if (reg & 1) {
  78         /* CFA1 style */
  79         retval = (reg & ~7u) | (addr & 7);
  80     } else {
  81         uint32_t slot, func;
  82
  83         /* Grab CFA0 style values */
  84         slot = ffs(reg & 0xfffff800) - 1;
  85         func = (reg >> 8) & 7;
  86
  87         /* ... and then convert them to x86 format */
  88         /* config pointer */
  89         retval = (reg & (0xff - 7)) | (addr & 7);
  90         /* slot */
  91         retval |= slot << 11;
  92         /* fn */
  93         retval |= func << 8;
  94     }
  95
  96
  97     UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
  98                  reg, addr, retval);
  99
 100     return retval;
 101 }
 102
 103 static void unin_data_write(void *opaque, target_phys_addr_t addr,
 104                             uint64_t val, unsigned len)
 105 {
 106     UNINState *s = opaque;
 107     UNIN_DPRINTF("write addr %" TARGET_FMT_plx " len %d val %"PRIx64"\n",
 108                  addr, len, val);
 109     pci_data_write(s->host_state.bus,
 110                    unin_get_config_reg(s->host_state.config_reg, addr),
 111                    val, len);
 112 }
 113
 114 static uint64_t unin_data_read(void *opaque, target_phys_addr_t addr,
 115                                unsigned len)
 116 {
 117     UNINState *s = opaque;
 118     uint32_t val;
 119
 120     val = pci_data_read(s->host_state.bus,
 121                         unin_get_config_reg(s->host_state.config_reg, addr),
 122                         len);
 123     UNIN_DPRINTF("read addr %" TARGET_FMT_plx " len %d val %x\n",
 124                  addr, len, val);
 125     return val;
 126 }
 127
 128 static const MemoryRegionOps unin_data_ops = {
 129     .read = unin_data_read,
 130     .write = unin_data_write,
 131     .endianness = DEVICE_LITTLE_ENDIAN,
 132 };
 133
 134 static int pci_unin_main_init_device(SysBusDevice *dev)
 135 {
 136     PCIHostState *h;
 137     UNINState *s;
 138
 139     /* Use values found on a real PowerMac */
 140     /* Uninorth main bus */
 141     h = FROM_SYSBUS(PCIHostState, dev);
 142     s = DO_UPCAST(UNINState, host_state, h);
 143
 144     memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
 145                           &s->host_state, "pci-conf-idx", 0x1000);
 146     memory_region_init_io(&s->host_state.data_mem, &unin_data_ops, s,
 147                           "pci-conf-data", 0x1000);
 148     sysbus_init_mmio(dev, &s->host_state.conf_mem);
 149     sysbus_init_mmio(dev, &s->host_state.data_mem);
 150
 151     qemu_register_reset(pci_unin_reset, &s->host_state);
 152     return 0;
 153 }
 154
 155
 156 static int pci_u3_agp_init_device(SysBusDevice *dev)
 157 {
 158     PCIHostState *h;
 159     UNINState *s;
 160
 161     /* Uninorth U3 AGP bus */
 162     h = FROM_SYSBUS(PCIHostState, dev);
 163     s = DO_UPCAST(UNINState, host_state, h);
 164
 165     memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
 166                           &s->host_state, "pci-conf-idx", 0x1000);
 167     memory_region_init_io(&s->host_state.data_mem, &unin_data_ops, s,
 168                           "pci-conf-data", 0x1000);
 169     sysbus_init_mmio(dev, &s->host_state.conf_mem);
 170     sysbus_init_mmio(dev, &s->host_state.data_mem);
 171
 172     qemu_register_reset(pci_unin_reset, &s->host_state);
 173
 174     return 0;
 175 }
 176
 177 static int pci_unin_agp_init_device(SysBusDevice *dev)
 178 {
 179     PCIHostState *h;
 180     UNINState *s;
 181
 182     /* Uninorth AGP bus */
 183     h = FROM_SYSBUS(PCIHostState, dev);
 184     s = DO_UPCAST(UNINState, host_state, h);
 185
 186     memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
 187                           &s->host_state, "pci-conf-idx", 0x1000);
 188     memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
 189                           &s->host_state, "pci-conf-data", 0x1000);
 190     sysbus_init_mmio(dev, &s->host_state.conf_mem);
 191     sysbus_init_mmio(dev, &s->host_state.data_mem);
 192     return 0;
 193 }
 194
 195 static int pci_unin_internal_init_device(SysBusDevice *dev)
 196 {
 197     PCIHostState *h;
 198     UNINState *s;
 199
 200     /* Uninorth internal bus */
 201     h = FROM_SYSBUS(PCIHostState, dev);
 202     s = DO_UPCAST(UNINState, host_state, h);
 203
 204     memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
 205                           &s->host_state, "pci-conf-idx", 0x1000);
 206     memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
 207                           &s->host_state, "pci-conf-data", 0x1000);
 208     sysbus_init_mmio(dev, &s->host_state.conf_mem);
 209     sysbus_init_mmio(dev, &s->host_state.data_mem);
 210     return 0;
 211 }
 212
 213 PCIBus *pci_pmac_init(qemu_irq *pic,
 214                       MemoryRegion *address_space_mem,
 215                       MemoryRegion *address_space_io)
 216 {
 217     DeviceState *dev;
 218     SysBusDevice *s;
 219     PCIHostState *h;
 220     UNINState *d;
 221
 222     /* Use values found on a real PowerMac */
 223     /* Uninorth main bus */
 224     dev = qdev_create(NULL, "uni-north-pci-pcihost");
 225     qdev_init_nofail(dev);
 226     s = sysbus_from_qdev(dev);
 227     h = FROM_SYSBUS(PCIHostState, s);
 228     d = DO_UPCAST(UNINState, host_state, h);
 229     memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
 230     memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
 231                              0x80000000ULL, 0x70000000ULL);
 232     memory_region_add_subregion(address_space_mem, 0x80000000ULL,
 233                                 &d->pci_hole);
 234
 235     d->host_state.bus = pci_register_bus(dev, "pci",
 236                                          pci_unin_set_irq, pci_unin_map_irq,
 237                                          pic,
 238                                          &d->pci_mmio,
 239                                          address_space_io,
 240                                          PCI_DEVFN(11, 0), 4);
 241
 242 #if 0
 243     pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north");
 244 #endif
 245
 246     sysbus_mmio_map(s, 0, 0xf2800000);
 247     sysbus_mmio_map(s, 1, 0xf2c00000);
 248
 249     /* DEC 21154 bridge */
 250 #if 0
 251     /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
 252     pci_create_simple(d->host_state.bus, PCI_DEVFN(12, 0), "dec-21154");
 253 #endif
 254
 255     /* Uninorth AGP bus */
 256     pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north-agp");
 257     dev = qdev_create(NULL, "uni-north-agp-pcihost");
 258     qdev_init_nofail(dev);
 259     s = sysbus_from_qdev(dev);
 260     sysbus_mmio_map(s, 0, 0xf0800000);
 261     sysbus_mmio_map(s, 1, 0xf0c00000);
 262
 263     /* Uninorth internal bus */
 264 #if 0
 265     /* XXX: not needed for now */
 266     pci_create_simple(d->host_state.bus, PCI_DEVFN(14, 0),
 267                       "uni-north-internal-pci");
 268     dev = qdev_create(NULL, "uni-north-internal-pci-pcihost");
 269     qdev_init_nofail(dev);
 270     s = sysbus_from_qdev(dev);
 271     sysbus_mmio_map(s, 0, 0xf4800000);
 272     sysbus_mmio_map(s, 1, 0xf4c00000);
 273 #endif
 274
 275     return d->host_state.bus;
 276 }
 277
 278 PCIBus *pci_pmac_u3_init(qemu_irq *pic,
 279                          MemoryRegion *address_space_mem,
 280                          MemoryRegion *address_space_io)
 281 {
 282     DeviceState *dev;
 283     SysBusDevice *s;
 284     PCIHostState *h;
 285     UNINState *d;
 286
 287     /* Uninorth AGP bus */
 288
 289     dev = qdev_create(NULL, "u3-agp-pcihost");
 290     qdev_init_nofail(dev);
 291     s = sysbus_from_qdev(dev);
 292     h = FROM_SYSBUS(PCIHostState, s);
 293     d = DO_UPCAST(UNINState, host_state, h);
 294
 295     memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
 296     memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
 297                              0x80000000ULL, 0x70000000ULL);
 298     memory_region_add_subregion(address_space_mem, 0x80000000ULL,
 299                                 &d->pci_hole);
 300
 301     d->host_state.bus = pci_register_bus(dev, "pci",
 302                                          pci_unin_set_irq, pci_unin_map_irq,
 303                                          pic,
 304                                          &d->pci_mmio,
 305                                          address_space_io,
 306                                          PCI_DEVFN(11, 0), 4);
 307
 308     sysbus_mmio_map(s, 0, 0xf0800000);
 309     sysbus_mmio_map(s, 1, 0xf0c00000);
 310
 311     pci_create_simple(d->host_state.bus, 11 << 3, "u3-agp");
 312
 313     return d->host_state.bus;
 314 }
 315
 316 static int unin_main_pci_host_init(PCIDevice *d)
 317 {
 318     d->config[0x0C] = 0x08; // cache_line_size
 319     d->config[0x0D] = 0x10; // latency_timer
 320     d->config[0x34] = 0x00; // capabilities_pointer
 321     return 0;
 322 }
 323
 324 static int unin_agp_pci_host_init(PCIDevice *d)
 325 {
 326     d->config[0x0C] = 0x08; // cache_line_size
 327     d->config[0x0D] = 0x10; // latency_timer
 328     //    d->config[0x34] = 0x80; // capabilities_pointer
 329     return 0;
 330 }
 331
 332 static int u3_agp_pci_host_init(PCIDevice *d)
 333 {
 334     /* cache line size */
 335     d->config[0x0C] = 0x08;
 336     /* latency timer */
 337     d->config[0x0D] = 0x10;
 338     return 0;
 339 }
 340
 341 static int unin_internal_pci_host_init(PCIDevice *d)
 342 {
 343     d->config[0x0C] = 0x08; // cache_line_size
 344     d->config[0x0D] = 0x10; // latency_timer
 345     d->config[0x34] = 0x00; // capabilities_pointer
 346     return 0;
 347 }
 348
 349 static PCIDeviceInfo unin_main_pci_host_info = {
 350     .qdev.name = "uni-north-pci",
 351     .qdev.size = sizeof(PCIDevice),
 352     .init      = unin_main_pci_host_init,
 353     .vendor_id = PCI_VENDOR_ID_APPLE,
 354     .device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI,
 355     .revision  = 0x00,
 356     .class_id  = PCI_CLASS_BRIDGE_HOST,
 357 };
 358
 359 static PCIDeviceInfo u3_agp_pci_host_info = {
 360     .qdev.name = "u3-agp",
 361     .qdev.size = sizeof(PCIDevice),
 362     .init      = u3_agp_pci_host_init,
 363     .vendor_id = PCI_VENDOR_ID_APPLE,
 364     .device_id = PCI_DEVICE_ID_APPLE_U3_AGP,
 365     .revision  = 0x00,
 366     .class_id  = PCI_CLASS_BRIDGE_HOST,
 367 };
 368
 369 static PCIDeviceInfo unin_agp_pci_host_info = {
 370     .qdev.name = "uni-north-agp",
 371     .qdev.size = sizeof(PCIDevice),
 372     .init      = unin_agp_pci_host_init,
 373     .vendor_id = PCI_VENDOR_ID_APPLE,
 374     .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP,
 375     .revision  = 0x00,
 376     .class_id  = PCI_CLASS_BRIDGE_HOST,
 377 };
 378
 379 static PCIDeviceInfo unin_internal_pci_host_info = {
 380     .qdev.name = "uni-north-internal-pci",
 381     .qdev.size = sizeof(PCIDevice),
 382     .init      = unin_internal_pci_host_init,
 383     .vendor_id = PCI_VENDOR_ID_APPLE,
 384     .device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI,
 385     .revision  = 0x00,
 386     .class_id  = PCI_CLASS_BRIDGE_HOST,
 387 };
 388
 389 static SysBusDeviceInfo sysbus_unin_pci_host_info = {
 390     .qdev.name = "uni-north-pci-pcihost",
 391     .qdev.size = sizeof(UNINState),
 392     .init      = pci_unin_main_init_device,
 393 };
 394
 395 static SysBusDeviceInfo sysbus_u3_agp_pci_host_info = {
 396     .qdev.name = "u3-agp-pcihost",
 397     .qdev.size = sizeof(UNINState),
 398     .init      = pci_u3_agp_init_device,
 399 };
 400
 401 static SysBusDeviceInfo sysbus_unin_agp_pci_host_info = {
 402     .qdev.name = "uni-north-agp-pcihost",
 403     .qdev.size = sizeof(UNINState),
 404     .init      = pci_unin_agp_init_device,
 405 };
 406
 407 static SysBusDeviceInfo sysbus_unin_internal_pci_host_info = {
 408     .qdev.name = "uni-north-internal-pci-pcihost",
 409     .qdev.size = sizeof(UNINState),
 410     .init      = pci_unin_internal_init_device,
 411 };
 412
 413 static void unin_register_devices(void)
 414 {
 415     sysbus_register_withprop(&sysbus_unin_pci_host_info);
 416     pci_qdev_register(&unin_main_pci_host_info);
 417
 418     sysbus_register_withprop(&sysbus_u3_agp_pci_host_info);
 419     pci_qdev_register(&u3_agp_pci_host_info);
 420
 421     sysbus_register_withprop(&sysbus_unin_agp_pci_host_info);
 422     pci_qdev_register(&unin_agp_pci_host_info);
 423
 424     sysbus_register_withprop(&sysbus_unin_internal_pci_host_info);
 425     pci_qdev_register(&unin_internal_pci_host_info);
 426 }
 427
 428 device_init(unin_register_devices)