4 * Copyright (c) 2005 Samuel Tardieu
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #ifndef CONFIG_USER_ONLY
25 #include "exec/softmmu_exec.h"
27 #define MMUSUFFIX _mmu
30 #include "exec/softmmu_template.h"
33 #include "exec/softmmu_template.h"
36 #include "exec/softmmu_template.h"
39 #include "exec/softmmu_template.h"
41 void tlb_fill(CPUSH4State *env, target_ulong addr, int is_write, int mmu_idx,
44 SuperHCPU *cpu = sh_env_get_cpu(env);
47 ret = superh_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
49 /* now we have a real cpu fault */
51 cpu_restore_state(env, retaddr);
59 void helper_ldtlb(CPUSH4State *env)
61 #ifdef CONFIG_USER_ONLY
63 cpu_abort(env, "Unhandled ldtlb");
69 static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
72 CPUState *cs = CPU(sh_env_get_cpu(env));
74 cs->exception_index = index;
76 cpu_restore_state(env, retaddr);
81 void helper_raise_illegal_instruction(CPUSH4State *env)
83 raise_exception(env, 0x180, 0);
86 void helper_raise_slot_illegal_instruction(CPUSH4State *env)
88 raise_exception(env, 0x1a0, 0);
91 void helper_raise_fpu_disable(CPUSH4State *env)
93 raise_exception(env, 0x800, 0);
96 void helper_raise_slot_fpu_disable(CPUSH4State *env)
98 raise_exception(env, 0x820, 0);
101 void helper_debug(CPUSH4State *env)
103 raise_exception(env, EXCP_DEBUG, 0);
106 void helper_sleep(CPUSH4State *env)
108 CPUState *cs = CPU(sh_env_get_cpu(env));
112 raise_exception(env, EXCP_HLT, 0);
115 void helper_trapa(CPUSH4State *env, uint32_t tra)
118 raise_exception(env, 0x160, 0);
121 void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value)
123 if (cpu_sh4_is_cached (env, address))
125 memory_content *r = malloc (sizeof(memory_content));
126 r->address = address;
130 *(env->movcal_backup_tail) = r;
131 env->movcal_backup_tail = &(r->next);
135 void helper_discard_movcal_backup(CPUSH4State *env)
137 memory_content *current = env->movcal_backup;
141 memory_content *next = current->next;
143 env->movcal_backup = current = next;
145 env->movcal_backup_tail = &(env->movcal_backup);
149 void helper_ocbi(CPUSH4State *env, uint32_t address)
151 memory_content **current = &(env->movcal_backup);
154 uint32_t a = (*current)->address;
155 if ((a & ~0x1F) == (address & ~0x1F))
157 memory_content *next = (*current)->next;
158 cpu_stl_data(env, a, (*current)->value);
162 env->movcal_backup_tail = current;
172 #define T (env->sr & SR_T)
173 #define Q (env->sr & SR_Q ? 1 : 0)
174 #define M (env->sr & SR_M ? 1 : 0)
175 #define SETT env->sr |= SR_T
176 #define CLRT env->sr &= ~SR_T
177 #define SETQ env->sr |= SR_Q
178 #define CLRQ env->sr &= ~SR_Q
179 #define SETM env->sr |= SR_M
180 #define CLRM env->sr &= ~SR_M
182 uint32_t helper_div1(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
185 uint8_t old_q, tmp1 = 0xff;
187 //printf("div1 arg0=0x%08x arg1=0x%08x M=%d Q=%d T=%d\n", arg0, arg1, M, Q, T);
189 if ((0x80000000 & arg1) != 0)
286 //printf("Output: arg1=0x%08x M=%d Q=%d T=%d\n", arg1, M, Q, T);
290 void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
294 res = ((uint64_t) env->mach << 32) | env->macl;
295 res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1;
296 env->mach = (res >> 32) & 0xffffffff;
297 env->macl = res & 0xffffffff;
298 if (env->sr & SR_S) {
300 env->mach |= 0xffff0000;
302 env->mach &= 0x00007fff;
306 void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
310 res = ((uint64_t) env->mach << 32) | env->macl;
311 res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1;
312 env->mach = (res >> 32) & 0xffffffff;
313 env->macl = res & 0xffffffff;
314 if (env->sr & SR_S) {
315 if (res < -0x80000000) {
317 env->macl = 0x80000000;
318 } else if (res > 0x000000007fffffff) {
320 env->macl = 0x7fffffff;
325 static inline void set_t(CPUSH4State *env)
330 static inline void clr_t(CPUSH4State *env)
335 void helper_ld_fpscr(CPUSH4State *env, uint32_t val)
337 env->fpscr = val & FPSCR_MASK;
338 if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
339 set_float_rounding_mode(float_round_to_zero, &env->fp_status);
341 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
343 set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
346 static void update_fpscr(CPUSH4State *env, uintptr_t retaddr)
348 int xcpt, cause, enable;
350 xcpt = get_float_exception_flags(&env->fp_status);
352 /* Clear the flag entries */
353 env->fpscr &= ~FPSCR_FLAG_MASK;
355 if (unlikely(xcpt)) {
356 if (xcpt & float_flag_invalid) {
357 env->fpscr |= FPSCR_FLAG_V;
359 if (xcpt & float_flag_divbyzero) {
360 env->fpscr |= FPSCR_FLAG_Z;
362 if (xcpt & float_flag_overflow) {
363 env->fpscr |= FPSCR_FLAG_O;
365 if (xcpt & float_flag_underflow) {
366 env->fpscr |= FPSCR_FLAG_U;
368 if (xcpt & float_flag_inexact) {
369 env->fpscr |= FPSCR_FLAG_I;
372 /* Accumulate in cause entries */
373 env->fpscr |= (env->fpscr & FPSCR_FLAG_MASK)
374 << (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT);
376 /* Generate an exception if enabled */
377 cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
378 enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
379 if (cause & enable) {
380 raise_exception(env, 0x120, retaddr);
385 float32 helper_fabs_FT(float32 t0)
387 return float32_abs(t0);
390 float64 helper_fabs_DT(float64 t0)
392 return float64_abs(t0);
395 float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1)
397 set_float_exception_flags(0, &env->fp_status);
398 t0 = float32_add(t0, t1, &env->fp_status);
399 update_fpscr(env, GETPC());
403 float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1)
405 set_float_exception_flags(0, &env->fp_status);
406 t0 = float64_add(t0, t1, &env->fp_status);
407 update_fpscr(env, GETPC());
411 void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
415 set_float_exception_flags(0, &env->fp_status);
416 relation = float32_compare(t0, t1, &env->fp_status);
417 if (unlikely(relation == float_relation_unordered)) {
418 update_fpscr(env, GETPC());
419 } else if (relation == float_relation_equal) {
426 void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1)
430 set_float_exception_flags(0, &env->fp_status);
431 relation = float64_compare(t0, t1, &env->fp_status);
432 if (unlikely(relation == float_relation_unordered)) {
433 update_fpscr(env, GETPC());
434 } else if (relation == float_relation_equal) {
441 void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1)
445 set_float_exception_flags(0, &env->fp_status);
446 relation = float32_compare(t0, t1, &env->fp_status);
447 if (unlikely(relation == float_relation_unordered)) {
448 update_fpscr(env, GETPC());
449 } else if (relation == float_relation_greater) {
456 void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
460 set_float_exception_flags(0, &env->fp_status);
461 relation = float64_compare(t0, t1, &env->fp_status);
462 if (unlikely(relation == float_relation_unordered)) {
463 update_fpscr(env, GETPC());
464 } else if (relation == float_relation_greater) {
471 float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0)
474 set_float_exception_flags(0, &env->fp_status);
475 ret = float32_to_float64(t0, &env->fp_status);
476 update_fpscr(env, GETPC());
480 float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0)
483 set_float_exception_flags(0, &env->fp_status);
484 ret = float64_to_float32(t0, &env->fp_status);
485 update_fpscr(env, GETPC());
489 float32 helper_fdiv_FT(CPUSH4State *env, float32 t0, float32 t1)
491 set_float_exception_flags(0, &env->fp_status);
492 t0 = float32_div(t0, t1, &env->fp_status);
493 update_fpscr(env, GETPC());
497 float64 helper_fdiv_DT(CPUSH4State *env, float64 t0, float64 t1)
499 set_float_exception_flags(0, &env->fp_status);
500 t0 = float64_div(t0, t1, &env->fp_status);
501 update_fpscr(env, GETPC());
505 float32 helper_float_FT(CPUSH4State *env, uint32_t t0)
508 set_float_exception_flags(0, &env->fp_status);
509 ret = int32_to_float32(t0, &env->fp_status);
510 update_fpscr(env, GETPC());
514 float64 helper_float_DT(CPUSH4State *env, uint32_t t0)
517 set_float_exception_flags(0, &env->fp_status);
518 ret = int32_to_float64(t0, &env->fp_status);
519 update_fpscr(env, GETPC());
523 float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2)
525 set_float_exception_flags(0, &env->fp_status);
526 t0 = float32_muladd(t0, t1, t2, 0, &env->fp_status);
527 update_fpscr(env, GETPC());
531 float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1)
533 set_float_exception_flags(0, &env->fp_status);
534 t0 = float32_mul(t0, t1, &env->fp_status);
535 update_fpscr(env, GETPC());
539 float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1)
541 set_float_exception_flags(0, &env->fp_status);
542 t0 = float64_mul(t0, t1, &env->fp_status);
543 update_fpscr(env, GETPC());
547 float32 helper_fneg_T(float32 t0)
549 return float32_chs(t0);
552 float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0)
554 set_float_exception_flags(0, &env->fp_status);
555 t0 = float32_sqrt(t0, &env->fp_status);
556 update_fpscr(env, GETPC());
560 float64 helper_fsqrt_DT(CPUSH4State *env, float64 t0)
562 set_float_exception_flags(0, &env->fp_status);
563 t0 = float64_sqrt(t0, &env->fp_status);
564 update_fpscr(env, GETPC());
568 float32 helper_fsub_FT(CPUSH4State *env, float32 t0, float32 t1)
570 set_float_exception_flags(0, &env->fp_status);
571 t0 = float32_sub(t0, t1, &env->fp_status);
572 update_fpscr(env, GETPC());
576 float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1)
578 set_float_exception_flags(0, &env->fp_status);
579 t0 = float64_sub(t0, t1, &env->fp_status);
580 update_fpscr(env, GETPC());
584 uint32_t helper_ftrc_FT(CPUSH4State *env, float32 t0)
587 set_float_exception_flags(0, &env->fp_status);
588 ret = float32_to_int32_round_to_zero(t0, &env->fp_status);
589 update_fpscr(env, GETPC());
593 uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0)
596 set_float_exception_flags(0, &env->fp_status);
597 ret = float64_to_int32_round_to_zero(t0, &env->fp_status);
598 update_fpscr(env, GETPC());
602 void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n)
607 bank = (env->sr & FPSCR_FR) ? 16 : 0;
609 set_float_exception_flags(0, &env->fp_status);
611 for (i = 0 ; i < 4 ; i++) {
612 p = float32_mul(env->fregs[bank + m + i],
613 env->fregs[bank + n + i],
615 r = float32_add(r, p, &env->fp_status);
617 update_fpscr(env, GETPC());
619 env->fregs[bank + n + 3] = r;
622 void helper_ftrv(CPUSH4State *env, uint32_t n)
624 int bank_matrix, bank_vector;
629 bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
630 bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
631 set_float_exception_flags(0, &env->fp_status);
632 for (i = 0 ; i < 4 ; i++) {
634 for (j = 0 ; j < 4 ; j++) {
635 p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
636 env->fregs[bank_vector + j],
638 r[i] = float32_add(r[i], p, &env->fp_status);
641 update_fpscr(env, GETPC());
643 for (i = 0 ; i < 4 ; i++) {
644 env->fregs[bank_vector + i] = r[i];