drivers/net/wireless/ath/ath9k/eeprom_def.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar9002_phy.h"
  19
  20 static void ath9k_get_txgain_index(struct ath_hw *ah,
  21                 struct ath9k_channel *chan,
  22                 struct calDataPerFreqOpLoop *rawDatasetOpLoop,
  23                 u8 *calChans,  u16 availPiers, u8 *pwr, u8 *pcdacIdx)
  24 {
  25         u8 pcdac, i = 0;
  26         u16 idxL = 0, idxR = 0, numPiers;
  27         bool match;
  28         struct chan_centers centers;
  29
  30         ath9k_hw_get_channel_centers(ah, chan, &centers);
  31
  32         for (numPiers = 0; numPiers < availPiers; numPiers++)
  33                 if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
  34                         break;
  35
  36         match = ath9k_hw_get_lower_upper_index(
  37                         (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
  38                         calChans, numPiers, &idxL, &idxR);
  39         if (match) {
  40                 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
  41                 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
  42         } else {
  43                 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
  44                 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
  45                                 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
  46         }
  47
  48         while (pcdac > ah->originalGain[i] &&
  49                         i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
  50                 i++;
  51
  52         *pcdacIdx = i;
  53         return;
  54 }
  55
  56 static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
  57                                 u32 initTxGain,
  58                                 int txPower,
  59                                 u8 *pPDADCValues)
  60 {
  61         u32 i;
  62         u32 offset;
  63
  64         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
  65                         AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
  66         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
  67                         AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
  68
  69         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
  70                         AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
  71
  72         offset = txPower;
  73         for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
  74                 if (i < offset)
  75                         pPDADCValues[i] = 0x0;
  76                 else
  77                         pPDADCValues[i] = 0xFF;
  78 }
  79
  80 static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
  81 {
  82         return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
  83 }
  84
  85 static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
  86 {
  87         return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
  88 }
  89
  90 static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
  91 {
  92 #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
  93         struct ath_common *common = ath9k_hw_common(ah);
  94         u16 *eep_data = (u16 *)&ah->eeprom.def;
  95         int addr, ar5416_eep_start_loc = 0x100;
  96
  97         for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
  98                 if (!ath9k_hw_nvram_read(common, addr + ar5416_eep_start_loc,
  99                                          eep_data)) {
 100                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 101                                   "Unable to read eeprom region\n");
 102                         return false;
 103                 }
 104                 eep_data++;
 105         }
 106         return true;
 107 #undef SIZE_EEPROM_DEF
 108 }
 109
 110 static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
 111 {
 112         struct ar5416_eeprom_def *eep =
 113                 (struct ar5416_eeprom_def *) &ah->eeprom.def;
 114         struct ath_common *common = ath9k_hw_common(ah);
 115         u16 *eepdata, temp, magic, magic2;
 116         u32 sum = 0, el;
 117         bool need_swap = false;
 118         int i, addr, size;
 119
 120         if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
 121                 ath_print(common, ATH_DBG_FATAL, "Reading Magic # failed\n");
 122                 return false;
 123         }
 124
 125         if (!ath9k_hw_use_flash(ah)) {
 126                 ath_print(common, ATH_DBG_EEPROM,
 127                           "Read Magic = 0x%04X\n", magic);
 128
 129                 if (magic != AR5416_EEPROM_MAGIC) {
 130                         magic2 = swab16(magic);
 131
 132                         if (magic2 == AR5416_EEPROM_MAGIC) {
 133                                 size = sizeof(struct ar5416_eeprom_def);
 134                                 need_swap = true;
 135                                 eepdata = (u16 *) (&ah->eeprom);
 136
 137                                 for (addr = 0; addr < size / sizeof(u16); addr++) {
 138                                         temp = swab16(*eepdata);
 139                                         *eepdata = temp;
 140                                         eepdata++;
 141                                 }
 142                         } else {
 143                                 ath_print(common, ATH_DBG_FATAL,
 144                                           "Invalid EEPROM Magic. "
 145                                           "Endianness mismatch.\n");
 146                                 return -EINVAL;
 147                         }
 148                 }
 149         }
 150
 151         ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
 152                   need_swap ? "True" : "False");
 153
 154         if (need_swap)
 155                 el = swab16(ah->eeprom.def.baseEepHeader.length);
 156         else
 157                 el = ah->eeprom.def.baseEepHeader.length;
 158
 159         if (el > sizeof(struct ar5416_eeprom_def))
 160                 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
 161         else
 162                 el = el / sizeof(u16);
 163
 164         eepdata = (u16 *)(&ah->eeprom);
 165
 166         for (i = 0; i < el; i++)
 167                 sum ^= *eepdata++;
 168
 169         if (need_swap) {
 170                 u32 integer, j;
 171                 u16 word;
 172
 173                 ath_print(common, ATH_DBG_EEPROM,
 174                           "EEPROM Endianness is not native.. Changing.\n");
 175
 176                 word = swab16(eep->baseEepHeader.length);
 177                 eep->baseEepHeader.length = word;
 178
 179                 word = swab16(eep->baseEepHeader.checksum);
 180                 eep->baseEepHeader.checksum = word;
 181
 182                 word = swab16(eep->baseEepHeader.version);
 183                 eep->baseEepHeader.version = word;
 184
 185                 word = swab16(eep->baseEepHeader.regDmn[0]);
 186                 eep->baseEepHeader.regDmn[0] = word;
 187
 188                 word = swab16(eep->baseEepHeader.regDmn[1]);
 189                 eep->baseEepHeader.regDmn[1] = word;
 190
 191                 word = swab16(eep->baseEepHeader.rfSilent);
 192                 eep->baseEepHeader.rfSilent = word;
 193
 194                 word = swab16(eep->baseEepHeader.blueToothOptions);
 195                 eep->baseEepHeader.blueToothOptions = word;
 196
 197                 word = swab16(eep->baseEepHeader.deviceCap);
 198                 eep->baseEepHeader.deviceCap = word;
 199
 200                 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
 201                         struct modal_eep_header *pModal =
 202                                 &eep->modalHeader[j];
 203                         integer = swab32(pModal->antCtrlCommon);
 204                         pModal->antCtrlCommon = integer;
 205
 206                         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 207                                 integer = swab32(pModal->antCtrlChain[i]);
 208                                 pModal->antCtrlChain[i] = integer;
 209                         }
 210
 211                         for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
 212                                 word = swab16(pModal->spurChans[i].spurChan);
 213                                 pModal->spurChans[i].spurChan = word;
 214                         }
 215                 }
 216         }
 217
 218         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
 219             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
 220                 ath_print(common, ATH_DBG_FATAL,
 221                           "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
 222                         sum, ah->eep_ops->get_eeprom_ver(ah));
 223                 return -EINVAL;
 224         }
 225
 226         return 0;
 227 }
 228
 229 static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
 230                                    enum eeprom_param param)
 231 {
 232         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
 233         struct modal_eep_header *pModal = eep->modalHeader;
 234         struct base_eep_header *pBase = &eep->baseEepHeader;
 235
 236         switch (param) {
 237         case EEP_NFTHRESH_5:
 238                 return pModal[0].noiseFloorThreshCh[0];
 239         case EEP_NFTHRESH_2:
 240                 return pModal[1].noiseFloorThreshCh[0];
 241         case AR_EEPROM_MAC(0):
 242                 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
 243         case AR_EEPROM_MAC(1):
 244                 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
 245         case AR_EEPROM_MAC(2):
 246                 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
 247         case EEP_REG_0:
 248                 return pBase->regDmn[0];
 249         case EEP_REG_1:
 250                 return pBase->regDmn[1];
 251         case EEP_OP_CAP:
 252                 return pBase->deviceCap;
 253         case EEP_OP_MODE:
 254                 return pBase->opCapFlags;
 255         case EEP_RF_SILENT:
 256                 return pBase->rfSilent;
 257         case EEP_OB_5:
 258                 return pModal[0].ob;
 259         case EEP_DB_5:
 260                 return pModal[0].db;
 261         case EEP_OB_2:
 262                 return pModal[1].ob;
 263         case EEP_DB_2:
 264                 return pModal[1].db;
 265         case EEP_MINOR_REV:
 266                 return AR5416_VER_MASK;
 267         case EEP_TX_MASK:
 268                 return pBase->txMask;
 269         case EEP_RX_MASK:
 270                 return pBase->rxMask;
 271         case EEP_RXGAIN_TYPE:
 272                 return pBase->rxGainType;
 273         case EEP_TXGAIN_TYPE:
 274                 return pBase->txGainType;
 275         case EEP_OL_PWRCTRL:
 276                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
 277                         return pBase->openLoopPwrCntl ? true : false;
 278                 else
 279                         return false;
 280         case EEP_RC_CHAIN_MASK:
 281                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
 282                         return pBase->rcChainMask;
 283                 else
 284                         return 0;
 285         case EEP_DAC_HPWR_5G:
 286                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
 287                         return pBase->dacHiPwrMode_5G;
 288                 else
 289                         return 0;
 290         case EEP_FRAC_N_5G:
 291                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
 292                         return pBase->frac_n_5g;
 293                 else
 294                         return 0;
 295         case EEP_PWR_TABLE_OFFSET:
 296                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_21)
 297                         return pBase->pwr_table_offset;
 298                 else
 299                         return AR5416_PWR_TABLE_OFFSET_DB;
 300         default:
 301                 return 0;
 302         }
 303 }
 304
 305 static void ath9k_hw_def_set_gain(struct ath_hw *ah,
 306                                   struct modal_eep_header *pModal,
 307                                   struct ar5416_eeprom_def *eep,
 308                                   u8 txRxAttenLocal, int regChainOffset, int i)
 309 {
 310         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
 311                 txRxAttenLocal = pModal->txRxAttenCh[i];
 312
 313                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 314                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 315                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
 316                               pModal->bswMargin[i]);
 317                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 318                               AR_PHY_GAIN_2GHZ_XATTEN1_DB,
 319                               pModal->bswAtten[i]);
 320                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 321                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
 322                               pModal->xatten2Margin[i]);
 323                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 324                               AR_PHY_GAIN_2GHZ_XATTEN2_DB,
 325                               pModal->xatten2Db[i]);
 326                 } else {
 327                         REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 328                           (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
 329                            ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
 330                           | SM(pModal-> bswMargin[i],
 331                                AR_PHY_GAIN_2GHZ_BSW_MARGIN));
 332                         REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 333                           (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
 334                            ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
 335                           | SM(pModal->bswAtten[i],
 336                                AR_PHY_GAIN_2GHZ_BSW_ATTEN));
 337                 }
 338         }
 339
 340         if (AR_SREV_9280_10_OR_LATER(ah)) {
 341                 REG_RMW_FIELD(ah,
 342                       AR_PHY_RXGAIN + regChainOffset,
 343                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
 344                 REG_RMW_FIELD(ah,
 345                       AR_PHY_RXGAIN + regChainOffset,
 346                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
 347         } else {
 348                 REG_WRITE(ah,
 349                           AR_PHY_RXGAIN + regChainOffset,
 350                           (REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) &
 351                            ~AR_PHY_RXGAIN_TXRX_ATTEN)
 352                           | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN));
 353                 REG_WRITE(ah,
 354                           AR_PHY_GAIN_2GHZ + regChainOffset,
 355                           (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
 356                            ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
 357                           SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
 358         }
 359 }
 360
 361 static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
 362                                           struct ath9k_channel *chan)
 363 {
 364         struct modal_eep_header *pModal;
 365         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
 366         int i, regChainOffset;
 367         u8 txRxAttenLocal;
 368
 369         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
 370         txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
 371
 372         REG_WRITE(ah, AR_PHY_SWITCH_COM,
 373                   ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
 374
 375         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 376                 if (AR_SREV_9280(ah)) {
 377                         if (i >= 2)
 378                                 break;
 379                 }
 380
 381                 if (AR_SREV_5416_20_OR_LATER(ah) &&
 382                     (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
 383                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
 384                 else
 385                         regChainOffset = i * 0x1000;
 386
 387                 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
 388                           pModal->antCtrlChain[i]);
 389
 390                 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
 391                           (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
 392                            ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
 393                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
 394                           SM(pModal->iqCalICh[i],
 395                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
 396                           SM(pModal->iqCalQCh[i],
 397                              AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
 398
 399                 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah))
 400                         ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
 401                                               regChainOffset, i);
 402         }
 403
 404         if (AR_SREV_9280_10_OR_LATER(ah)) {
 405                 if (IS_CHAN_2GHZ(chan)) {
 406                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
 407                                                   AR_AN_RF2G1_CH0_OB,
 408                                                   AR_AN_RF2G1_CH0_OB_S,
 409                                                   pModal->ob);
 410                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
 411                                                   AR_AN_RF2G1_CH0_DB,
 412                                                   AR_AN_RF2G1_CH0_DB_S,
 413                                                   pModal->db);
 414                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
 415                                                   AR_AN_RF2G1_CH1_OB,
 416                                                   AR_AN_RF2G1_CH1_OB_S,
 417                                                   pModal->ob_ch1);
 418                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
 419                                                   AR_AN_RF2G1_CH1_DB,
 420                                                   AR_AN_RF2G1_CH1_DB_S,
 421                                                   pModal->db_ch1);
 422                 } else {
 423                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
 424                                                   AR_AN_RF5G1_CH0_OB5,
 425                                                   AR_AN_RF5G1_CH0_OB5_S,
 426                                                   pModal->ob);
 427                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
 428                                                   AR_AN_RF5G1_CH0_DB5,
 429                                                   AR_AN_RF5G1_CH0_DB5_S,
 430                                                   pModal->db);
 431                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
 432                                                   AR_AN_RF5G1_CH1_OB5,
 433                                                   AR_AN_RF5G1_CH1_OB5_S,
 434                                                   pModal->ob_ch1);
 435                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
 436                                                   AR_AN_RF5G1_CH1_DB5,
 437                                                   AR_AN_RF5G1_CH1_DB5_S,
 438                                                   pModal->db_ch1);
 439                 }
 440                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
 441                                           AR_AN_TOP2_XPABIAS_LVL,
 442                                           AR_AN_TOP2_XPABIAS_LVL_S,
 443                                           pModal->xpaBiasLvl);
 444                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
 445                                           AR_AN_TOP2_LOCALBIAS,
 446                                           AR_AN_TOP2_LOCALBIAS_S,
 447                                           pModal->local_bias);
 448                 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
 449                               pModal->force_xpaon);
 450         }
 451
 452         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
 453                       pModal->switchSettling);
 454         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
 455                       pModal->adcDesiredSize);
 456
 457         if (!AR_SREV_9280_10_OR_LATER(ah))
 458                 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
 459                               AR_PHY_DESIRED_SZ_PGA,
 460                               pModal->pgaDesiredSize);
 461
 462         REG_WRITE(ah, AR_PHY_RF_CTL4,
 463                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
 464                   | SM(pModal->txEndToXpaOff,
 465                        AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
 466                   | SM(pModal->txFrameToXpaOn,
 467                        AR_PHY_RF_CTL4_FRAME_XPAA_ON)
 468                   | SM(pModal->txFrameToXpaOn,
 469                        AR_PHY_RF_CTL4_FRAME_XPAB_ON));
 470
 471         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
 472                       pModal->txEndToRxOn);
 473
 474         if (AR_SREV_9280_10_OR_LATER(ah)) {
 475                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
 476                               pModal->thresh62);
 477                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
 478                               AR_PHY_EXT_CCA0_THRESH62,
 479                               pModal->thresh62);
 480         } else {
 481                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
 482                               pModal->thresh62);
 483                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
 484                               AR_PHY_EXT_CCA_THRESH62,
 485                               pModal->thresh62);
 486         }
 487
 488         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
 489                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
 490                               AR_PHY_TX_END_DATA_START,
 491                               pModal->txFrameToDataStart);
 492                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
 493                               pModal->txFrameToPaOn);
 494         }
 495
 496         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
 497                 if (IS_CHAN_HT40(chan))
 498                         REG_RMW_FIELD(ah, AR_PHY_SETTLING,
 499                                       AR_PHY_SETTLING_SWITCH,
 500                                       pModal->swSettleHt40);
 501         }
 502
 503         if (AR_SREV_9280_20_OR_LATER(ah) &&
 504             AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
 505                 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
 506                               AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
 507                               pModal->miscBits);
 508
 509
 510         if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
 511                 if (IS_CHAN_2GHZ(chan))
 512                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
 513                                         eep->baseEepHeader.dacLpMode);
 514                 else if (eep->baseEepHeader.dacHiPwrMode_5G)
 515                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
 516                 else
 517                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
 518                                       eep->baseEepHeader.dacLpMode);
 519
 520                 udelay(100);
 521
 522                 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
 523                               pModal->miscBits >> 2);
 524
 525                 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
 526                               AR_PHY_TX_DESIRED_SCALE_CCK,
 527                               eep->baseEepHeader.desiredScaleCCK);
 528         }
 529 }
 530
 531 static void ath9k_hw_def_set_addac(struct ath_hw *ah,
 532                                    struct ath9k_channel *chan)
 533 {
 534 #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
 535         struct modal_eep_header *pModal;
 536         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
 537         u8 biaslevel;
 538
 539         if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
 540                 return;
 541
 542         if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
 543                 return;
 544
 545         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
 546
 547         if (pModal->xpaBiasLvl != 0xff) {
 548                 biaslevel = pModal->xpaBiasLvl;
 549         } else {
 550                 u16 resetFreqBin, freqBin, freqCount = 0;
 551                 struct chan_centers centers;
 552
 553                 ath9k_hw_get_channel_centers(ah, chan, &centers);
 554
 555                 resetFreqBin = FREQ2FBIN(centers.synth_center,
 556                                          IS_CHAN_2GHZ(chan));
 557                 freqBin = XPA_LVL_FREQ(0) & 0xff;
 558                 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
 559
 560                 freqCount++;
 561
 562                 while (freqCount < 3) {
 563                         if (XPA_LVL_FREQ(freqCount) == 0x0)
 564                                 break;
 565
 566                         freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
 567                         if (resetFreqBin >= freqBin)
 568                                 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
 569                         else
 570                                 break;
 571                         freqCount++;
 572                 }
 573         }
 574
 575         if (IS_CHAN_2GHZ(chan)) {
 576                 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
 577                                         7, 1) & (~0x18)) | biaslevel << 3;
 578         } else {
 579                 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
 580                                         6, 1) & (~0xc0)) | biaslevel << 6;
 581         }
 582 #undef XPA_LVL_FREQ
 583 }
 584
 585 static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
 586                                 struct ath9k_channel *chan,
 587                                 struct cal_data_per_freq *pRawDataSet,
 588                                 u8 *bChans, u16 availPiers,
 589                                 u16 tPdGainOverlap, int16_t *pMinCalPower,
 590                                 u16 *pPdGainBoundaries, u8 *pPDADCValues,
 591                                 u16 numXpdGains)
 592 {
 593         int i, j, k;
 594         int16_t ss;
 595         u16 idxL = 0, idxR = 0, numPiers;
 596         static u8 vpdTableL[AR5416_NUM_PD_GAINS]
 597                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 598         static u8 vpdTableR[AR5416_NUM_PD_GAINS]
 599                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 600         static u8 vpdTableI[AR5416_NUM_PD_GAINS]
 601                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 602
 603         u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
 604         u8 minPwrT4[AR5416_NUM_PD_GAINS];
 605         u8 maxPwrT4[AR5416_NUM_PD_GAINS];
 606         int16_t vpdStep;
 607         int16_t tmpVal;
 608         u16 sizeCurrVpdTable, maxIndex, tgtIndex;
 609         bool match;
 610         int16_t minDelta = 0;
 611         struct chan_centers centers;
 612
 613         ath9k_hw_get_channel_centers(ah, chan, &centers);
 614
 615         for (numPiers = 0; numPiers < availPiers; numPiers++) {
 616                 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
 617                         break;
 618         }
 619
 620         match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
 621                                                              IS_CHAN_2GHZ(chan)),
 622                                                bChans, numPiers, &idxL, &idxR);
 623
 624         if (match) {
 625                 for (i = 0; i < numXpdGains; i++) {
 626                         minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
 627                         maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
 628                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
 629                                         pRawDataSet[idxL].pwrPdg[i],
 630                                         pRawDataSet[idxL].vpdPdg[i],
 631                                         AR5416_PD_GAIN_ICEPTS,
 632                                         vpdTableI[i]);
 633                 }
 634         } else {
 635                 for (i = 0; i < numXpdGains; i++) {
 636                         pVpdL = pRawDataSet[idxL].vpdPdg[i];
 637                         pPwrL = pRawDataSet[idxL].pwrPdg[i];
 638                         pVpdR = pRawDataSet[idxR].vpdPdg[i];
 639                         pPwrR = pRawDataSet[idxR].pwrPdg[i];
 640
 641                         minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
 642
 643                         maxPwrT4[i] =
 644                                 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
 645                                     pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
 646
 647
 648                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
 649                                                 pPwrL, pVpdL,
 650                                                 AR5416_PD_GAIN_ICEPTS,
 651                                                 vpdTableL[i]);
 652                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
 653                                                 pPwrR, pVpdR,
 654                                                 AR5416_PD_GAIN_ICEPTS,
 655                                                 vpdTableR[i]);
 656
 657                         for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
 658                                 vpdTableI[i][j] =
 659                                         (u8)(ath9k_hw_interpolate((u16)
 660                                              FREQ2FBIN(centers.
 661                                                        synth_center,
 662                                                        IS_CHAN_2GHZ
 663                                                        (chan)),
 664                                              bChans[idxL], bChans[idxR],
 665                                              vpdTableL[i][j], vpdTableR[i][j]));
 666                         }
 667                 }
 668         }
 669
 670         *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
 671
 672         k = 0;
 673
 674         for (i = 0; i < numXpdGains; i++) {
 675                 if (i == (numXpdGains - 1))
 676                         pPdGainBoundaries[i] =
 677                                 (u16)(maxPwrT4[i] / 2);
 678                 else
 679                         pPdGainBoundaries[i] =
 680                                 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
 681
 682                 pPdGainBoundaries[i] =
 683                         min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
 684
 685                 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
 686                         minDelta = pPdGainBoundaries[0] - 23;
 687                         pPdGainBoundaries[0] = 23;
 688                 } else {
 689                         minDelta = 0;
 690                 }
 691
 692                 if (i == 0) {
 693                         if (AR_SREV_9280_10_OR_LATER(ah))
 694                                 ss = (int16_t)(0 - (minPwrT4[i] / 2));
 695                         else
 696                                 ss = 0;
 697                 } else {
 698                         ss = (int16_t)((pPdGainBoundaries[i - 1] -
 699                                         (minPwrT4[i] / 2)) -
 700                                        tPdGainOverlap + 1 + minDelta);
 701                 }
 702                 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
 703                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
 704
 705                 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
 706                         tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
 707                         pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
 708                         ss++;
 709                 }
 710
 711                 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
 712                 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
 713                                 (minPwrT4[i] / 2));
 714                 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
 715                         tgtIndex : sizeCurrVpdTable;
 716
 717                 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
 718                         pPDADCValues[k++] = vpdTableI[i][ss++];
 719                 }
 720
 721                 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
 722                                     vpdTableI[i][sizeCurrVpdTable - 2]);
 723                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
 724
 725                 if (tgtIndex > maxIndex) {
 726                         while ((ss <= tgtIndex) &&
 727                                (k < (AR5416_NUM_PDADC_VALUES - 1))) {
 728                                 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
 729                                                     (ss - maxIndex + 1) * vpdStep));
 730                                 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
 731                                                          255 : tmpVal);
 732                                 ss++;
 733                         }
 734                 }
 735         }
 736
 737         while (i < AR5416_PD_GAINS_IN_MASK) {
 738                 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
 739                 i++;
 740         }
 741
 742         while (k < AR5416_NUM_PDADC_VALUES) {
 743                 pPDADCValues[k] = pPDADCValues[k - 1];
 744                 k++;
 745         }
 746
 747         return;
 748 }
 749
 750 static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
 751                                 u16 *gb,
 752                                 u16 numXpdGain,
 753                                 u16 pdGainOverlap_t2,
 754                                 int8_t pwr_table_offset,
 755                                 int16_t *diff)
 756
 757 {
 758         u16 k;
 759
 760         /* Prior to writing the boundaries or the pdadc vs. power table
 761          * into the chip registers the default starting point on the pdadc
 762          * vs. power table needs to be checked and the curve boundaries
 763          * adjusted accordingly
 764          */
 765         if (AR_SREV_9280_20_OR_LATER(ah)) {
 766                 u16 gb_limit;
 767
 768                 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
 769                         /* get the difference in dB */
 770                         *diff = (u16)(pwr_table_offset - AR5416_PWR_TABLE_OFFSET_DB);
 771                         /* get the number of half dB steps */
 772                         *diff *= 2;
 773                         /* change the original gain boundary settings
 774                          * by the number of half dB steps
 775                          */
 776                         for (k = 0; k < numXpdGain; k++)
 777                                 gb[k] = (u16)(gb[k] - *diff);
 778                 }
 779                 /* Because of a hardware limitation, ensure the gain boundary
 780                  * is not larger than (63 - overlap)
 781                  */
 782                 gb_limit = (u16)(AR5416_MAX_RATE_POWER - pdGainOverlap_t2);
 783
 784                 for (k = 0; k < numXpdGain; k++)
 785                         gb[k] = (u16)min(gb_limit, gb[k]);
 786         }
 787
 788         return *diff;
 789 }
 790
 791 static void ath9k_adjust_pdadc_values(struct ath_hw *ah,
 792                                       int8_t pwr_table_offset,
 793                                       int16_t diff,
 794                                       u8 *pdadcValues)
 795 {
 796 #define NUM_PDADC(diff) (AR5416_NUM_PDADC_VALUES - diff)
 797         u16 k;
 798
 799         /* If this is a board that has a pwrTableOffset that differs from
 800          * the default AR5416_PWR_TABLE_OFFSET_DB then the start of the
 801          * pdadc vs pwr table needs to be adjusted prior to writing to the
 802          * chip.
 803          */
 804         if (AR_SREV_9280_20_OR_LATER(ah)) {
 805                 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
 806                         /* shift the table to start at the new offset */
 807                         for (k = 0; k < (u16)NUM_PDADC(diff); k++ ) {
 808                                 pdadcValues[k] = pdadcValues[k + diff];
 809                         }
 810
 811                         /* fill the back of the table */
 812                         for (k = (u16)NUM_PDADC(diff); k < NUM_PDADC(0); k++) {
 813                                 pdadcValues[k] = pdadcValues[NUM_PDADC(diff)];
 814                         }
 815                 }
 816         }
 817 #undef NUM_PDADC
 818 }
 819
 820 static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
 821                                   struct ath9k_channel *chan,
 822                                   int16_t *pTxPowerIndexOffset)
 823 {
 824 #define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
 825 #define SM_PDGAIN_B(x, y) \
 826                 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
 827         struct ath_common *common = ath9k_hw_common(ah);
 828         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
 829         struct cal_data_per_freq *pRawDataset;
 830         u8 *pCalBChans = NULL;
 831         u16 pdGainOverlap_t2;
 832         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
 833         u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
 834         u16 numPiers, i, j;
 835         int16_t tMinCalPower, diff = 0;
 836         u16 numXpdGain, xpdMask;
 837         u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
 838         u32 reg32, regOffset, regChainOffset;
 839         int16_t modalIdx;
 840         int8_t pwr_table_offset;
 841
 842         modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
 843         xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
 844
 845         pwr_table_offset = ah->eep_ops->get_eeprom(ah, EEP_PWR_TABLE_OFFSET);
 846
 847         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 848             AR5416_EEP_MINOR_VER_2) {
 849                 pdGainOverlap_t2 =
 850                         pEepData->modalHeader[modalIdx].pdGainOverlap;
 851         } else {
 852                 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
 853                                             AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
 854         }
 855
 856         if (IS_CHAN_2GHZ(chan)) {
 857                 pCalBChans = pEepData->calFreqPier2G;
 858                 numPiers = AR5416_NUM_2G_CAL_PIERS;
 859         } else {
 860                 pCalBChans = pEepData->calFreqPier5G;
 861                 numPiers = AR5416_NUM_5G_CAL_PIERS;
 862         }
 863
 864         if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) {
 865                 pRawDataset = pEepData->calPierData2G[0];
 866                 ah->initPDADC = ((struct calDataPerFreqOpLoop *)
 867                                  pRawDataset)->vpdPdg[0][0];
 868         }
 869
 870         numXpdGain = 0;
 871
 872         for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
 873                 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
 874                         if (numXpdGain >= AR5416_NUM_PD_GAINS)
 875                                 break;
 876                         xpdGainValues[numXpdGain] =
 877                                 (u16)(AR5416_PD_GAINS_IN_MASK - i);
 878                         numXpdGain++;
 879                 }
 880         }
 881
 882         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
 883                       (numXpdGain - 1) & 0x3);
 884         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
 885                       xpdGainValues[0]);
 886         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
 887                       xpdGainValues[1]);
 888         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
 889                       xpdGainValues[2]);
 890
 891         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 892                 if (AR_SREV_5416_20_OR_LATER(ah) &&
 893                     (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
 894                     (i != 0)) {
 895                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
 896                 } else
 897                         regChainOffset = i * 0x1000;
 898
 899                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
 900                         if (IS_CHAN_2GHZ(chan))
 901                                 pRawDataset = pEepData->calPierData2G[i];
 902                         else
 903                                 pRawDataset = pEepData->calPierData5G[i];
 904
 905
 906                         if (OLC_FOR_AR9280_20_LATER) {
 907                                 u8 pcdacIdx;
 908                                 u8 txPower;
 909
 910                                 ath9k_get_txgain_index(ah, chan,
 911                                 (struct calDataPerFreqOpLoop *)pRawDataset,
 912                                 pCalBChans, numPiers, &txPower, &pcdacIdx);
 913                                 ath9k_olc_get_pdadcs(ah, pcdacIdx,
 914                                                      txPower/2, pdadcValues);
 915                         } else {
 916                                 ath9k_hw_get_def_gain_boundaries_pdadcs(ah,
 917                                                         chan, pRawDataset,
 918                                                         pCalBChans, numPiers,
 919                                                         pdGainOverlap_t2,
 920                                                         &tMinCalPower,
 921                                                         gainBoundaries,
 922                                                         pdadcValues,
 923                                                         numXpdGain);
 924                         }
 925
 926                         diff = ath9k_change_gain_boundary_setting(ah,
 927                                                            gainBoundaries,
 928                                                            numXpdGain,
 929                                                            pdGainOverlap_t2,
 930                                                            pwr_table_offset,
 931                                                            &diff);
 932
 933                         if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
 934                                 if (OLC_FOR_AR9280_20_LATER) {
 935                                         REG_WRITE(ah,
 936                                                 AR_PHY_TPCRG5 + regChainOffset,
 937                                                 SM(0x6,
 938                                                 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
 939                                                 SM_PD_GAIN(1) | SM_PD_GAIN(2) |
 940                                                 SM_PD_GAIN(3) | SM_PD_GAIN(4));
 941                                 } else {
 942                                         REG_WRITE(ah,
 943                                                 AR_PHY_TPCRG5 + regChainOffset,
 944                                                 SM(pdGainOverlap_t2,
 945                                                 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
 946                                                 SM_PDGAIN_B(0, 1) |
 947                                                 SM_PDGAIN_B(1, 2) |
 948                                                 SM_PDGAIN_B(2, 3) |
 949                                                 SM_PDGAIN_B(3, 4));
 950                                 }
 951                         }
 952
 953
 954                         ath9k_adjust_pdadc_values(ah, pwr_table_offset,
 955                                                   diff, pdadcValues);
 956
 957                         regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
 958                         for (j = 0; j < 32; j++) {
 959                                 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
 960                                         ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
 961                                         ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
 962                                         ((pdadcValues[4 * j + 3] & 0xFF) << 24);
 963                                 REG_WRITE(ah, regOffset, reg32);
 964
 965                                 ath_print(common, ATH_DBG_EEPROM,
 966                                           "PDADC (%d,%4x): %4.4x %8.8x\n",
 967                                           i, regChainOffset, regOffset,
 968                                           reg32);
 969                                 ath_print(common, ATH_DBG_EEPROM,
 970                                           "PDADC: Chain %d | PDADC %3d "
 971                                           "Value %3d | PDADC %3d Value %3d | "
 972                                           "PDADC %3d Value %3d | PDADC %3d "
 973                                           "Value %3d |\n",
 974                                           i, 4 * j, pdadcValues[4 * j],
 975                                           4 * j + 1, pdadcValues[4 * j + 1],
 976                                           4 * j + 2, pdadcValues[4 * j + 2],
 977                                           4 * j + 3,
 978                                           pdadcValues[4 * j + 3]);
 979
 980                                 regOffset += 4;
 981                         }
 982                 }
 983         }
 984
 985         *pTxPowerIndexOffset = 0;
 986 #undef SM_PD_GAIN
 987 #undef SM_PDGAIN_B
 988 }
 989
 990 static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
 991                                                   struct ath9k_channel *chan,
 992                                                   int16_t *ratesArray,
 993                                                   u16 cfgCtl,
 994                                                   u16 AntennaReduction,
 995                                                   u16 twiceMaxRegulatoryPower,
 996                                                   u16 powerLimit)
 997 {
 998 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */
 999 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN   9 /* 10*log10(3)*2 */
1000
1001         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1002         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1003         u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1004         static const u16 tpScaleReductionTable[5] =
1005                 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
1006
1007         int i;
1008         int16_t twiceLargestAntenna;
1009         struct cal_ctl_data *rep;
1010         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
1011                 0, { 0, 0, 0, 0}
1012         };
1013         struct cal_target_power_leg targetPowerOfdmExt = {
1014                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
1015                 0, { 0, 0, 0, 0 }
1016         };
1017         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
1018                 0, {0, 0, 0, 0}
1019         };
1020         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
1021         u16 ctlModesFor11a[] =
1022                 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
1023         u16 ctlModesFor11g[] =
1024                 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
1025                   CTL_2GHT40
1026                 };
1027         u16 numCtlModes, *pCtlMode, ctlMode, freq;
1028         struct chan_centers centers;
1029         int tx_chainmask;
1030         u16 twiceMinEdgePower;
1031
1032         tx_chainmask = ah->txchainmask;
1033
1034         ath9k_hw_get_channel_centers(ah, chan, &centers);
1035
1036         twiceLargestAntenna = max(
1037                 pEepData->modalHeader
1038                         [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
1039                 pEepData->modalHeader
1040                         [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
1041
1042         twiceLargestAntenna = max((u8)twiceLargestAntenna,
1043                                   pEepData->modalHeader
1044                                   [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
1045
1046         twiceLargestAntenna = (int16_t)min(AntennaReduction -
1047                                            twiceLargestAntenna, 0);
1048
1049         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
1050
1051         if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
1052                 maxRegAllowedPower -=
1053                         (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
1054         }
1055
1056         scaledPower = min(powerLimit, maxRegAllowedPower);
1057
1058         switch (ar5416_get_ntxchains(tx_chainmask)) {
1059         case 1:
1060                 break;
1061         case 2:
1062                 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
1063                 break;
1064         case 3:
1065                 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
1066                 break;
1067         }
1068
1069         scaledPower = max((u16)0, scaledPower);
1070
1071         if (IS_CHAN_2GHZ(chan)) {
1072                 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
1073                         SUB_NUM_CTL_MODES_AT_2G_40;
1074                 pCtlMode = ctlModesFor11g;
1075
1076                 ath9k_hw_get_legacy_target_powers(ah, chan,
1077                         pEepData->calTargetPowerCck,
1078                         AR5416_NUM_2G_CCK_TARGET_POWERS,
1079                         &targetPowerCck, 4, false);
1080                 ath9k_hw_get_legacy_target_powers(ah, chan,
1081                         pEepData->calTargetPower2G,
1082                         AR5416_NUM_2G_20_TARGET_POWERS,
1083                         &targetPowerOfdm, 4, false);
1084                 ath9k_hw_get_target_powers(ah, chan,
1085                         pEepData->calTargetPower2GHT20,
1086                         AR5416_NUM_2G_20_TARGET_POWERS,
1087                         &targetPowerHt20, 8, false);
1088
1089                 if (IS_CHAN_HT40(chan)) {
1090                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
1091                         ath9k_hw_get_target_powers(ah, chan,
1092                                 pEepData->calTargetPower2GHT40,
1093                                 AR5416_NUM_2G_40_TARGET_POWERS,
1094                                 &targetPowerHt40, 8, true);
1095                         ath9k_hw_get_legacy_target_powers(ah, chan,
1096                                 pEepData->calTargetPowerCck,
1097                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
1098                                 &targetPowerCckExt, 4, true);
1099                         ath9k_hw_get_legacy_target_powers(ah, chan,
1100                                 pEepData->calTargetPower2G,
1101                                 AR5416_NUM_2G_20_TARGET_POWERS,
1102                                 &targetPowerOfdmExt, 4, true);
1103                 }
1104         } else {
1105                 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
1106                         SUB_NUM_CTL_MODES_AT_5G_40;
1107                 pCtlMode = ctlModesFor11a;
1108
1109                 ath9k_hw_get_legacy_target_powers(ah, chan,
1110                         pEepData->calTargetPower5G,
1111                         AR5416_NUM_5G_20_TARGET_POWERS,
1112                         &targetPowerOfdm, 4, false);
1113                 ath9k_hw_get_target_powers(ah, chan,
1114                         pEepData->calTargetPower5GHT20,
1115                         AR5416_NUM_5G_20_TARGET_POWERS,
1116                         &targetPowerHt20, 8, false);
1117
1118                 if (IS_CHAN_HT40(chan)) {
1119                         numCtlModes = ARRAY_SIZE(ctlModesFor11a);
1120                         ath9k_hw_get_target_powers(ah, chan,
1121                                 pEepData->calTargetPower5GHT40,
1122                                 AR5416_NUM_5G_40_TARGET_POWERS,
1123                                 &targetPowerHt40, 8, true);
1124                         ath9k_hw_get_legacy_target_powers(ah, chan,
1125                                 pEepData->calTargetPower5G,
1126                                 AR5416_NUM_5G_20_TARGET_POWERS,
1127                                 &targetPowerOfdmExt, 4, true);
1128                 }
1129         }
1130
1131         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1132                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1133                         (pCtlMode[ctlMode] == CTL_2GHT40);
1134                 if (isHt40CtlMode)
1135                         freq = centers.synth_center;
1136                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
1137                         freq = centers.ext_center;
1138                 else
1139                         freq = centers.ctl_center;
1140
1141                 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
1142                     ah->eep_ops->get_eeprom_rev(ah) <= 2)
1143                         twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1144
1145                 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1146                         if ((((cfgCtl & ~CTL_MODE_M) |
1147                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1148                              pEepData->ctlIndex[i]) ||
1149                             (((cfgCtl & ~CTL_MODE_M) |
1150                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1151                              ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
1152                                 rep = &(pEepData->ctlData[i]);
1153
1154                                 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
1155                                 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
1156                                 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
1157
1158                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1159                                         twiceMaxEdgePower = min(twiceMaxEdgePower,
1160                                                                 twiceMinEdgePower);
1161                                 } else {
1162                                         twiceMaxEdgePower = twiceMinEdgePower;
1163                                         break;
1164                                 }
1165                         }
1166                 }
1167
1168                 minCtlPower = min(twiceMaxEdgePower, scaledPower);
1169
1170                 switch (pCtlMode[ctlMode]) {
1171                 case CTL_11B:
1172                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
1173                                 targetPowerCck.tPow2x[i] =
1174                                         min((u16)targetPowerCck.tPow2x[i],
1175                                             minCtlPower);
1176                         }
1177                         break;
1178                 case CTL_11A:
1179                 case CTL_11G:
1180                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
1181                                 targetPowerOfdm.tPow2x[i] =
1182                                         min((u16)targetPowerOfdm.tPow2x[i],
1183                                             minCtlPower);
1184                         }
1185                         break;
1186                 case CTL_5GHT20:
1187                 case CTL_2GHT20:
1188                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
1189                                 targetPowerHt20.tPow2x[i] =
1190                                         min((u16)targetPowerHt20.tPow2x[i],
1191                                             minCtlPower);
1192                         }
1193                         break;
1194                 case CTL_11B_EXT:
1195                         targetPowerCckExt.tPow2x[0] = min((u16)
1196                                         targetPowerCckExt.tPow2x[0],
1197                                         minCtlPower);
1198                         break;
1199                 case CTL_11A_EXT:
1200                 case CTL_11G_EXT:
1201                         targetPowerOfdmExt.tPow2x[0] = min((u16)
1202                                         targetPowerOfdmExt.tPow2x[0],
1203                                         minCtlPower);
1204                         break;
1205                 case CTL_5GHT40:
1206                 case CTL_2GHT40:
1207                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1208                                 targetPowerHt40.tPow2x[i] =
1209                                         min((u16)targetPowerHt40.tPow2x[i],
1210                                             minCtlPower);
1211                         }
1212                         break;
1213                 default:
1214                         break;
1215                 }
1216         }
1217
1218         ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1219                 ratesArray[rate18mb] = ratesArray[rate24mb] =
1220                 targetPowerOfdm.tPow2x[0];
1221         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1222         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1223         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1224         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1225
1226         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1227                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1228
1229         if (IS_CHAN_2GHZ(chan)) {
1230                 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1231                 ratesArray[rate2s] = ratesArray[rate2l] =
1232                         targetPowerCck.tPow2x[1];
1233                 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
1234                         targetPowerCck.tPow2x[2];
1235                 ratesArray[rate11s] = ratesArray[rate11l] =
1236                         targetPowerCck.tPow2x[3];
1237         }
1238         if (IS_CHAN_HT40(chan)) {
1239                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1240                         ratesArray[rateHt40_0 + i] =
1241                                 targetPowerHt40.tPow2x[i];
1242                 }
1243                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1244                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1245                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1246                 if (IS_CHAN_2GHZ(chan)) {
1247                         ratesArray[rateExtCck] =
1248                                 targetPowerCckExt.tPow2x[0];
1249                 }
1250         }
1251 }
1252
1253 static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1254                                     struct ath9k_channel *chan,
1255                                     u16 cfgCtl,
1256                                     u8 twiceAntennaReduction,
1257                                     u8 twiceMaxRegulatoryPower,
1258                                     u8 powerLimit)
1259 {
1260 #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
1261         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1262         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1263         struct modal_eep_header *pModal =
1264                 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
1265         int16_t ratesArray[Ar5416RateSize];
1266         int16_t txPowerIndexOffset = 0;
1267         u8 ht40PowerIncForPdadc = 2;
1268         int i, cck_ofdm_delta = 0;
1269
1270         memset(ratesArray, 0, sizeof(ratesArray));
1271
1272         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1273             AR5416_EEP_MINOR_VER_2) {
1274                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1275         }
1276
1277         ath9k_hw_set_def_power_per_rate_table(ah, chan,
1278                                                &ratesArray[0], cfgCtl,
1279                                                twiceAntennaReduction,
1280                                                twiceMaxRegulatoryPower,
1281                                                powerLimit);
1282
1283         ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset);
1284
1285         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1286                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1287                 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
1288                         ratesArray[i] = AR5416_MAX_RATE_POWER;
1289         }
1290
1291         if (AR_SREV_9280_10_OR_LATER(ah)) {
1292                 for (i = 0; i < Ar5416RateSize; i++) {
1293                         int8_t pwr_table_offset;
1294
1295                         pwr_table_offset = ah->eep_ops->get_eeprom(ah,
1296                                                         EEP_PWR_TABLE_OFFSET);
1297                         ratesArray[i] -= pwr_table_offset * 2;
1298                 }
1299         }
1300
1301         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1302                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
1303                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1304                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1305                   | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1306         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1307                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
1308                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1309                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1310                   | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1311
1312         if (IS_CHAN_2GHZ(chan)) {
1313                 if (OLC_FOR_AR9280_20_LATER) {
1314                         cck_ofdm_delta = 2;
1315                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1316                                 ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24)
1317                                 | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16)
1318                                 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1319                                 | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0));
1320                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1321                                 ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24)
1322                                 | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16)
1323                                 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8)
1324                                 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0));
1325                 } else {
1326                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1327                                 ATH9K_POW_SM(ratesArray[rate2s], 24)
1328                                 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1329                                 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1330                                 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1331                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1332                                 ATH9K_POW_SM(ratesArray[rate11s], 24)
1333                                 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1334                                 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1335                                 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1336                 }
1337         }
1338
1339         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1340                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1341                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1342                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1343                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1344         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1345                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1346                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1347                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1348                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1349
1350         if (IS_CHAN_HT40(chan)) {
1351                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1352                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
1353                                        ht40PowerIncForPdadc, 24)
1354                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1355                                          ht40PowerIncForPdadc, 16)
1356                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1357                                          ht40PowerIncForPdadc, 8)
1358                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1359                                          ht40PowerIncForPdadc, 0));
1360                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1361                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
1362                                        ht40PowerIncForPdadc, 24)
1363                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1364                                          ht40PowerIncForPdadc, 16)
1365                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1366                                          ht40PowerIncForPdadc, 8)
1367                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1368                                          ht40PowerIncForPdadc, 0));
1369                 if (OLC_FOR_AR9280_20_LATER) {
1370                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1371                                 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1372                                 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16)
1373                                 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1374                                 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0));
1375                 } else {
1376                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1377                                 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1378                                 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1379                                 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1380                                 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1381                 }
1382         }
1383
1384         REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1385                   ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1386                   | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
1387
1388         i = rate6mb;
1389
1390         if (IS_CHAN_HT40(chan))
1391                 i = rateHt40_0;
1392         else if (IS_CHAN_HT20(chan))
1393                 i = rateHt20_0;
1394
1395         if (AR_SREV_9280_10_OR_LATER(ah))
1396                 regulatory->max_power_level =
1397                         ratesArray[i] + AR5416_PWR_TABLE_OFFSET_DB * 2;
1398         else
1399                 regulatory->max_power_level = ratesArray[i];
1400
1401         switch(ar5416_get_ntxchains(ah->txchainmask)) {
1402         case 1:
1403                 break;
1404         case 2:
1405                 regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
1406                 break;
1407         case 3:
1408                 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
1409                 break;
1410         default:
1411                 ath_print(ath9k_hw_common(ah), ATH_DBG_EEPROM,
1412                           "Invalid chainmask configuration\n");
1413                 break;
1414         }
1415 }
1416
1417 static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
1418                                           enum ieee80211_band freq_band)
1419 {
1420         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1421         struct modal_eep_header *pModal =
1422                 &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]);
1423         struct base_eep_header *pBase = &eep->baseEepHeader;
1424         u8 num_ant_config;
1425
1426         num_ant_config = 1;
1427
1428         if (pBase->version >= 0x0E0D)
1429                 if (pModal->useAnt1)
1430                         num_ant_config += 1;
1431
1432         return num_ant_config;
1433 }
1434
1435 static u16 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah,
1436                                                struct ath9k_channel *chan)
1437 {
1438         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1439         struct modal_eep_header *pModal =
1440                 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1441
1442         return pModal->antCtrlCommon & 0xFFFF;
1443 }
1444
1445 static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1446 {
1447 #define EEP_DEF_SPURCHAN \
1448         (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
1449         struct ath_common *common = ath9k_hw_common(ah);
1450
1451         u16 spur_val = AR_NO_SPUR;
1452
1453         ath_print(common, ATH_DBG_ANI,
1454                   "Getting spur idx %d is2Ghz. %d val %x\n",
1455                   i, is2GHz, ah->config.spurchans[i][is2GHz]);
1456
1457         switch (ah->config.spurmode) {
1458         case SPUR_DISABLE:
1459                 break;
1460         case SPUR_ENABLE_IOCTL:
1461                 spur_val = ah->config.spurchans[i][is2GHz];
1462                 ath_print(common, ATH_DBG_ANI,
1463                           "Getting spur val from new loc. %d\n", spur_val);
1464                 break;
1465         case SPUR_ENABLE_EEPROM:
1466                 spur_val = EEP_DEF_SPURCHAN;
1467                 break;
1468         }
1469
1470         return spur_val;
1471
1472 #undef EEP_DEF_SPURCHAN
1473 }
1474
1475 const struct eeprom_ops eep_def_ops = {
1476         .check_eeprom           = ath9k_hw_def_check_eeprom,
1477         .get_eeprom             = ath9k_hw_def_get_eeprom,
1478         .fill_eeprom            = ath9k_hw_def_fill_eeprom,
1479         .get_eeprom_ver         = ath9k_hw_def_get_eeprom_ver,
1480         .get_eeprom_rev         = ath9k_hw_def_get_eeprom_rev,
1481         .get_num_ant_config     = ath9k_hw_def_get_num_ant_config,
1482         .get_eeprom_antenna_cfg = ath9k_hw_def_get_eeprom_antenna_cfg,
1483         .set_board_values       = ath9k_hw_def_set_board_values,
1484         .set_addac              = ath9k_hw_def_set_addac,
1485         .set_txpower            = ath9k_hw_def_set_txpower,
1486         .get_spur_channel       = ath9k_hw_def_get_spur_channel
1487 };