drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/slab.h>
  19 #include <asm/unaligned.h>
  20
  21 #include "hw.h"
  22 #include "hw-ops.h"
  23 #include "rc.h"
  24 #include "ar9003_mac.h"
  25
  26 #define ATH9K_CLOCK_RATE_CCK            22
  27 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  28 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  29 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
  30
  31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  32
  33 MODULE_AUTHOR("Atheros Communications");
  34 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  35 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  36 MODULE_LICENSE("Dual BSD/GPL");
  37
  38 static int __init ath9k_init(void)
  39 {
  40         return 0;
  41 }
  42 module_init(ath9k_init);
  43
  44 static void __exit ath9k_exit(void)
  45 {
  46         return;
  47 }
  48 module_exit(ath9k_exit);
  49
  50 /* Private hardware callbacks */
  51
  52 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
  53 {
  54         ath9k_hw_private_ops(ah)->init_cal_settings(ah);
  55 }
  56
  57 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
  58 {
  59         ath9k_hw_private_ops(ah)->init_mode_regs(ah);
  60 }
  61
  62 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
  63 {
  64         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
  65
  66         return priv_ops->macversion_supported(ah->hw_version.macVersion);
  67 }
  68
  69 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
  70                                         struct ath9k_channel *chan)
  71 {
  72         return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
  73 }
  74
  75 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
  76 {
  77         if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
  78                 return;
  79
  80         ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
  81 }
  82
  83 /********************/
  84 /* Helper Functions */
  85 /********************/
  86
  87 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  88 {
  89         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  90
  91         if (!ah->curchan) /* should really check for CCK instead */
  92                 return usecs *ATH9K_CLOCK_RATE_CCK;
  93         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  94                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  95
  96         if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
  97                 return usecs * ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
  98         else
  99                 return usecs * ATH9K_CLOCK_RATE_5GHZ_OFDM;
 100 }
 101
 102 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
 103 {
 104         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
 105
 106         if (conf_is_ht40(conf))
 107                 return ath9k_hw_mac_clks(ah, usecs) * 2;
 108         else
 109                 return ath9k_hw_mac_clks(ah, usecs);
 110 }
 111
 112 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 113 {
 114         int i;
 115
 116         BUG_ON(timeout < AH_TIME_QUANTUM);
 117
 118         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
 119                 if ((REG_READ(ah, reg) & mask) == val)
 120                         return true;
 121
 122                 udelay(AH_TIME_QUANTUM);
 123         }
 124
 125         ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
 126                   "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 127                   timeout, reg, REG_READ(ah, reg), mask, val);
 128
 129         return false;
 130 }
 131 EXPORT_SYMBOL(ath9k_hw_wait);
 132
 133 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 134 {
 135         u32 retval;
 136         int i;
 137
 138         for (i = 0, retval = 0; i < n; i++) {
 139                 retval = (retval << 1) | (val & 1);
 140                 val >>= 1;
 141         }
 142         return retval;
 143 }
 144
 145 bool ath9k_get_channel_edges(struct ath_hw *ah,
 146                              u16 flags, u16 *low,
 147                              u16 *high)
 148 {
 149         struct ath9k_hw_capabilities *pCap = &ah->caps;
 150
 151         if (flags & CHANNEL_5GHZ) {
 152                 *low = pCap->low_5ghz_chan;
 153                 *high = pCap->high_5ghz_chan;
 154                 return true;
 155         }
 156         if ((flags & CHANNEL_2GHZ)) {
 157                 *low = pCap->low_2ghz_chan;
 158                 *high = pCap->high_2ghz_chan;
 159                 return true;
 160         }
 161         return false;
 162 }
 163
 164 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 165                            u8 phy, int kbps,
 166                            u32 frameLen, u16 rateix,
 167                            bool shortPreamble)
 168 {
 169         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 170
 171         if (kbps == 0)
 172                 return 0;
 173
 174         switch (phy) {
 175         case WLAN_RC_PHY_CCK:
 176                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 177                 if (shortPreamble)
 178                         phyTime >>= 1;
 179                 numBits = frameLen << 3;
 180                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 181                 break;
 182         case WLAN_RC_PHY_OFDM:
 183                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 184                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 185                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 186                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 187                         txTime = OFDM_SIFS_TIME_QUARTER
 188                                 + OFDM_PREAMBLE_TIME_QUARTER
 189                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 190                 } else if (ah->curchan &&
 191                            IS_CHAN_HALF_RATE(ah->curchan)) {
 192                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 193                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 194                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 195                         txTime = OFDM_SIFS_TIME_HALF +
 196                                 OFDM_PREAMBLE_TIME_HALF
 197                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 198                 } else {
 199                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 200                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 201                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 202                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 203                                 + (numSymbols * OFDM_SYMBOL_TIME);
 204                 }
 205                 break;
 206         default:
 207                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 208                           "Unknown phy %u (rate ix %u)\n", phy, rateix);
 209                 txTime = 0;
 210                 break;
 211         }
 212
 213         return txTime;
 214 }
 215 EXPORT_SYMBOL(ath9k_hw_computetxtime);
 216
 217 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 218                                   struct ath9k_channel *chan,
 219                                   struct chan_centers *centers)
 220 {
 221         int8_t extoff;
 222
 223         if (!IS_CHAN_HT40(chan)) {
 224                 centers->ctl_center = centers->ext_center =
 225                         centers->synth_center = chan->channel;
 226                 return;
 227         }
 228
 229         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 230             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 231                 centers->synth_center =
 232                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 233                 extoff = 1;
 234         } else {
 235                 centers->synth_center =
 236                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 237                 extoff = -1;
 238         }
 239
 240         centers->ctl_center =
 241                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 242         /* 25 MHz spacing is supported by hw but not on upper layers */
 243         centers->ext_center =
 244                 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 245 }
 246
 247 /******************/
 248 /* Chip Revisions */
 249 /******************/
 250
 251 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 252 {
 253         u32 val;
 254
 255         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 256
 257         if (val == 0xFF) {
 258                 val = REG_READ(ah, AR_SREV);
 259                 ah->hw_version.macVersion =
 260                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 261                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 262                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 263         } else {
 264                 if (!AR_SREV_9100(ah))
 265                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 266
 267                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 268
 269                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 270                         ah->is_pciexpress = true;
 271         }
 272 }
 273
 274 /************************************/
 275 /* HW Attach, Detach, Init Routines */
 276 /************************************/
 277
 278 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 279 {
 280         if (AR_SREV_9100(ah))
 281                 return;
 282
 283         ENABLE_REGWRITE_BUFFER(ah);
 284
 285         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 286         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 287         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 288         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 289         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 290         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 291         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 292         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 293         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 294
 295         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 296
 297         REGWRITE_BUFFER_FLUSH(ah);
 298         DISABLE_REGWRITE_BUFFER(ah);
 299 }
 300
 301 /* This should work for all families including legacy */
 302 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 303 {
 304         struct ath_common *common = ath9k_hw_common(ah);
 305         u32 regAddr[2] = { AR_STA_ID0 };
 306         u32 regHold[2];
 307         u32 patternData[4] = { 0x55555555,
 308                                0xaaaaaaaa,
 309                                0x66666666,
 310                                0x99999999 };
 311         int i, j, loop_max;
 312
 313         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 314                 loop_max = 2;
 315                 regAddr[1] = AR_PHY_BASE + (8 << 2);
 316         } else
 317                 loop_max = 1;
 318
 319         for (i = 0; i < loop_max; i++) {
 320                 u32 addr = regAddr[i];
 321                 u32 wrData, rdData;
 322
 323                 regHold[i] = REG_READ(ah, addr);
 324                 for (j = 0; j < 0x100; j++) {
 325                         wrData = (j << 16) | j;
 326                         REG_WRITE(ah, addr, wrData);
 327                         rdData = REG_READ(ah, addr);
 328                         if (rdData != wrData) {
 329                                 ath_print(common, ATH_DBG_FATAL,
 330                                           "address test failed "
 331                                           "addr: 0x%08x - wr:0x%08x != "
 332                                           "rd:0x%08x\n",
 333                                           addr, wrData, rdData);
 334                                 return false;
 335                         }
 336                 }
 337                 for (j = 0; j < 4; j++) {
 338                         wrData = patternData[j];
 339                         REG_WRITE(ah, addr, wrData);
 340                         rdData = REG_READ(ah, addr);
 341                         if (wrData != rdData) {
 342                                 ath_print(common, ATH_DBG_FATAL,
 343                                           "address test failed "
 344                                           "addr: 0x%08x - wr:0x%08x != "
 345                                           "rd:0x%08x\n",
 346                                           addr, wrData, rdData);
 347                                 return false;
 348                         }
 349                 }
 350                 REG_WRITE(ah, regAddr[i], regHold[i]);
 351         }
 352         udelay(100);
 353
 354         return true;
 355 }
 356
 357 static void ath9k_hw_init_config(struct ath_hw *ah)
 358 {
 359         int i;
 360
 361         ah->config.dma_beacon_response_time = 2;
 362         ah->config.sw_beacon_response_time = 10;
 363         ah->config.additional_swba_backoff = 0;
 364         ah->config.ack_6mb = 0x0;
 365         ah->config.cwm_ignore_extcca = 0;
 366         ah->config.pcie_powersave_enable = 0;
 367         ah->config.pcie_clock_req = 0;
 368         ah->config.pcie_waen = 0;
 369         ah->config.analog_shiftreg = 1;
 370         ah->config.ofdm_trig_low = 200;
 371         ah->config.ofdm_trig_high = 500;
 372         ah->config.cck_trig_high = 200;
 373         ah->config.cck_trig_low = 100;
 374
 375         /*
 376          * For now ANI is disabled for AR9003, it is still
 377          * being tested.
 378          */
 379         if (!AR_SREV_9300_20_OR_LATER(ah))
 380                 ah->config.enable_ani = 1;
 381
 382         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 383                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 384                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 385         }
 386
 387         if (ah->hw_version.devid != AR2427_DEVID_PCIE)
 388                 ah->config.ht_enable = 1;
 389         else
 390                 ah->config.ht_enable = 0;
 391
 392         ah->config.rx_intr_mitigation = true;
 393
 394         /*
 395          * Tx IQ Calibration (ah->config.tx_iq_calibration) is only
 396          * used by AR9003, but it is showing reliability issues.
 397          * It will take a while to fix so this is currently disabled.
 398          */
 399
 400         /*
 401          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 402          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 403          * This means we use it for all AR5416 devices, and the few
 404          * minor PCI AR9280 devices out there.
 405          *
 406          * Serialization is required because these devices do not handle
 407          * well the case of two concurrent reads/writes due to the latency
 408          * involved. During one read/write another read/write can be issued
 409          * on another CPU while the previous read/write may still be working
 410          * on our hardware, if we hit this case the hardware poops in a loop.
 411          * We prevent this by serializing reads and writes.
 412          *
 413          * This issue is not present on PCI-Express devices or pre-AR5416
 414          * devices (legacy, 802.11abg).
 415          */
 416         if (num_possible_cpus() > 1)
 417                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 418 }
 419
 420 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 421 {
 422         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 423
 424         regulatory->country_code = CTRY_DEFAULT;
 425         regulatory->power_limit = MAX_RATE_POWER;
 426         regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
 427
 428         ah->hw_version.magic = AR5416_MAGIC;
 429         ah->hw_version.subvendorid = 0;
 430
 431         ah->ah_flags = 0;
 432         if (!AR_SREV_9100(ah))
 433                 ah->ah_flags = AH_USE_EEPROM;
 434
 435         ah->atim_window = 0;
 436         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 437         ah->beacon_interval = 100;
 438         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 439         ah->slottime = (u32) -1;
 440         ah->globaltxtimeout = (u32) -1;
 441         ah->power_mode = ATH9K_PM_UNDEFINED;
 442 }
 443
 444 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 445 {
 446         struct ath_common *common = ath9k_hw_common(ah);
 447         u32 sum;
 448         int i;
 449         u16 eeval;
 450         u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
 451
 452         sum = 0;
 453         for (i = 0; i < 3; i++) {
 454                 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
 455                 sum += eeval;
 456                 common->macaddr[2 * i] = eeval >> 8;
 457                 common->macaddr[2 * i + 1] = eeval & 0xff;
 458         }
 459         if (sum == 0 || sum == 0xffff * 3)
 460                 return -EADDRNOTAVAIL;
 461
 462         return 0;
 463 }
 464
 465 static int ath9k_hw_post_init(struct ath_hw *ah)
 466 {
 467         int ecode;
 468
 469         if (!AR_SREV_9271(ah)) {
 470                 if (!ath9k_hw_chip_test(ah))
 471                         return -ENODEV;
 472         }
 473
 474         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 475                 ecode = ar9002_hw_rf_claim(ah);
 476                 if (ecode != 0)
 477                         return ecode;
 478         }
 479
 480         ecode = ath9k_hw_eeprom_init(ah);
 481         if (ecode != 0)
 482                 return ecode;
 483
 484         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
 485                   "Eeprom VER: %d, REV: %d\n",
 486                   ah->eep_ops->get_eeprom_ver(ah),
 487                   ah->eep_ops->get_eeprom_rev(ah));
 488
 489         ecode = ath9k_hw_rf_alloc_ext_banks(ah);
 490         if (ecode) {
 491                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 492                           "Failed allocating banks for "
 493                           "external radio\n");
 494                 return ecode;
 495         }
 496
 497         if (!AR_SREV_9100(ah)) {
 498                 ath9k_hw_ani_setup(ah);
 499                 ath9k_hw_ani_init(ah);
 500         }
 501
 502         return 0;
 503 }
 504
 505 static void ath9k_hw_attach_ops(struct ath_hw *ah)
 506 {
 507         if (AR_SREV_9300_20_OR_LATER(ah))
 508                 ar9003_hw_attach_ops(ah);
 509         else
 510                 ar9002_hw_attach_ops(ah);
 511 }
 512
 513 /* Called for all hardware families */
 514 static int __ath9k_hw_init(struct ath_hw *ah)
 515 {
 516         struct ath_common *common = ath9k_hw_common(ah);
 517         int r = 0;
 518
 519         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 520                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 521
 522         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 523                 ath_print(common, ATH_DBG_FATAL,
 524                           "Couldn't reset chip\n");
 525                 return -EIO;
 526         }
 527
 528         ath9k_hw_init_defaults(ah);
 529         ath9k_hw_init_config(ah);
 530
 531         ath9k_hw_attach_ops(ah);
 532
 533         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 534                 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 535                 return -EIO;
 536         }
 537
 538         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 539                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 540                     ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
 541                      !ah->is_pciexpress)) {
 542                         ah->config.serialize_regmode =
 543                                 SER_REG_MODE_ON;
 544                 } else {
 545                         ah->config.serialize_regmode =
 546                                 SER_REG_MODE_OFF;
 547                 }
 548         }
 549
 550         ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
 551                 ah->config.serialize_regmode);
 552
 553         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 554                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
 555         else
 556                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
 557
 558         if (!ath9k_hw_macversion_supported(ah)) {
 559                 ath_print(common, ATH_DBG_FATAL,
 560                           "Mac Chip Rev 0x%02x.%x is not supported by "
 561                           "this driver\n", ah->hw_version.macVersion,
 562                           ah->hw_version.macRev);
 563                 return -EOPNOTSUPP;
 564         }
 565
 566         if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
 567                 ah->is_pciexpress = false;
 568
 569         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 570         ath9k_hw_init_cal_settings(ah);
 571
 572         ah->ani_function = ATH9K_ANI_ALL;
 573         if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
 574                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 575
 576         ath9k_hw_init_mode_regs(ah);
 577
 578         /*
 579          * Configire PCIE after Ini init. SERDES values now come from ini file
 580          * This enables PCIe low power mode.
 581          */
 582         if (AR_SREV_9300_20_OR_LATER(ah)) {
 583                 u32 regval;
 584                 unsigned int i;
 585
 586                 /* Set Bits 16 and 17 in the AR_WA register. */
 587                 regval = REG_READ(ah, AR_WA);
 588                 regval |= 0x00030000;
 589                 REG_WRITE(ah, AR_WA, regval);
 590
 591                 for (i = 0; i < ah->iniPcieSerdesLowPower.ia_rows; i++) {
 592                         REG_WRITE(ah,
 593                                   INI_RA(&ah->iniPcieSerdesLowPower, i, 0),
 594                                   INI_RA(&ah->iniPcieSerdesLowPower, i, 1));
 595                 }
 596         }
 597
 598         if (ah->is_pciexpress)
 599                 ath9k_hw_configpcipowersave(ah, 0, 0);
 600         else
 601                 ath9k_hw_disablepcie(ah);
 602
 603         if (!AR_SREV_9300_20_OR_LATER(ah))
 604                 ar9002_hw_cck_chan14_spread(ah);
 605
 606         r = ath9k_hw_post_init(ah);
 607         if (r)
 608                 return r;
 609
 610         ath9k_hw_init_mode_gain_regs(ah);
 611         r = ath9k_hw_fill_cap_info(ah);
 612         if (r)
 613                 return r;
 614
 615         r = ath9k_hw_init_macaddr(ah);
 616         if (r) {
 617                 ath_print(common, ATH_DBG_FATAL,
 618                           "Failed to initialize MAC address\n");
 619                 return r;
 620         }
 621
 622         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 623                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 624         else
 625                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 626
 627         if (AR_SREV_9300_20_OR_LATER(ah))
 628                 ar9003_hw_set_nf_limits(ah);
 629
 630         ath9k_init_nfcal_hist_buffer(ah);
 631
 632         common->state = ATH_HW_INITIALIZED;
 633
 634         return 0;
 635 }
 636
 637 int ath9k_hw_init(struct ath_hw *ah)
 638 {
 639         int ret;
 640         struct ath_common *common = ath9k_hw_common(ah);
 641
 642         /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
 643         switch (ah->hw_version.devid) {
 644         case AR5416_DEVID_PCI:
 645         case AR5416_DEVID_PCIE:
 646         case AR5416_AR9100_DEVID:
 647         case AR9160_DEVID_PCI:
 648         case AR9280_DEVID_PCI:
 649         case AR9280_DEVID_PCIE:
 650         case AR9285_DEVID_PCIE:
 651         case AR9287_DEVID_PCI:
 652         case AR9287_DEVID_PCIE:
 653         case AR2427_DEVID_PCIE:
 654         case AR9300_DEVID_PCIE:
 655                 break;
 656         default:
 657                 if (common->bus_ops->ath_bus_type == ATH_USB)
 658                         break;
 659                 ath_print(common, ATH_DBG_FATAL,
 660                           "Hardware device ID 0x%04x not supported\n",
 661                           ah->hw_version.devid);
 662                 return -EOPNOTSUPP;
 663         }
 664
 665         ret = __ath9k_hw_init(ah);
 666         if (ret) {
 667                 ath_print(common, ATH_DBG_FATAL,
 668                           "Unable to initialize hardware; "
 669                           "initialization status: %d\n", ret);
 670                 return ret;
 671         }
 672
 673         return 0;
 674 }
 675 EXPORT_SYMBOL(ath9k_hw_init);
 676
 677 static void ath9k_hw_init_qos(struct ath_hw *ah)
 678 {
 679         ENABLE_REGWRITE_BUFFER(ah);
 680
 681         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 682         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 683
 684         REG_WRITE(ah, AR_QOS_NO_ACK,
 685                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 686                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 687                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 688
 689         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 690         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 691         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 692         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 693         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 694
 695         REGWRITE_BUFFER_FLUSH(ah);
 696         DISABLE_REGWRITE_BUFFER(ah);
 697 }
 698
 699 static void ath9k_hw_init_pll(struct ath_hw *ah,
 700                               struct ath9k_channel *chan)
 701 {
 702         u32 pll = ath9k_hw_compute_pll_control(ah, chan);
 703
 704         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
 705
 706         /* Switch the core clock for ar9271 to 117Mhz */
 707         if (AR_SREV_9271(ah)) {
 708                 udelay(500);
 709                 REG_WRITE(ah, 0x50040, 0x304);
 710         }
 711
 712         udelay(RTC_PLL_SETTLE_DELAY);
 713
 714         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
 715 }
 716
 717 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
 718                                           enum nl80211_iftype opmode)
 719 {
 720         u32 imr_reg = AR_IMR_TXERR |
 721                 AR_IMR_TXURN |
 722                 AR_IMR_RXERR |
 723                 AR_IMR_RXORN |
 724                 AR_IMR_BCNMISC;
 725
 726         if (AR_SREV_9300_20_OR_LATER(ah)) {
 727                 imr_reg |= AR_IMR_RXOK_HP;
 728                 if (ah->config.rx_intr_mitigation)
 729                         imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 730                 else
 731                         imr_reg |= AR_IMR_RXOK_LP;
 732
 733         } else {
 734                 if (ah->config.rx_intr_mitigation)
 735                         imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 736                 else
 737                         imr_reg |= AR_IMR_RXOK;
 738         }
 739
 740         if (ah->config.tx_intr_mitigation)
 741                 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
 742         else
 743                 imr_reg |= AR_IMR_TXOK;
 744
 745         if (opmode == NL80211_IFTYPE_AP)
 746                 imr_reg |= AR_IMR_MIB;
 747
 748         ENABLE_REGWRITE_BUFFER(ah);
 749
 750         REG_WRITE(ah, AR_IMR, imr_reg);
 751         ah->imrs2_reg |= AR_IMR_S2_GTT;
 752         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
 753
 754         if (!AR_SREV_9100(ah)) {
 755                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
 756                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
 757                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
 758         }
 759
 760         REGWRITE_BUFFER_FLUSH(ah);
 761         DISABLE_REGWRITE_BUFFER(ah);
 762
 763         if (AR_SREV_9300_20_OR_LATER(ah)) {
 764                 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
 765                 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
 766                 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
 767                 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
 768         }
 769 }
 770
 771 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
 772 {
 773         u32 val = ath9k_hw_mac_to_clks(ah, us);
 774         val = min(val, (u32) 0xFFFF);
 775         REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
 776 }
 777
 778 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
 779 {
 780         u32 val = ath9k_hw_mac_to_clks(ah, us);
 781         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
 782         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
 783 }
 784
 785 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
 786 {
 787         u32 val = ath9k_hw_mac_to_clks(ah, us);
 788         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
 789         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
 790 }
 791
 792 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
 793 {
 794         if (tu > 0xFFFF) {
 795                 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
 796                           "bad global tx timeout %u\n", tu);
 797                 ah->globaltxtimeout = (u32) -1;
 798                 return false;
 799         } else {
 800                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
 801                 ah->globaltxtimeout = tu;
 802                 return true;
 803         }
 804 }
 805
 806 void ath9k_hw_init_global_settings(struct ath_hw *ah)
 807 {
 808         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
 809         int acktimeout;
 810         int slottime;
 811         int sifstime;
 812
 813         ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
 814                   ah->misc_mode);
 815
 816         if (ah->misc_mode != 0)
 817                 REG_WRITE(ah, AR_PCU_MISC,
 818                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
 819
 820         if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
 821                 sifstime = 16;
 822         else
 823                 sifstime = 10;
 824
 825         /* As defined by IEEE 802.11-2007 17.3.8.6 */
 826         slottime = ah->slottime + 3 * ah->coverage_class;
 827         acktimeout = slottime + sifstime;
 828
 829         /*
 830          * Workaround for early ACK timeouts, add an offset to match the
 831          * initval's 64us ack timeout value.
 832          * This was initially only meant to work around an issue with delayed
 833          * BA frames in some implementations, but it has been found to fix ACK
 834          * timeout issues in other cases as well.
 835          */
 836         if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
 837                 acktimeout += 64 - sifstime - ah->slottime;
 838
 839         ath9k_hw_setslottime(ah, slottime);
 840         ath9k_hw_set_ack_timeout(ah, acktimeout);
 841         ath9k_hw_set_cts_timeout(ah, acktimeout);
 842         if (ah->globaltxtimeout != (u32) -1)
 843                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
 844 }
 845 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
 846
 847 void ath9k_hw_deinit(struct ath_hw *ah)
 848 {
 849         struct ath_common *common = ath9k_hw_common(ah);
 850
 851         if (common->state < ATH_HW_INITIALIZED)
 852                 goto free_hw;
 853
 854         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
 855
 856 free_hw:
 857         ath9k_hw_rf_free_ext_banks(ah);
 858 }
 859 EXPORT_SYMBOL(ath9k_hw_deinit);
 860
 861 /*******/
 862 /* INI */
 863 /*******/
 864
 865 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
 866 {
 867         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
 868
 869         if (IS_CHAN_B(chan))
 870                 ctl |= CTL_11B;
 871         else if (IS_CHAN_G(chan))
 872                 ctl |= CTL_11G;
 873         else
 874                 ctl |= CTL_11A;
 875
 876         return ctl;
 877 }
 878
 879 /****************************************/
 880 /* Reset and Channel Switching Routines */
 881 /****************************************/
 882
 883 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
 884 {
 885         struct ath_common *common = ath9k_hw_common(ah);
 886         u32 regval;
 887
 888         ENABLE_REGWRITE_BUFFER(ah);
 889
 890         /*
 891          * set AHB_MODE not to do cacheline prefetches
 892         */
 893         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 894                 regval = REG_READ(ah, AR_AHB_MODE);
 895                 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
 896         }
 897
 898         /*
 899          * let mac dma reads be in 128 byte chunks
 900          */
 901         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
 902         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
 903
 904         REGWRITE_BUFFER_FLUSH(ah);
 905         DISABLE_REGWRITE_BUFFER(ah);
 906
 907         /*
 908          * Restore TX Trigger Level to its pre-reset value.
 909          * The initial value depends on whether aggregation is enabled, and is
 910          * adjusted whenever underruns are detected.
 911          */
 912         if (!AR_SREV_9300_20_OR_LATER(ah))
 913                 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
 914
 915         ENABLE_REGWRITE_BUFFER(ah);
 916
 917         /*
 918          * let mac dma writes be in 128 byte chunks
 919          */
 920         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
 921         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
 922
 923         /*
 924          * Setup receive FIFO threshold to hold off TX activities
 925          */
 926         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
 927
 928         if (AR_SREV_9300_20_OR_LATER(ah)) {
 929                 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
 930                 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
 931
 932                 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
 933                         ah->caps.rx_status_len);
 934         }
 935
 936         /*
 937          * reduce the number of usable entries in PCU TXBUF to avoid
 938          * wrap around issues.
 939          */
 940         if (AR_SREV_9285(ah)) {
 941                 /* For AR9285 the number of Fifos are reduced to half.
 942                  * So set the usable tx buf size also to half to
 943                  * avoid data/delimiter underruns
 944                  */
 945                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
 946                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
 947         } else if (!AR_SREV_9271(ah)) {
 948                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
 949                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
 950         }
 951
 952         REGWRITE_BUFFER_FLUSH(ah);
 953         DISABLE_REGWRITE_BUFFER(ah);
 954
 955         if (AR_SREV_9300_20_OR_LATER(ah))
 956                 ath9k_hw_reset_txstatus_ring(ah);
 957 }
 958
 959 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
 960 {
 961         u32 val;
 962
 963         val = REG_READ(ah, AR_STA_ID1);
 964         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
 965         switch (opmode) {
 966         case NL80211_IFTYPE_AP:
 967                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
 968                           | AR_STA_ID1_KSRCH_MODE);
 969                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 970                 break;
 971         case NL80211_IFTYPE_ADHOC:
 972         case NL80211_IFTYPE_MESH_POINT:
 973                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
 974                           | AR_STA_ID1_KSRCH_MODE);
 975                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 976                 break;
 977         case NL80211_IFTYPE_STATION:
 978         case NL80211_IFTYPE_MONITOR:
 979                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
 980                 break;
 981         }
 982 }
 983
 984 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
 985                                    u32 *coef_mantissa, u32 *coef_exponent)
 986 {
 987         u32 coef_exp, coef_man;
 988
 989         for (coef_exp = 31; coef_exp > 0; coef_exp--)
 990                 if ((coef_scaled >> coef_exp) & 0x1)
 991                         break;
 992
 993         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
 994
 995         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
 996
 997         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
 998         *coef_exponent = coef_exp - 16;
 999 }
1000
1001 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1002 {
1003         u32 rst_flags;
1004         u32 tmpReg;
1005
1006         if (AR_SREV_9100(ah)) {
1007                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1008                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1009                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1010                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1011                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1012         }
1013
1014         ENABLE_REGWRITE_BUFFER(ah);
1015
1016         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1017                   AR_RTC_FORCE_WAKE_ON_INT);
1018
1019         if (AR_SREV_9100(ah)) {
1020                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1021                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1022         } else {
1023                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1024                 if (tmpReg &
1025                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1026                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1027                         u32 val;
1028                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1029
1030                         val = AR_RC_HOSTIF;
1031                         if (!AR_SREV_9300_20_OR_LATER(ah))
1032                                 val |= AR_RC_AHB;
1033                         REG_WRITE(ah, AR_RC, val);
1034
1035                 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1036                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1037
1038                 rst_flags = AR_RTC_RC_MAC_WARM;
1039                 if (type == ATH9K_RESET_COLD)
1040                         rst_flags |= AR_RTC_RC_MAC_COLD;
1041         }
1042
1043         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1044
1045         REGWRITE_BUFFER_FLUSH(ah);
1046         DISABLE_REGWRITE_BUFFER(ah);
1047
1048         udelay(50);
1049
1050         REG_WRITE(ah, AR_RTC_RC, 0);
1051         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1052                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1053                           "RTC stuck in MAC reset\n");
1054                 return false;
1055         }
1056
1057         if (!AR_SREV_9100(ah))
1058                 REG_WRITE(ah, AR_RC, 0);
1059
1060         if (AR_SREV_9100(ah))
1061                 udelay(50);
1062
1063         return true;
1064 }
1065
1066 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1067 {
1068         ENABLE_REGWRITE_BUFFER(ah);
1069
1070         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1071                   AR_RTC_FORCE_WAKE_ON_INT);
1072
1073         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1074                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1075
1076         REG_WRITE(ah, AR_RTC_RESET, 0);
1077
1078         REGWRITE_BUFFER_FLUSH(ah);
1079         DISABLE_REGWRITE_BUFFER(ah);
1080
1081         if (!AR_SREV_9300_20_OR_LATER(ah))
1082                 udelay(2);
1083
1084         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1085                 REG_WRITE(ah, AR_RC, 0);
1086
1087         REG_WRITE(ah, AR_RTC_RESET, 1);
1088
1089         if (!ath9k_hw_wait(ah,
1090                            AR_RTC_STATUS,
1091                            AR_RTC_STATUS_M,
1092                            AR_RTC_STATUS_ON,
1093                            AH_WAIT_TIMEOUT)) {
1094                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1095                           "RTC not waking up\n");
1096                 return false;
1097         }
1098
1099         ath9k_hw_read_revisions(ah);
1100
1101         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1102 }
1103
1104 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1105 {
1106         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1107                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1108
1109         switch (type) {
1110         case ATH9K_RESET_POWER_ON:
1111                 return ath9k_hw_set_reset_power_on(ah);
1112         case ATH9K_RESET_WARM:
1113         case ATH9K_RESET_COLD:
1114                 return ath9k_hw_set_reset(ah, type);
1115         default:
1116                 return false;
1117         }
1118 }
1119
1120 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1121                                 struct ath9k_channel *chan)
1122 {
1123         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1124                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1125                         return false;
1126         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1127                 return false;
1128
1129         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1130                 return false;
1131
1132         ah->chip_fullsleep = false;
1133         ath9k_hw_init_pll(ah, chan);
1134         ath9k_hw_set_rfmode(ah, chan);
1135
1136         return true;
1137 }
1138
1139 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1140                                     struct ath9k_channel *chan)
1141 {
1142         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1143         struct ath_common *common = ath9k_hw_common(ah);
1144         struct ieee80211_channel *channel = chan->chan;
1145         u32 qnum;
1146         int r;
1147
1148         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1149                 if (ath9k_hw_numtxpending(ah, qnum)) {
1150                         ath_print(common, ATH_DBG_QUEUE,
1151                                   "Transmit frames pending on "
1152                                   "queue %d\n", qnum);
1153                         return false;
1154                 }
1155         }
1156
1157         if (!ath9k_hw_rfbus_req(ah)) {
1158                 ath_print(common, ATH_DBG_FATAL,
1159                           "Could not kill baseband RX\n");
1160                 return false;
1161         }
1162
1163         ath9k_hw_set_channel_regs(ah, chan);
1164
1165         r = ath9k_hw_rf_set_freq(ah, chan);
1166         if (r) {
1167                 ath_print(common, ATH_DBG_FATAL,
1168                           "Failed to set channel\n");
1169                 return false;
1170         }
1171
1172         ah->eep_ops->set_txpower(ah, chan,
1173                              ath9k_regd_get_ctl(regulatory, chan),
1174                              channel->max_antenna_gain * 2,
1175                              channel->max_power * 2,
1176                              min((u32) MAX_RATE_POWER,
1177                              (u32) regulatory->power_limit));
1178
1179         ath9k_hw_rfbus_done(ah);
1180
1181         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1182                 ath9k_hw_set_delta_slope(ah, chan);
1183
1184         ath9k_hw_spur_mitigate_freq(ah, chan);
1185
1186         if (!chan->oneTimeCalsDone)
1187                 chan->oneTimeCalsDone = true;
1188
1189         return true;
1190 }
1191
1192 bool ath9k_hw_check_alive(struct ath_hw *ah)
1193 {
1194         int count = 50;
1195         u32 reg;
1196
1197         if (AR_SREV_9285_10_OR_LATER(ah))
1198                 return true;
1199
1200         do {
1201                 reg = REG_READ(ah, AR_OBS_BUS_1);
1202
1203                 if ((reg & 0x7E7FFFEF) == 0x00702400)
1204                         continue;
1205
1206                 switch (reg & 0x7E000B00) {
1207                 case 0x1E000000:
1208                 case 0x52000B00:
1209                 case 0x18000B00:
1210                         continue;
1211                 default:
1212                         return true;
1213                 }
1214         } while (count-- > 0);
1215
1216         return false;
1217 }
1218 EXPORT_SYMBOL(ath9k_hw_check_alive);
1219
1220 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1221                     bool bChannelChange)
1222 {
1223         struct ath_common *common = ath9k_hw_common(ah);
1224         u32 saveLedState;
1225         struct ath9k_channel *curchan = ah->curchan;
1226         u32 saveDefAntenna;
1227         u32 macStaId1;
1228         u64 tsf = 0;
1229         int i, r;
1230
1231         ah->txchainmask = common->tx_chainmask;
1232         ah->rxchainmask = common->rx_chainmask;
1233
1234         if (!ah->chip_fullsleep) {
1235                 ath9k_hw_abortpcurecv(ah);
1236                 if (!ath9k_hw_stopdmarecv(ah))
1237                         ath_print(common, ATH_DBG_XMIT,
1238                                 "Failed to stop receive dma\n");
1239         }
1240
1241         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1242                 return -EIO;
1243
1244         if (curchan && !ah->chip_fullsleep)
1245                 ath9k_hw_getnf(ah, curchan);
1246
1247         if (bChannelChange &&
1248             (ah->chip_fullsleep != true) &&
1249             (ah->curchan != NULL) &&
1250             (chan->channel != ah->curchan->channel) &&
1251             ((chan->channelFlags & CHANNEL_ALL) ==
1252              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1253             !AR_SREV_9280(ah)) {
1254
1255                 if (ath9k_hw_channel_change(ah, chan)) {
1256                         ath9k_hw_loadnf(ah, ah->curchan);
1257                         ath9k_hw_start_nfcal(ah);
1258                         return 0;
1259                 }
1260         }
1261
1262         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1263         if (saveDefAntenna == 0)
1264                 saveDefAntenna = 1;
1265
1266         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1267
1268         /* For chips on which RTC reset is done, save TSF before it gets cleared */
1269         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1270                 tsf = ath9k_hw_gettsf64(ah);
1271
1272         saveLedState = REG_READ(ah, AR_CFG_LED) &
1273                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1274                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1275
1276         ath9k_hw_mark_phy_inactive(ah);
1277
1278         /* Only required on the first reset */
1279         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1280                 REG_WRITE(ah,
1281                           AR9271_RESET_POWER_DOWN_CONTROL,
1282                           AR9271_RADIO_RF_RST);
1283                 udelay(50);
1284         }
1285
1286         if (!ath9k_hw_chip_reset(ah, chan)) {
1287                 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1288                 return -EINVAL;
1289         }
1290
1291         /* Only required on the first reset */
1292         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1293                 ah->htc_reset_init = false;
1294                 REG_WRITE(ah,
1295                           AR9271_RESET_POWER_DOWN_CONTROL,
1296                           AR9271_GATE_MAC_CTL);
1297                 udelay(50);
1298         }
1299
1300         /* Restore TSF */
1301         if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1302                 ath9k_hw_settsf64(ah, tsf);
1303
1304         if (AR_SREV_9280_10_OR_LATER(ah))
1305                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1306
1307         r = ath9k_hw_process_ini(ah, chan);
1308         if (r)
1309                 return r;
1310
1311         /* Setup MFP options for CCMP */
1312         if (AR_SREV_9280_20_OR_LATER(ah)) {
1313                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1314                  * frames when constructing CCMP AAD. */
1315                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1316                               0xc7ff);
1317                 ah->sw_mgmt_crypto = false;
1318         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1319                 /* Disable hardware crypto for management frames */
1320                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1321                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1322                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1323                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1324                 ah->sw_mgmt_crypto = true;
1325         } else
1326                 ah->sw_mgmt_crypto = true;
1327
1328         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1329                 ath9k_hw_set_delta_slope(ah, chan);
1330
1331         ath9k_hw_spur_mitigate_freq(ah, chan);
1332         ah->eep_ops->set_board_values(ah, chan);
1333
1334         ath9k_hw_set_operating_mode(ah, ah->opmode);
1335
1336         ENABLE_REGWRITE_BUFFER(ah);
1337
1338         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1339         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1340                   | macStaId1
1341                   | AR_STA_ID1_RTS_USE_DEF
1342                   | (ah->config.
1343                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1344                   | ah->sta_id1_defaults);
1345         ath_hw_setbssidmask(common);
1346         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1347         ath9k_hw_write_associd(ah);
1348         REG_WRITE(ah, AR_ISR, ~0);
1349         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1350
1351         REGWRITE_BUFFER_FLUSH(ah);
1352         DISABLE_REGWRITE_BUFFER(ah);
1353
1354         r = ath9k_hw_rf_set_freq(ah, chan);
1355         if (r)
1356                 return r;
1357
1358         ENABLE_REGWRITE_BUFFER(ah);
1359
1360         for (i = 0; i < AR_NUM_DCU; i++)
1361                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1362
1363         REGWRITE_BUFFER_FLUSH(ah);
1364         DISABLE_REGWRITE_BUFFER(ah);
1365
1366         ah->intr_txqs = 0;
1367         for (i = 0; i < ah->caps.total_queues; i++)
1368                 ath9k_hw_resettxqueue(ah, i);
1369
1370         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1371         ath9k_hw_init_qos(ah);
1372
1373         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1374                 ath9k_enable_rfkill(ah);
1375
1376         ath9k_hw_init_global_settings(ah);
1377
1378         if (!AR_SREV_9300_20_OR_LATER(ah)) {
1379                 ar9002_hw_enable_async_fifo(ah);
1380                 ar9002_hw_enable_wep_aggregation(ah);
1381         }
1382
1383         REG_WRITE(ah, AR_STA_ID1,
1384                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1385
1386         ath9k_hw_set_dma(ah);
1387
1388         REG_WRITE(ah, AR_OBS, 8);
1389
1390         if (ah->config.rx_intr_mitigation) {
1391                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1392                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1393         }
1394
1395         if (ah->config.tx_intr_mitigation) {
1396                 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1397                 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1398         }
1399
1400         ath9k_hw_init_bb(ah, chan);
1401
1402         if (!ath9k_hw_init_cal(ah, chan))
1403                 return -EIO;
1404
1405         ENABLE_REGWRITE_BUFFER(ah);
1406
1407         ath9k_hw_restore_chainmask(ah);
1408         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1409
1410         REGWRITE_BUFFER_FLUSH(ah);
1411         DISABLE_REGWRITE_BUFFER(ah);
1412
1413         /*
1414          * For big endian systems turn on swapping for descriptors
1415          */
1416         if (AR_SREV_9100(ah)) {
1417                 u32 mask;
1418                 mask = REG_READ(ah, AR_CFG);
1419                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1420                         ath_print(common, ATH_DBG_RESET,
1421                                 "CFG Byte Swap Set 0x%x\n", mask);
1422                 } else {
1423                         mask =
1424                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1425                         REG_WRITE(ah, AR_CFG, mask);
1426                         ath_print(common, ATH_DBG_RESET,
1427                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1428                 }
1429         } else {
1430                 /* Configure AR9271 target WLAN */
1431                 if (AR_SREV_9271(ah))
1432                         REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1433 #ifdef __BIG_ENDIAN
1434                 else
1435                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1436 #endif
1437         }
1438
1439         if (ah->btcoex_hw.enabled)
1440                 ath9k_hw_btcoex_enable(ah);
1441
1442         if (AR_SREV_9300_20_OR_LATER(ah)) {
1443                 ath9k_hw_loadnf(ah, curchan);
1444                 ath9k_hw_start_nfcal(ah);
1445         }
1446
1447         return 0;
1448 }
1449 EXPORT_SYMBOL(ath9k_hw_reset);
1450
1451 /************************/
1452 /* Key Cache Management */
1453 /************************/
1454
1455 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1456 {
1457         u32 keyType;
1458
1459         if (entry >= ah->caps.keycache_size) {
1460                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1461                           "keychache entry %u out of range\n", entry);
1462                 return false;
1463         }
1464
1465         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
1466
1467         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1468         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1469         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1470         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1471         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1472         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1473         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1474         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1475
1476         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1477                 u16 micentry = entry + 64;
1478
1479                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1480                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1481                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1482                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1483
1484         }
1485
1486         return true;
1487 }
1488 EXPORT_SYMBOL(ath9k_hw_keyreset);
1489
1490 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1491 {
1492         u32 macHi, macLo;
1493
1494         if (entry >= ah->caps.keycache_size) {
1495                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1496                           "keychache entry %u out of range\n", entry);
1497                 return false;
1498         }
1499
1500         if (mac != NULL) {
1501                 macHi = (mac[5] << 8) | mac[4];
1502                 macLo = (mac[3] << 24) |
1503                         (mac[2] << 16) |
1504                         (mac[1] << 8) |
1505                         mac[0];
1506                 macLo >>= 1;
1507                 macLo |= (macHi & 1) << 31;
1508                 macHi >>= 1;
1509         } else {
1510                 macLo = macHi = 0;
1511         }
1512         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1513         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
1514
1515         return true;
1516 }
1517 EXPORT_SYMBOL(ath9k_hw_keysetmac);
1518
1519 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
1520                                  const struct ath9k_keyval *k,
1521                                  const u8 *mac)
1522 {
1523         const struct ath9k_hw_capabilities *pCap = &ah->caps;
1524         struct ath_common *common = ath9k_hw_common(ah);
1525         u32 key0, key1, key2, key3, key4;
1526         u32 keyType;
1527
1528         if (entry >= pCap->keycache_size) {
1529                 ath_print(common, ATH_DBG_FATAL,
1530                           "keycache entry %u out of range\n", entry);
1531                 return false;
1532         }
1533
1534         switch (k->kv_type) {
1535         case ATH9K_CIPHER_AES_OCB:
1536                 keyType = AR_KEYTABLE_TYPE_AES;
1537                 break;
1538         case ATH9K_CIPHER_AES_CCM:
1539                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1540                         ath_print(common, ATH_DBG_ANY,
1541                                   "AES-CCM not supported by mac rev 0x%x\n",
1542                                   ah->hw_version.macRev);
1543                         return false;
1544                 }
1545                 keyType = AR_KEYTABLE_TYPE_CCM;
1546                 break;
1547         case ATH9K_CIPHER_TKIP:
1548                 keyType = AR_KEYTABLE_TYPE_TKIP;
1549                 if (ATH9K_IS_MIC_ENABLED(ah)
1550                     && entry + 64 >= pCap->keycache_size) {
1551                         ath_print(common, ATH_DBG_ANY,
1552                                   "entry %u inappropriate for TKIP\n", entry);
1553                         return false;
1554                 }
1555                 break;
1556         case ATH9K_CIPHER_WEP:
1557                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1558                         ath_print(common, ATH_DBG_ANY,
1559                                   "WEP key length %u too small\n", k->kv_len);
1560                         return false;
1561                 }
1562                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
1563                         keyType = AR_KEYTABLE_TYPE_40;
1564                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1565                         keyType = AR_KEYTABLE_TYPE_104;
1566                 else
1567                         keyType = AR_KEYTABLE_TYPE_128;
1568                 break;
1569         case ATH9K_CIPHER_CLR:
1570                 keyType = AR_KEYTABLE_TYPE_CLR;
1571                 break;
1572         default:
1573                 ath_print(common, ATH_DBG_FATAL,
1574                           "cipher %u not supported\n", k->kv_type);
1575                 return false;
1576         }
1577
1578         key0 = get_unaligned_le32(k->kv_val + 0);
1579         key1 = get_unaligned_le16(k->kv_val + 4);
1580         key2 = get_unaligned_le32(k->kv_val + 6);
1581         key3 = get_unaligned_le16(k->kv_val + 10);
1582         key4 = get_unaligned_le32(k->kv_val + 12);
1583         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1584                 key4 &= 0xff;
1585
1586         /*
1587          * Note: Key cache registers access special memory area that requires
1588          * two 32-bit writes to actually update the values in the internal
1589          * memory. Consequently, the exact order and pairs used here must be
1590          * maintained.
1591          */
1592
1593         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1594                 u16 micentry = entry + 64;
1595
1596                 /*
1597                  * Write inverted key[47:0] first to avoid Michael MIC errors
1598                  * on frames that could be sent or received at the same time.
1599                  * The correct key will be written in the end once everything
1600                  * else is ready.
1601                  */
1602                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1603                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1604
1605                 /* Write key[95:48] */
1606                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1607                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1608
1609                 /* Write key[127:96] and key type */
1610                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1611                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1612
1613                 /* Write MAC address for the entry */
1614                 (void) ath9k_hw_keysetmac(ah, entry, mac);
1615
1616                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1617                         /*
1618                          * TKIP uses two key cache entries:
1619                          * Michael MIC TX/RX keys in the same key cache entry
1620                          * (idx = main index + 64):
1621                          * key0 [31:0] = RX key [31:0]
1622                          * key1 [15:0] = TX key [31:16]
1623                          * key1 [31:16] = reserved
1624                          * key2 [31:0] = RX key [63:32]
1625                          * key3 [15:0] = TX key [15:0]
1626                          * key3 [31:16] = reserved
1627                          * key4 [31:0] = TX key [63:32]
1628                          */
1629                         u32 mic0, mic1, mic2, mic3, mic4;
1630
1631                         mic0 = get_unaligned_le32(k->kv_mic + 0);
1632                         mic2 = get_unaligned_le32(k->kv_mic + 4);
1633                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1634                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1635                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
1636
1637                         /* Write RX[31:0] and TX[31:16] */
1638                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1639                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1640
1641                         /* Write RX[63:32] and TX[15:0] */
1642                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1643                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1644
1645                         /* Write TX[63:32] and keyType(reserved) */
1646                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1647                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1648                                   AR_KEYTABLE_TYPE_CLR);
1649
1650                 } else {
1651                         /*
1652                          * TKIP uses four key cache entries (two for group
1653                          * keys):
1654                          * Michael MIC TX/RX keys are in different key cache
1655                          * entries (idx = main index + 64 for TX and
1656                          * main index + 32 + 96 for RX):
1657                          * key0 [31:0] = TX/RX MIC key [31:0]
1658                          * key1 [31:0] = reserved
1659                          * key2 [31:0] = TX/RX MIC key [63:32]
1660                          * key3 [31:0] = reserved
1661                          * key4 [31:0] = reserved
1662                          *
1663                          * Upper layer code will call this function separately
1664                          * for TX and RX keys when these registers offsets are
1665                          * used.
1666                          */
1667                         u32 mic0, mic2;
1668
1669                         mic0 = get_unaligned_le32(k->kv_mic + 0);
1670                         mic2 = get_unaligned_le32(k->kv_mic + 4);
1671
1672                         /* Write MIC key[31:0] */
1673                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1674                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1675
1676                         /* Write MIC key[63:32] */
1677                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1678                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1679
1680                         /* Write TX[63:32] and keyType(reserved) */
1681                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1682                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1683                                   AR_KEYTABLE_TYPE_CLR);
1684                 }
1685
1686                 /* MAC address registers are reserved for the MIC entry */
1687                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1688                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
1689
1690                 /*
1691                  * Write the correct (un-inverted) key[47:0] last to enable
1692                  * TKIP now that all other registers are set with correct
1693                  * values.
1694                  */
1695                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1696                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1697         } else {
1698                 /* Write key[47:0] */
1699                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1700                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1701
1702                 /* Write key[95:48] */
1703                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1704                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1705
1706                 /* Write key[127:96] and key type */
1707                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1708                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1709
1710                 /* Write MAC address for the entry */
1711                 (void) ath9k_hw_keysetmac(ah, entry, mac);
1712         }
1713
1714         return true;
1715 }
1716 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
1717
1718 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
1719 {
1720         if (entry < ah->caps.keycache_size) {
1721                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1722                 if (val & AR_KEYTABLE_VALID)
1723                         return true;
1724         }
1725         return false;
1726 }
1727 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
1728
1729 /******************************/
1730 /* Power Management (Chipset) */
1731 /******************************/
1732
1733 /*
1734  * Notify Power Mgt is disabled in self-generated frames.
1735  * If requested, force chip to sleep.
1736  */
1737 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1738 {
1739         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1740         if (setChip) {
1741                 /*
1742                  * Clear the RTC force wake bit to allow the
1743                  * mac to go to sleep.
1744                  */
1745                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1746                             AR_RTC_FORCE_WAKE_EN);
1747                 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1748                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1749
1750                 /* Shutdown chip. Active low */
1751                 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1752                         REG_CLR_BIT(ah, (AR_RTC_RESET),
1753                                     AR_RTC_RESET_EN);
1754         }
1755 }
1756
1757 /*
1758  * Notify Power Management is enabled in self-generating
1759  * frames. If request, set power mode of chip to
1760  * auto/normal.  Duration in units of 128us (1/8 TU).
1761  */
1762 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1763 {
1764         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1765         if (setChip) {
1766                 struct ath9k_hw_capabilities *pCap = &ah->caps;
1767
1768                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1769                         /* Set WakeOnInterrupt bit; clear ForceWake bit */
1770                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1771                                   AR_RTC_FORCE_WAKE_ON_INT);
1772                 } else {
1773                         /*
1774                          * Clear the RTC force wake bit to allow the
1775                          * mac to go to sleep.
1776                          */
1777                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1778                                     AR_RTC_FORCE_WAKE_EN);
1779                 }
1780         }
1781 }
1782
1783 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1784 {
1785         u32 val;
1786         int i;
1787
1788         if (setChip) {
1789                 if ((REG_READ(ah, AR_RTC_STATUS) &
1790                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1791                         if (ath9k_hw_set_reset_reg(ah,
1792                                            ATH9K_RESET_POWER_ON) != true) {
1793                                 return false;
1794                         }
1795                         if (!AR_SREV_9300_20_OR_LATER(ah))
1796                                 ath9k_hw_init_pll(ah, NULL);
1797                 }
1798                 if (AR_SREV_9100(ah))
1799                         REG_SET_BIT(ah, AR_RTC_RESET,
1800                                     AR_RTC_RESET_EN);
1801
1802                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1803                             AR_RTC_FORCE_WAKE_EN);
1804                 udelay(50);
1805
1806                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1807                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1808                         if (val == AR_RTC_STATUS_ON)
1809                                 break;
1810                         udelay(50);
1811                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1812                                     AR_RTC_FORCE_WAKE_EN);
1813                 }
1814                 if (i == 0) {
1815                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1816                                   "Failed to wakeup in %uus\n",
1817                                   POWER_UP_TIME / 20);
1818                         return false;
1819                 }
1820         }
1821
1822         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1823
1824         return true;
1825 }
1826
1827 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1828 {
1829         struct ath_common *common = ath9k_hw_common(ah);
1830         int status = true, setChip = true;
1831         static const char *modes[] = {
1832                 "AWAKE",
1833                 "FULL-SLEEP",
1834                 "NETWORK SLEEP",
1835                 "UNDEFINED"
1836         };
1837
1838         if (ah->power_mode == mode)
1839                 return status;
1840
1841         ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1842                   modes[ah->power_mode], modes[mode]);
1843
1844         switch (mode) {
1845         case ATH9K_PM_AWAKE:
1846                 status = ath9k_hw_set_power_awake(ah, setChip);
1847                 break;
1848         case ATH9K_PM_FULL_SLEEP:
1849                 ath9k_set_power_sleep(ah, setChip);
1850                 ah->chip_fullsleep = true;
1851                 break;
1852         case ATH9K_PM_NETWORK_SLEEP:
1853                 ath9k_set_power_network_sleep(ah, setChip);
1854                 break;
1855         default:
1856                 ath_print(common, ATH_DBG_FATAL,
1857                           "Unknown power mode %u\n", mode);
1858                 return false;
1859         }
1860         ah->power_mode = mode;
1861
1862         return status;
1863 }
1864 EXPORT_SYMBOL(ath9k_hw_setpower);
1865
1866 /*******************/
1867 /* Beacon Handling */
1868 /*******************/
1869
1870 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1871 {
1872         int flags = 0;
1873
1874         ah->beacon_interval = beacon_period;
1875
1876         ENABLE_REGWRITE_BUFFER(ah);
1877
1878         switch (ah->opmode) {
1879         case NL80211_IFTYPE_STATION:
1880         case NL80211_IFTYPE_MONITOR:
1881                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1882                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1883                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1884                 flags |= AR_TBTT_TIMER_EN;
1885                 break;
1886         case NL80211_IFTYPE_ADHOC:
1887         case NL80211_IFTYPE_MESH_POINT:
1888                 REG_SET_BIT(ah, AR_TXCFG,
1889                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1890                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1891                           TU_TO_USEC(next_beacon +
1892                                      (ah->atim_window ? ah->
1893                                       atim_window : 1)));
1894                 flags |= AR_NDP_TIMER_EN;
1895         case NL80211_IFTYPE_AP:
1896                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1897                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1898                           TU_TO_USEC(next_beacon -
1899                                      ah->config.
1900                                      dma_beacon_response_time));
1901                 REG_WRITE(ah, AR_NEXT_SWBA,
1902                           TU_TO_USEC(next_beacon -
1903                                      ah->config.
1904                                      sw_beacon_response_time));
1905                 flags |=
1906                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1907                 break;
1908         default:
1909                 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1910                           "%s: unsupported opmode: %d\n",
1911                           __func__, ah->opmode);
1912                 return;
1913                 break;
1914         }
1915
1916         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1917         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1918         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1919         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1920
1921         REGWRITE_BUFFER_FLUSH(ah);
1922         DISABLE_REGWRITE_BUFFER(ah);
1923
1924         beacon_period &= ~ATH9K_BEACON_ENA;
1925         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1926                 ath9k_hw_reset_tsf(ah);
1927         }
1928
1929         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1930 }
1931 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1932
1933 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1934                                     const struct ath9k_beacon_state *bs)
1935 {
1936         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1937         struct ath9k_hw_capabilities *pCap = &ah->caps;
1938         struct ath_common *common = ath9k_hw_common(ah);
1939
1940         ENABLE_REGWRITE_BUFFER(ah);
1941
1942         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1943
1944         REG_WRITE(ah, AR_BEACON_PERIOD,
1945                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1946         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1947                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1948
1949         REGWRITE_BUFFER_FLUSH(ah);
1950         DISABLE_REGWRITE_BUFFER(ah);
1951
1952         REG_RMW_FIELD(ah, AR_RSSI_THR,
1953                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1954
1955         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1956
1957         if (bs->bs_sleepduration > beaconintval)
1958                 beaconintval = bs->bs_sleepduration;
1959
1960         dtimperiod = bs->bs_dtimperiod;
1961         if (bs->bs_sleepduration > dtimperiod)
1962                 dtimperiod = bs->bs_sleepduration;
1963
1964         if (beaconintval == dtimperiod)
1965                 nextTbtt = bs->bs_nextdtim;
1966         else
1967                 nextTbtt = bs->bs_nexttbtt;
1968
1969         ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1970         ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1971         ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1972         ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1973
1974         ENABLE_REGWRITE_BUFFER(ah);
1975
1976         REG_WRITE(ah, AR_NEXT_DTIM,
1977                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1978         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1979
1980         REG_WRITE(ah, AR_SLEEP1,
1981                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1982                   | AR_SLEEP1_ASSUME_DTIM);
1983
1984         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1985                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1986         else
1987                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1988
1989         REG_WRITE(ah, AR_SLEEP2,
1990                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1991
1992         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1993         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1994
1995         REGWRITE_BUFFER_FLUSH(ah);
1996         DISABLE_REGWRITE_BUFFER(ah);
1997
1998         REG_SET_BIT(ah, AR_TIMER_MODE,
1999                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2000                     AR_DTIM_TIMER_EN);
2001
2002         /* TSF Out of Range Threshold */
2003         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2004 }
2005 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2006
2007 /*******************/
2008 /* HW Capabilities */
2009 /*******************/
2010
2011 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2012 {
2013         struct ath9k_hw_capabilities *pCap = &ah->caps;
2014         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2015         struct ath_common *common = ath9k_hw_common(ah);
2016         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
2017
2018         u16 capField = 0, eeval;
2019
2020         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2021         regulatory->current_rd = eeval;
2022
2023         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
2024         if (AR_SREV_9285_10_OR_LATER(ah))
2025                 eeval |= AR9285_RDEXT_DEFAULT;
2026         regulatory->current_rd_ext = eeval;
2027
2028         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
2029
2030         if (ah->opmode != NL80211_IFTYPE_AP &&
2031             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2032                 if (regulatory->current_rd == 0x64 ||
2033                     regulatory->current_rd == 0x65)
2034                         regulatory->current_rd += 5;
2035                 else if (regulatory->current_rd == 0x41)
2036                         regulatory->current_rd = 0x43;
2037                 ath_print(common, ATH_DBG_REGULATORY,
2038                           "regdomain mapped to 0x%x\n", regulatory->current_rd);
2039         }
2040
2041         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2042         if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2043                 ath_print(common, ATH_DBG_FATAL,
2044                           "no band has been marked as supported in EEPROM.\n");
2045                 return -EINVAL;
2046         }
2047
2048         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2049
2050         if (eeval & AR5416_OPFLAGS_11A) {
2051                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2052                 if (ah->config.ht_enable) {
2053                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2054                                 set_bit(ATH9K_MODE_11NA_HT20,
2055                                         pCap->wireless_modes);
2056                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2057                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2058                                         pCap->wireless_modes);
2059                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2060                                         pCap->wireless_modes);
2061                         }
2062                 }
2063         }
2064
2065         if (eeval & AR5416_OPFLAGS_11G) {
2066                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2067                 if (ah->config.ht_enable) {
2068                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2069                                 set_bit(ATH9K_MODE_11NG_HT20,
2070                                         pCap->wireless_modes);
2071                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2072                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2073                                         pCap->wireless_modes);
2074                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2075                                         pCap->wireless_modes);
2076                         }
2077                 }
2078         }
2079
2080         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2081         /*
2082          * For AR9271 we will temporarilly uses the rx chainmax as read from
2083          * the EEPROM.
2084          */
2085         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2086             !(eeval & AR5416_OPFLAGS_11A) &&
2087             !(AR_SREV_9271(ah)))
2088                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2089                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2090         else
2091                 /* Use rx_chainmask from EEPROM. */
2092                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2093
2094         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2095                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2096
2097         pCap->low_2ghz_chan = 2312;
2098         pCap->high_2ghz_chan = 2732;
2099
2100         pCap->low_5ghz_chan = 4920;
2101         pCap->high_5ghz_chan = 6100;
2102
2103         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2104         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2105         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
2106
2107         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2108         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2109         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
2110
2111         if (ah->config.ht_enable)
2112                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2113         else
2114                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2115
2116         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2117         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2118         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2119         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
2120
2121         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2122                 pCap->total_queues =
2123                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2124         else
2125                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
2126
2127         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2128                 pCap->keycache_size =
2129                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2130         else
2131                 pCap->keycache_size = AR_KEYTABLE_SIZE;
2132
2133         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2134
2135         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2136                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2137         else
2138                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2139
2140         if (AR_SREV_9271(ah))
2141                 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2142         else if (AR_SREV_9285_10_OR_LATER(ah))
2143                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2144         else if (AR_SREV_9280_10_OR_LATER(ah))
2145                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2146         else
2147                 pCap->num_gpio_pins = AR_NUM_GPIO;
2148
2149         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2150                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2151                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2152         } else {
2153                 pCap->rts_aggr_limit = (8 * 1024);
2154         }
2155
2156         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2157
2158 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2159         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2160         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2161                 ah->rfkill_gpio =
2162                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2163                 ah->rfkill_polarity =
2164                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2165
2166                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2167         }
2168 #endif
2169         if (AR_SREV_9271(ah))
2170                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2171         else
2172                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2173
2174         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2175                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2176         else
2177                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2178
2179         if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2180                 pCap->reg_cap =
2181                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2182                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2183                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
2184                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2185         } else {
2186                 pCap->reg_cap =
2187                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2188                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2189         }
2190
2191         /* Advertise midband for AR5416 with FCC midband set in eeprom */
2192         if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2193             AR_SREV_5416(ah))
2194                 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2195
2196         pCap->num_antcfg_5ghz =
2197                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
2198         pCap->num_antcfg_2ghz =
2199                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2200
2201         if (AR_SREV_9280_10_OR_LATER(ah) &&
2202             ath9k_hw_btcoex_supported(ah)) {
2203                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2204                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2205
2206                 if (AR_SREV_9285(ah)) {
2207                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2208                         btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
2209                 } else {
2210                         btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2211                 }
2212         } else {
2213                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2214         }
2215
2216         if (AR_SREV_9300_20_OR_LATER(ah)) {
2217                 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
2218                                  ATH9K_HW_CAP_FASTCLOCK;
2219                 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2220                 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2221                 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2222                 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2223                 pCap->txs_len = sizeof(struct ar9003_txs);
2224         } else {
2225                 pCap->tx_desc_len = sizeof(struct ath_desc);
2226                 if (AR_SREV_9280_20(ah) &&
2227                     ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
2228                       AR5416_EEP_MINOR_VER_16) ||
2229                      ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
2230                         pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2231         }
2232
2233         if (AR_SREV_9300_20_OR_LATER(ah))
2234                 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2235
2236         return 0;
2237 }
2238
2239 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2240                             u32 capability, u32 *result)
2241 {
2242         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2243         switch (type) {
2244         case ATH9K_CAP_CIPHER:
2245                 switch (capability) {
2246                 case ATH9K_CIPHER_AES_CCM:
2247                 case ATH9K_CIPHER_AES_OCB:
2248                 case ATH9K_CIPHER_TKIP:
2249                 case ATH9K_CIPHER_WEP:
2250                 case ATH9K_CIPHER_MIC:
2251                 case ATH9K_CIPHER_CLR:
2252                         return true;
2253                 default:
2254                         return false;
2255                 }
2256         case ATH9K_CAP_TKIP_MIC:
2257                 switch (capability) {
2258                 case 0:
2259                         return true;
2260                 case 1:
2261                         return (ah->sta_id1_defaults &
2262                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2263                         false;
2264                 }
2265         case ATH9K_CAP_TKIP_SPLIT:
2266                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
2267                         false : true;
2268         case ATH9K_CAP_MCAST_KEYSRCH:
2269                 switch (capability) {
2270                 case 0:
2271                         return true;
2272                 case 1:
2273                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2274                                 return false;
2275                         } else {
2276                                 return (ah->sta_id1_defaults &
2277                                         AR_STA_ID1_MCAST_KSRCH) ? true :
2278                                         false;
2279                         }
2280                 }
2281                 return false;
2282         case ATH9K_CAP_TXPOW:
2283                 switch (capability) {
2284                 case 0:
2285                         return 0;
2286                 case 1:
2287                         *result = regulatory->power_limit;
2288                         return 0;
2289                 case 2:
2290                         *result = regulatory->max_power_level;
2291                         return 0;
2292                 case 3:
2293                         *result = regulatory->tp_scale;
2294                         return 0;
2295                 }
2296                 return false;
2297         case ATH9K_CAP_DS:
2298                 return (AR_SREV_9280_20_OR_LATER(ah) &&
2299                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2300                         ? false : true;
2301         default:
2302                 return false;
2303         }
2304 }
2305 EXPORT_SYMBOL(ath9k_hw_getcapability);
2306
2307 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2308                             u32 capability, u32 setting, int *status)
2309 {
2310         switch (type) {
2311         case ATH9K_CAP_TKIP_MIC:
2312                 if (setting)
2313                         ah->sta_id1_defaults |=
2314                                 AR_STA_ID1_CRPT_MIC_ENABLE;
2315                 else
2316                         ah->sta_id1_defaults &=
2317                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2318                 return true;
2319         case ATH9K_CAP_MCAST_KEYSRCH:
2320                 if (setting)
2321                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
2322                 else
2323                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
2324                 return true;
2325         default:
2326                 return false;
2327         }
2328 }
2329 EXPORT_SYMBOL(ath9k_hw_setcapability);
2330
2331 /****************************/
2332 /* GPIO / RFKILL / Antennae */
2333 /****************************/
2334
2335 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2336                                          u32 gpio, u32 type)
2337 {
2338         int addr;
2339         u32 gpio_shift, tmp;
2340
2341         if (gpio > 11)
2342                 addr = AR_GPIO_OUTPUT_MUX3;
2343         else if (gpio > 5)
2344                 addr = AR_GPIO_OUTPUT_MUX2;
2345         else
2346                 addr = AR_GPIO_OUTPUT_MUX1;
2347
2348         gpio_shift = (gpio % 6) * 5;
2349
2350         if (AR_SREV_9280_20_OR_LATER(ah)
2351             || (addr != AR_GPIO_OUTPUT_MUX1)) {
2352                 REG_RMW(ah, addr, (type << gpio_shift),
2353                         (0x1f << gpio_shift));
2354         } else {
2355                 tmp = REG_READ(ah, addr);
2356                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2357                 tmp &= ~(0x1f << gpio_shift);
2358                 tmp |= (type << gpio_shift);
2359                 REG_WRITE(ah, addr, tmp);
2360         }
2361 }
2362
2363 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2364 {
2365         u32 gpio_shift;
2366
2367         BUG_ON(gpio >= ah->caps.num_gpio_pins);
2368
2369         gpio_shift = gpio << 1;
2370
2371         REG_RMW(ah,
2372                 AR_GPIO_OE_OUT,
2373                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2374                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2375 }
2376 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2377
2378 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2379 {
2380 #define MS_REG_READ(x, y) \
2381         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2382
2383         if (gpio >= ah->caps.num_gpio_pins)
2384                 return 0xffffffff;
2385
2386         if (AR_SREV_9300_20_OR_LATER(ah))
2387                 return MS_REG_READ(AR9300, gpio) != 0;
2388         else if (AR_SREV_9271(ah))
2389                 return MS_REG_READ(AR9271, gpio) != 0;
2390         else if (AR_SREV_9287_10_OR_LATER(ah))
2391                 return MS_REG_READ(AR9287, gpio) != 0;
2392         else if (AR_SREV_9285_10_OR_LATER(ah))
2393                 return MS_REG_READ(AR9285, gpio) != 0;
2394         else if (AR_SREV_9280_10_OR_LATER(ah))
2395                 return MS_REG_READ(AR928X, gpio) != 0;
2396         else
2397                 return MS_REG_READ(AR, gpio) != 0;
2398 }
2399 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2400
2401 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2402                          u32 ah_signal_type)
2403 {
2404         u32 gpio_shift;
2405
2406         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2407
2408         gpio_shift = 2 * gpio;
2409
2410         REG_RMW(ah,
2411                 AR_GPIO_OE_OUT,
2412                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2413                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2414 }
2415 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2416
2417 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2418 {
2419         if (AR_SREV_9271(ah))
2420                 val = ~val;
2421
2422         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2423                 AR_GPIO_BIT(gpio));
2424 }
2425 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2426
2427 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2428 {
2429         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2430 }
2431 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2432
2433 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2434 {
2435         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2436 }
2437 EXPORT_SYMBOL(ath9k_hw_setantenna);
2438
2439 /*********************/
2440 /* General Operation */
2441 /*********************/
2442
2443 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2444 {
2445         u32 bits = REG_READ(ah, AR_RX_FILTER);
2446         u32 phybits = REG_READ(ah, AR_PHY_ERR);
2447
2448         if (phybits & AR_PHY_ERR_RADAR)
2449                 bits |= ATH9K_RX_FILTER_PHYRADAR;
2450         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2451                 bits |= ATH9K_RX_FILTER_PHYERR;
2452
2453         return bits;
2454 }
2455 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2456
2457 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2458 {
2459         u32 phybits;
2460
2461         ENABLE_REGWRITE_BUFFER(ah);
2462
2463         REG_WRITE(ah, AR_RX_FILTER, bits);
2464
2465         phybits = 0;
2466         if (bits & ATH9K_RX_FILTER_PHYRADAR)
2467                 phybits |= AR_PHY_ERR_RADAR;
2468         if (bits & ATH9K_RX_FILTER_PHYERR)
2469                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2470         REG_WRITE(ah, AR_PHY_ERR, phybits);
2471
2472         if (phybits)
2473                 REG_WRITE(ah, AR_RXCFG,
2474                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2475         else
2476                 REG_WRITE(ah, AR_RXCFG,
2477                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2478
2479         REGWRITE_BUFFER_FLUSH(ah);
2480         DISABLE_REGWRITE_BUFFER(ah);
2481 }
2482 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2483
2484 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2485 {
2486         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2487                 return false;
2488
2489         ath9k_hw_init_pll(ah, NULL);
2490         return true;
2491 }
2492 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2493
2494 bool ath9k_hw_disable(struct ath_hw *ah)
2495 {
2496         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2497                 return false;
2498
2499         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2500                 return false;
2501
2502         ath9k_hw_init_pll(ah, NULL);
2503         return true;
2504 }
2505 EXPORT_SYMBOL(ath9k_hw_disable);
2506
2507 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
2508 {
2509         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2510         struct ath9k_channel *chan = ah->curchan;
2511         struct ieee80211_channel *channel = chan->chan;
2512
2513         regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2514
2515         ah->eep_ops->set_txpower(ah, chan,
2516                                  ath9k_regd_get_ctl(regulatory, chan),
2517                                  channel->max_antenna_gain * 2,
2518                                  channel->max_power * 2,
2519                                  min((u32) MAX_RATE_POWER,
2520                                  (u32) regulatory->power_limit));
2521 }
2522 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2523
2524 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
2525 {
2526         memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
2527 }
2528 EXPORT_SYMBOL(ath9k_hw_setmac);
2529
2530 void ath9k_hw_setopmode(struct ath_hw *ah)
2531 {
2532         ath9k_hw_set_operating_mode(ah, ah->opmode);
2533 }
2534 EXPORT_SYMBOL(ath9k_hw_setopmode);
2535
2536 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2537 {
2538         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2539         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2540 }
2541 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2542
2543 void ath9k_hw_write_associd(struct ath_hw *ah)
2544 {
2545         struct ath_common *common = ath9k_hw_common(ah);
2546
2547         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2548         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2549                   ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2550 }
2551 EXPORT_SYMBOL(ath9k_hw_write_associd);
2552
2553 #define ATH9K_MAX_TSF_READ 10
2554
2555 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2556 {
2557         u32 tsf_lower, tsf_upper1, tsf_upper2;
2558         int i;
2559
2560         tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2561         for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2562                 tsf_lower = REG_READ(ah, AR_TSF_L32);
2563                 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2564                 if (tsf_upper2 == tsf_upper1)
2565                         break;
2566                 tsf_upper1 = tsf_upper2;
2567         }
2568
2569         WARN_ON( i == ATH9K_MAX_TSF_READ );
2570
2571         return (((u64)tsf_upper1 << 32) | tsf_lower);
2572 }
2573 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2574
2575 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2576 {
2577         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2578         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2579 }
2580 EXPORT_SYMBOL(ath9k_hw_settsf64);
2581
2582 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2583 {
2584         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2585                            AH_TSF_WRITE_TIMEOUT))
2586                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2587                           "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2588
2589         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2590 }
2591 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2592
2593 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2594 {
2595         if (setting)
2596                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2597         else
2598                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2599 }
2600 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2601
2602 /*
2603  *  Extend 15-bit time stamp from rx descriptor to
2604  *  a full 64-bit TSF using the current h/w TSF.
2605 */
2606 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
2607 {
2608         u64 tsf;
2609
2610         tsf = ath9k_hw_gettsf64(ah);
2611         if ((tsf & 0x7fff) < rstamp)
2612                 tsf -= 0x8000;
2613         return (tsf & ~0x7fff) | rstamp;
2614 }
2615 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
2616
2617 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2618 {
2619         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2620         u32 macmode;
2621
2622         if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2623                 macmode = AR_2040_JOINED_RX_CLEAR;
2624         else
2625                 macmode = 0;
2626
2627         REG_WRITE(ah, AR_2040_MODE, macmode);
2628 }
2629
2630 /* HW Generic timers configuration */
2631
2632 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2633 {
2634         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2635         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2636         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2637         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2638         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2639         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2640         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2641         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2642         {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2643         {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2644                                 AR_NDP2_TIMER_MODE, 0x0002},
2645         {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2646                                 AR_NDP2_TIMER_MODE, 0x0004},
2647         {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2648                                 AR_NDP2_TIMER_MODE, 0x0008},
2649         {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2650                                 AR_NDP2_TIMER_MODE, 0x0010},
2651         {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2652                                 AR_NDP2_TIMER_MODE, 0x0020},
2653         {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2654                                 AR_NDP2_TIMER_MODE, 0x0040},
2655         {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2656                                 AR_NDP2_TIMER_MODE, 0x0080}
2657 };
2658
2659 /* HW generic timer primitives */
2660
2661 /* compute and clear index of rightmost 1 */
2662 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2663 {
2664         u32 b;
2665
2666         b = *mask;
2667         b &= (0-b);
2668         *mask &= ~b;
2669         b *= debruijn32;
2670         b >>= 27;
2671
2672         return timer_table->gen_timer_index[b];
2673 }
2674
2675 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2676 {
2677         return REG_READ(ah, AR_TSF_L32);
2678 }
2679 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2680
2681 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2682                                           void (*trigger)(void *),
2683                                           void (*overflow)(void *),
2684                                           void *arg,
2685                                           u8 timer_index)
2686 {
2687         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2688         struct ath_gen_timer *timer;
2689
2690         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2691
2692         if (timer == NULL) {
2693                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2694                           "Failed to allocate memory"
2695                           "for hw timer[%d]\n", timer_index);
2696                 return NULL;
2697         }
2698
2699         /* allocate a hardware generic timer slot */
2700         timer_table->timers[timer_index] = timer;
2701         timer->index = timer_index;
2702         timer->trigger = trigger;
2703         timer->overflow = overflow;
2704         timer->arg = arg;
2705
2706         return timer;
2707 }
2708 EXPORT_SYMBOL(ath_gen_timer_alloc);
2709
2710 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2711                               struct ath_gen_timer *timer,
2712                               u32 timer_next,
2713                               u32 timer_period)
2714 {
2715         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2716         u32 tsf;
2717
2718         BUG_ON(!timer_period);
2719
2720         set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2721
2722         tsf = ath9k_hw_gettsf32(ah);
2723
2724         ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2725                   "curent tsf %x period %x"
2726                   "timer_next %x\n", tsf, timer_period, timer_next);
2727
2728         /*
2729          * Pull timer_next forward if the current TSF already passed it
2730          * because of software latency
2731          */
2732         if (timer_next < tsf)
2733                 timer_next = tsf + timer_period;
2734
2735         /*
2736          * Program generic timer registers
2737          */
2738         REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2739                  timer_next);
2740         REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2741                   timer_period);
2742         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2743                     gen_tmr_configuration[timer->index].mode_mask);
2744
2745         /* Enable both trigger and thresh interrupt masks */
2746         REG_SET_BIT(ah, AR_IMR_S5,
2747                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2748                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2749 }
2750 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2751
2752 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2753 {
2754         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2755
2756         if ((timer->index < AR_FIRST_NDP_TIMER) ||
2757                 (timer->index >= ATH_MAX_GEN_TIMER)) {
2758                 return;
2759         }
2760
2761         /* Clear generic timer enable bits. */
2762         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2763                         gen_tmr_configuration[timer->index].mode_mask);
2764
2765         /* Disable both trigger and thresh interrupt masks */
2766         REG_CLR_BIT(ah, AR_IMR_S5,
2767                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2768                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2769
2770         clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2771 }
2772 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2773
2774 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2775 {
2776         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2777
2778         /* free the hardware generic timer slot */
2779         timer_table->timers[timer->index] = NULL;
2780         kfree(timer);
2781 }
2782 EXPORT_SYMBOL(ath_gen_timer_free);
2783
2784 /*
2785  * Generic Timer Interrupts handling
2786  */
2787 void ath_gen_timer_isr(struct ath_hw *ah)
2788 {
2789         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2790         struct ath_gen_timer *timer;
2791         struct ath_common *common = ath9k_hw_common(ah);
2792         u32 trigger_mask, thresh_mask, index;
2793
2794         /* get hardware generic timer interrupt status */
2795         trigger_mask = ah->intr_gen_timer_trigger;
2796         thresh_mask = ah->intr_gen_timer_thresh;
2797         trigger_mask &= timer_table->timer_mask.val;
2798         thresh_mask &= timer_table->timer_mask.val;
2799
2800         trigger_mask &= ~thresh_mask;
2801
2802         while (thresh_mask) {
2803                 index = rightmost_index(timer_table, &thresh_mask);
2804                 timer = timer_table->timers[index];
2805                 BUG_ON(!timer);
2806                 ath_print(common, ATH_DBG_HWTIMER,
2807                           "TSF overflow for Gen timer %d\n", index);
2808                 timer->overflow(timer->arg);
2809         }
2810
2811         while (trigger_mask) {
2812                 index = rightmost_index(timer_table, &trigger_mask);
2813                 timer = timer_table->timers[index];
2814                 BUG_ON(!timer);
2815                 ath_print(common, ATH_DBG_HWTIMER,
2816                           "Gen timer[%d] trigger\n", index);
2817                 timer->trigger(timer->arg);
2818         }
2819 }
2820 EXPORT_SYMBOL(ath_gen_timer_isr);
2821
2822 /********/
2823 /* HTC  */
2824 /********/
2825
2826 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2827 {
2828         ah->htc_reset_init = true;
2829 }
2830 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2831
2832 static struct {
2833         u32 version;
2834         const char * name;
2835 } ath_mac_bb_names[] = {
2836         /* Devices with external radios */
2837         { AR_SREV_VERSION_5416_PCI,     "5416" },
2838         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2839         { AR_SREV_VERSION_9100,         "9100" },
2840         { AR_SREV_VERSION_9160,         "9160" },
2841         /* Single-chip solutions */
2842         { AR_SREV_VERSION_9280,         "9280" },
2843         { AR_SREV_VERSION_9285,         "9285" },
2844         { AR_SREV_VERSION_9287,         "9287" },
2845         { AR_SREV_VERSION_9271,         "9271" },
2846         { AR_SREV_VERSION_9300,         "9300" },
2847 };
2848
2849 /* For devices with external radios */
2850 static struct {
2851         u16 version;
2852         const char * name;
2853 } ath_rf_names[] = {
2854         { 0,                            "5133" },
2855         { AR_RAD5133_SREV_MAJOR,        "5133" },
2856         { AR_RAD5122_SREV_MAJOR,        "5122" },
2857         { AR_RAD2133_SREV_MAJOR,        "2133" },
2858         { AR_RAD2122_SREV_MAJOR,        "2122" }
2859 };
2860
2861 /*
2862  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2863  */
2864 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2865 {
2866         int i;
2867
2868         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2869                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2870                         return ath_mac_bb_names[i].name;
2871                 }
2872         }
2873
2874         return "????";
2875 }
2876
2877 /*
2878  * Return the RF name. "????" is returned if the RF is unknown.
2879  * Used for devices with external radios.
2880  */
2881 static const char *ath9k_hw_rf_name(u16 rf_version)
2882 {
2883         int i;
2884
2885         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2886                 if (ath_rf_names[i].version == rf_version) {
2887                         return ath_rf_names[i].name;
2888                 }
2889         }
2890
2891         return "????";
2892 }
2893
2894 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2895 {
2896         int used;
2897
2898         /* chipsets >= AR9280 are single-chip */
2899         if (AR_SREV_9280_10_OR_LATER(ah)) {
2900                 used = snprintf(hw_name, len,
2901                                "Atheros AR%s Rev:%x",
2902                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2903                                ah->hw_version.macRev);
2904         }
2905         else {
2906                 used = snprintf(hw_name, len,
2907                                "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2908                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2909                                ah->hw_version.macRev,
2910                                ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2911                                                 AR_RADIO_SREV_MAJOR)),
2912                                ah->hw_version.phyRev);
2913         }
2914
2915         hw_name[used] = '\0';
2916 }
2917 EXPORT_SYMBOL(ath9k_hw_name);