From 541875de9e63ea9996e275e00d2a2479d53ed75e Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Sat, 1 Oct 2011 14:27:04 +0200 Subject: [PATCH] Contributed support for LCP17xx devices and PiKRON's LMC1 board. The support originates from uLAN project sysless repository and is result of new HPLC instruments development at PiKRON company. Signed-off-by: Pavel Pisa --- embedded/arch/arm/mach-lpc17xx/Makefile | 14 + embedded/arch/arm/mach-lpc17xx/Makefile.omk | 1 + .../arch/arm/mach-lpc17xx/defines/LPC17xx.h | 1095 +++++++++++++++++ .../arch/arm/mach-lpc17xx/defines/Makefile | 14 + .../arm/mach-lpc17xx/defines/Makefile.omk | 3 + .../arch/arm/mach-lpc17xx/defines/core_cm3.h | 978 +++++++++++++++ .../mach-lpc17xx/defines/lpc17xx-um2reg.sh | 12 + .../arch/arm/mach-lpc17xx/defines/lpcUSB.h | 366 ++++++ embedded/arch/arm/mach-lpc17xx/libs/Makefile | 14 + .../arch/arm/mach-lpc17xx/libs/Makefile.omk | 3 + .../arch/arm/mach-lpc17xx/libs/hal/Makefile | 14 + .../arm/mach-lpc17xx/libs/hal/Makefile.omk | 10 + embedded/arch/arm/mach-lpc17xx/libs/hal/hal.c | 53 + .../arch/arm/mach-lpc17xx/libs/hal/hal_gpio.c | 72 ++ .../arch/arm/mach-lpc17xx/libs/hal/hal_gpio.h | 75 ++ .../arm/mach-lpc17xx/libs/hal/hal_gpio_def.h | 53 + .../mach-lpc17xx/libs/hal/hal_machperiph.c | 161 +++ .../mach-lpc17xx/libs/hal/hal_machperiph.h | 14 + .../libs/hal/hal_reserve_usb_ram.c | 21 + .../arch/arm/mach-lpc17xx/libs/hal/startup.c | 311 +++++ .../arch/arm/mach-lpc17xx/libs/iap/Makefile | 14 + .../arm/mach-lpc17xx/libs/iap/Makefile.omk | 6 + embedded/arch/arm/mach-lpc17xx/libs/iap/iap.c | 109 ++ .../arch/arm/mach-lpc17xx/libs/iap/lpciap.h | 8 + embedded/board/arm/lpc17xx-common/Makefile | 14 + .../board/arm/lpc17xx-common/Makefile.omk | 3 + .../arm/lpc17xx-common/config/config.lmc1 | 83 ++ .../arm/lpc17xx-common/config/config.u2uv2 | 88 ++ .../arm/lpc17xx-common/config/config.ulboot | 47 + .../config/config.ulboot-mpx-uu-pc | 47 + .../board/arm/lpc17xx-common/defines/Makefile | 14 + .../arm/lpc17xx-common/defines/Makefile.omk | 15 + .../lpc17xx-common/defines/system_def-lmc1.h | 666 ++++++++++ .../defines/system_def-mpx-uu-pc.h | 591 +++++++++ .../lpc17xx-common/defines/system_def-ulmi.h | 584 +++++++++ .../board/arm/lpc17xx-common/libs/Makefile | 14 + .../arm/lpc17xx-common/libs/Makefile.omk | 3 + .../arm/lpc17xx-common/libs/bspbase/Makefile | 14 + .../lpc17xx-common/libs/bspbase/Makefile.omk | 23 + .../lpc17xx-common/libs/bspbase/bsp0hwinit.c | 463 +++++++ .../arm/lpc17xx-common/libs/bspbase/bspbase.h | 11 + .../lpc17xx-common/libs/bspbase/serial_reg.h | 282 +++++ .../arm/lpc17xx-common/libs/bspbase/uart.c | 131 ++ .../arm/lpc17xx-common/libs/bspbase/uart.h | 64 + .../lpc17xx-common/libs/ldscripts/Makefile | 14 + .../libs/ldscripts/Makefile.omk | 5 + .../libs/ldscripts/keyval_loc.h | 10 + .../libs/ldscripts/lpc1754.ld-app | 10 + .../libs/ldscripts/lpc1754.ld-boot | 9 + .../libs/ldscripts/lpc1754.ld-cfg | 26 + .../libs/ldscripts/lpc1758.ld-app | 10 + .../libs/ldscripts/lpc1758.ld-boot | 9 + .../libs/ldscripts/lpc1758.ld-cfg | 30 + .../libs/ldscripts/lpc1766.ld-app | 10 + .../libs/ldscripts/lpc1766.ld-boot | 9 + .../libs/ldscripts/lpc1766.ld-cfg | 26 + .../libs/ldscripts/lpc1768.ld-app | 10 + .../libs/ldscripts/lpc1768.ld-boot | 9 + .../libs/ldscripts/lpc1768.ld-cfg | 26 + .../libs/ldscripts/lpc17xx-base.ld-app | 181 +++ .../libs/ldscripts/lpc17xx-base.ld-boot | 181 +++ .../lpc17xx-common/libs/ldscripts/mem_loc.h | 8 + 62 files changed, 7161 insertions(+) create mode 100644 embedded/arch/arm/mach-lpc17xx/Makefile create mode 100644 embedded/arch/arm/mach-lpc17xx/Makefile.omk create mode 100644 embedded/arch/arm/mach-lpc17xx/defines/LPC17xx.h create mode 100644 embedded/arch/arm/mach-lpc17xx/defines/Makefile create mode 100644 embedded/arch/arm/mach-lpc17xx/defines/Makefile.omk create mode 100644 embedded/arch/arm/mach-lpc17xx/defines/core_cm3.h create mode 100644 embedded/arch/arm/mach-lpc17xx/defines/lpc17xx-um2reg.sh create mode 100644 embedded/arch/arm/mach-lpc17xx/defines/lpcUSB.h create mode 100644 embedded/arch/arm/mach-lpc17xx/libs/Makefile create mode 100644 embedded/arch/arm/mach-lpc17xx/libs/Makefile.omk create mode 100644 embedded/arch/arm/mach-lpc17xx/libs/hal/Makefile create mode 100644 embedded/arch/arm/mach-lpc17xx/libs/hal/Makefile.omk create mode 100644 embedded/arch/arm/mach-lpc17xx/libs/hal/hal.c create mode 100644 embedded/arch/arm/mach-lpc17xx/libs/hal/hal_gpio.c create mode 100644 embedded/arch/arm/mach-lpc17xx/libs/hal/hal_gpio.h create mode 100644 embedded/arch/arm/mach-lpc17xx/libs/hal/hal_gpio_def.h create mode 100644 embedded/arch/arm/mach-lpc17xx/libs/hal/hal_machperiph.c create mode 100644 embedded/arch/arm/mach-lpc17xx/libs/hal/hal_machperiph.h create mode 100644 embedded/arch/arm/mach-lpc17xx/libs/hal/hal_reserve_usb_ram.c create mode 100644 embedded/arch/arm/mach-lpc17xx/libs/hal/startup.c create mode 100644 embedded/arch/arm/mach-lpc17xx/libs/iap/Makefile create mode 100644 embedded/arch/arm/mach-lpc17xx/libs/iap/Makefile.omk create mode 100644 embedded/arch/arm/mach-lpc17xx/libs/iap/iap.c create mode 100644 embedded/arch/arm/mach-lpc17xx/libs/iap/lpciap.h create mode 100644 embedded/board/arm/lpc17xx-common/Makefile create mode 100644 embedded/board/arm/lpc17xx-common/Makefile.omk create mode 100644 embedded/board/arm/lpc17xx-common/config/config.lmc1 create mode 100644 embedded/board/arm/lpc17xx-common/config/config.u2uv2 create mode 100644 embedded/board/arm/lpc17xx-common/config/config.ulboot create mode 100644 embedded/board/arm/lpc17xx-common/config/config.ulboot-mpx-uu-pc create mode 100644 embedded/board/arm/lpc17xx-common/defines/Makefile create mode 100644 embedded/board/arm/lpc17xx-common/defines/Makefile.omk create mode 100644 embedded/board/arm/lpc17xx-common/defines/system_def-lmc1.h create mode 100644 embedded/board/arm/lpc17xx-common/defines/system_def-mpx-uu-pc.h create mode 100644 embedded/board/arm/lpc17xx-common/defines/system_def-ulmi.h create mode 100644 embedded/board/arm/lpc17xx-common/libs/Makefile create mode 100644 embedded/board/arm/lpc17xx-common/libs/Makefile.omk create mode 100644 embedded/board/arm/lpc17xx-common/libs/bspbase/Makefile create mode 100644 embedded/board/arm/lpc17xx-common/libs/bspbase/Makefile.omk create mode 100644 embedded/board/arm/lpc17xx-common/libs/bspbase/bsp0hwinit.c create mode 100644 embedded/board/arm/lpc17xx-common/libs/bspbase/bspbase.h create mode 100644 embedded/board/arm/lpc17xx-common/libs/bspbase/serial_reg.h create mode 100644 embedded/board/arm/lpc17xx-common/libs/bspbase/uart.c create mode 100644 embedded/board/arm/lpc17xx-common/libs/bspbase/uart.h create mode 100644 embedded/board/arm/lpc17xx-common/libs/ldscripts/Makefile create mode 100644 embedded/board/arm/lpc17xx-common/libs/ldscripts/Makefile.omk create mode 100644 embedded/board/arm/lpc17xx-common/libs/ldscripts/keyval_loc.h create mode 100644 embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1754.ld-app create mode 100644 embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1754.ld-boot create mode 100644 embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1754.ld-cfg create mode 100644 embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1758.ld-app create mode 100644 embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1758.ld-boot create mode 100644 embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1758.ld-cfg create mode 100644 embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1766.ld-app create mode 100644 embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1766.ld-boot create mode 100644 embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1766.ld-cfg create mode 100644 embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1768.ld-app create mode 100644 embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1768.ld-boot create mode 100644 embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1768.ld-cfg create mode 100644 embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc17xx-base.ld-app create mode 100644 embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc17xx-base.ld-boot create mode 100644 embedded/board/arm/lpc17xx-common/libs/ldscripts/mem_loc.h diff --git a/embedded/arch/arm/mach-lpc17xx/Makefile b/embedded/arch/arm/mach-lpc17xx/Makefile new file mode 100644 index 0000000..76b56fd --- /dev/null +++ b/embedded/arch/arm/mach-lpc17xx/Makefile @@ -0,0 +1,14 @@ +# Generic directory or leaf node makefile for OCERA make framework + +ifndef MAKERULES_DIR +MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) ) +endif + +ifeq ($(MAKERULES_DIR),) +all : default +.DEFAULT:: + @echo -e "\nThe Makefile.rules has not been found in this or parent directory\n" +else +include $(MAKERULES_DIR)/Makefile.rules +endif + diff --git a/embedded/arch/arm/mach-lpc17xx/Makefile.omk b/embedded/arch/arm/mach-lpc17xx/Makefile.omk new file mode 100644 index 0000000..2ebd5c8 --- /dev/null +++ b/embedded/arch/arm/mach-lpc17xx/Makefile.omk @@ -0,0 +1 @@ +SUBDIRS = defines libs diff --git a/embedded/arch/arm/mach-lpc17xx/defines/LPC17xx.h b/embedded/arch/arm/mach-lpc17xx/defines/LPC17xx.h new file mode 100644 index 0000000..e1d597b --- /dev/null +++ b/embedded/arch/arm/mach-lpc17xx/defines/LPC17xx.h @@ -0,0 +1,1095 @@ +/****************************************************************************//** + * @file : LPC17xx.h + * @brief : CMSIS Cortex-M3 Core Peripheral Access Layer Header File for + * NXP LPC17xx Device Series + * @version : V1.1 + * @date : 14th May 2009 + *---------------------------------------------------------------------------- + * + * Copyright (C) 2008 ARM Limited. All rights reserved. + * + * ARM Limited (ARM) is supplying this software for use with Cortex-M3 + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __LPC17xx_H__ +#define __LPC17xx_H__ + +/////////////////////////////////////////////////////////////////////////////// +// Keyval +#define KVPB_CHUNK_SIZE 16 + +/////////////////////////////////////////////////////////////////////////////// +// ISP_RAM2FLASH_BLOCK_SIZE for 17xx CPU +#ifndef ISP_RAM2FLASH_BLOCK_SIZE + #define ISP_RAM2FLASH_BLOCK_SIZE 256 +#endif /* ISP_RAM2FLASH_BLOCK_SIZE */ + +/** @addtogroup CMSIS_Configuration + * @{ + */ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +/** + * @brief Interrupt Number Type Definition + */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** LPC17xx Specific Interrupt Numbers *******************************************************/ + WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ + TIMER0_IRQn = 1, /*!< Timer0 Interrupt */ + TIMER1_IRQn = 2, /*!< Timer1 Interrupt */ + TIMER2_IRQn = 3, /*!< Timer2 Interrupt */ + TIMER3_IRQn = 4, /*!< Timer3 Interrupt */ + UART0_IRQn = 5, /*!< UART0 Interrupt */ + UART1_IRQn = 6, /*!< UART1 Interrupt */ + UART2_IRQn = 7, /*!< UART2 Interrupt */ + UART3_IRQn = 8, /*!< UART3 Interrupt */ + PWM1_IRQn = 9, /*!< PWM1 Interrupt */ + I2C0_IRQn = 10, /*!< I2C0 Interrupt */ + I2C1_IRQn = 11, /*!< I2C1 Interrupt */ + I2C2_IRQn = 12, /*!< I2C2 Interrupt */ + SPI_IRQn = 13, /*!< SPI Interrupt */ + SSP0_IRQn = 14, /*!< SSP0 Interrupt */ + SSP1_IRQn = 15, /*!< SSP1 Interrupt */ + PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */ + RTC_IRQn = 17, /*!< Real Time Clock Interrupt */ + EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */ + EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */ + EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */ + EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */ + ADC_IRQn = 22, /*!< A/D Converter Interrupt */ + BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */ + USB_IRQn = 24, /*!< USB Interrupt */ + CAN_IRQn = 25, /*!< CAN Interrupt */ + DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */ + I2S_IRQn = 27, /*!< I2S Interrupt */ + ENET_IRQn = 28, /*!< Ethernet Interrupt */ + RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */ + MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ + QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ + PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ +} IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M3 Processor and Core Peripherals */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ + + + +/** + * Initialize the system clock + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemFrequency variable. + */ +extern void SystemInit (void); + + +/** @addtogroup Peripheral_register_structures + * @{ + */ + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +//#ifndef __IAR_SYSTEMS_ICC__ +//#pragma anon_unions +//#endif + + +/*------------- System Control (SC) ------------------------------------------*/ +/** + * @brief System Control Structure Type Definition + */ +typedef struct +{ + __IO uint32_t FLASHCFG; /* Flash Accelerator Module */ + uint32_t RESERVED0[31]; + __IO uint32_t PLL0CON; /* Clocking and Power Control */ + __IO uint32_t PLL0CFG; + __I uint32_t PLL0STAT; + __O uint32_t PLL0FEED; + uint32_t RESERVED1[4]; + __IO uint32_t PLL1CON; + __IO uint32_t PLL1CFG; + __I uint32_t PLL1STAT; + __O uint32_t PLL1FEED; + uint32_t RESERVED2[4]; + __IO uint32_t PCON; + __IO uint32_t PCONP; + uint32_t RESERVED3[15]; + __IO uint32_t CCLKCFG; + __IO uint32_t USBCLKCFG; + __IO uint32_t CLKSRCSEL; + uint32_t RESERVED4[12]; + __IO uint32_t EXTINT; /* External Interrupts */ + uint32_t RESERVED5; + __IO uint32_t EXTMODE; + __IO uint32_t EXTPOLAR; + uint32_t RESERVED6[12]; + __IO uint32_t RSID; /* Reset */ + uint32_t RESERVED7[7]; + __IO uint32_t SCS; /* Syscon Miscellaneous Registers */ + __IO uint32_t IRCTRIM; /* Clock Dividers */ + __IO uint32_t PCLKSEL0; + __IO uint32_t PCLKSEL1; + uint32_t RESERVED8[4]; + __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */ + uint32_t RESERVED9; + __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */ + } SC_TypeDef; + +/*------------- Pin Connect Block (PINCON) -----------------------------------*/ +/** + * @brief Pin Connect (Select) Structure Type Definition + */ +typedef struct +{ + __IO uint32_t PINSEL0; + __IO uint32_t PINSEL1; + __IO uint32_t PINSEL2; + __IO uint32_t PINSEL3; + __IO uint32_t PINSEL4; + __IO uint32_t PINSEL5; + __IO uint32_t PINSEL6; + __IO uint32_t PINSEL7; + __IO uint32_t PINSEL8; + __IO uint32_t PINSEL9; + __IO uint32_t PINSEL10; + uint32_t RESERVED0[5]; + __IO uint32_t PINMODE0; + __IO uint32_t PINMODE1; + __IO uint32_t PINMODE2; + __IO uint32_t PINMODE3; + __IO uint32_t PINMODE4; + __IO uint32_t PINMODE5; + __IO uint32_t PINMODE6; + __IO uint32_t PINMODE7; + __IO uint32_t PINMODE8; + __IO uint32_t PINMODE9; + __IO uint32_t PINMODE_OD0; + __IO uint32_t PINMODE_OD1; + __IO uint32_t PINMODE_OD2; + __IO uint32_t PINMODE_OD3; + __IO uint32_t PINMODE_OD4; + __IO uint32_t I2CPADCFG; +} PINCON_TypeDef; + + +/*------------- General Purpose Input/Output (GPIO) --------------------------*/ +/** + * @brief GPIO Structure Type Definition + */ +typedef struct +{ + __IO uint32_t FIODIR; + uint32_t RESERVED0[3]; + __IO uint32_t FIOMASK; + __IO uint32_t FIOPIN; + __IO uint32_t FIOSET; + __O uint32_t FIOCLR; +} GPIO_TypeDef; + +/** + * @brief GPIO Interrupt Structure Type Definition + */ +typedef struct +{ + __I uint32_t IntStatus; + __I uint32_t IO0IntStatR; + __I uint32_t IO0IntStatF; + __O uint32_t IO0IntClr; + __IO uint32_t IO0IntEnR; + __IO uint32_t IO0IntEnF; + uint32_t RESERVED0[3]; + __I uint32_t IO2IntStatR; + __I uint32_t IO2IntStatF; + __O uint32_t IO2IntClr; + __IO uint32_t IO2IntEnR; + __IO uint32_t IO2IntEnF; +} GPIOINT_TypeDef; + +/*------------- Timer (TIM) --------------------------------------------------*/ +/** + * @brief Timer Structure Type Definition + */ +typedef struct +{ + __IO uint32_t IR; + __IO uint32_t TCR; + __IO uint32_t TC; + __IO uint32_t PR; + __IO uint32_t PC; + __IO uint32_t MCR; + __IO uint32_t MR0; + __IO uint32_t MR1; + __IO uint32_t MR2; + __IO uint32_t MR3; + __IO uint32_t CCR; + __I uint32_t CR0; + __I uint32_t CR1; + uint32_t RESERVED0[2]; + __IO uint32_t EMR; + uint32_t RESERVED1[24]; + __IO uint32_t CTCR; +} TIM_TypeDef; + +/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ +/** + * @brief Pulse Width ModulationStructure Type Definition + */ +typedef struct +{ + __IO uint32_t IR; + __IO uint32_t TCR; + __IO uint32_t TC; + __IO uint32_t PR; + __IO uint32_t PC; + __IO uint32_t MCR; + __IO uint32_t MR0; + __IO uint32_t MR1; + __IO uint32_t MR2; + __IO uint32_t MR3; + __IO uint32_t CCR; + __I uint32_t CR0; + __I uint32_t CR1; + __I uint32_t CR2; + __I uint32_t CR3; + uint32_t RESERVED0; + __IO uint32_t MR4; + __IO uint32_t MR5; + __IO uint32_t MR6; + __IO uint32_t PCR; + __IO uint32_t LER; + uint32_t RESERVED1[7]; + __IO uint32_t CTCR; +} PWM_TypeDef; + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +/** + * @brief Universal Asynchronous Receiver Transmitter 0/2/3 Structure Type Definition + */ +typedef struct +{ + union { + __I uint8_t RBR; + __O uint8_t THR; + __IO uint8_t DLL; + uint32_t RESERVED0; + }; + + union { + __IO uint8_t DLM; + __IO uint32_t IER; + }; + + union { + __I uint32_t IIR; + __O uint8_t FCR; + }; + + __IO uint8_t LCR; + uint8_t RESERVED1[7]; + __I uint8_t LSR; + uint8_t RESERVED2[7]; + __IO uint8_t SCR; + uint8_t RESERVED3[3]; + __IO uint32_t ACR; + __IO uint32_t ICR; + __IO uint32_t FDR; + uint32_t RESERVED4; + __IO uint8_t TER; + uint8_t RESERVED5[39]; + __I uint32_t FIFOLVL; +} UART_TypeDef; + +/** + * @brief Universal Asynchronous Receiver Transmitter 1 Structure Type Definition + */ +typedef struct +{ + union { + __I uint8_t RBR; + __O uint8_t THR; + __IO uint8_t DLL; + uint32_t RESERVED0; + }; + union { + __IO uint8_t DLM; + __IO uint32_t IER; + }; + union { + __I uint32_t IIR; + __O uint8_t FCR; + }; + __IO uint8_t LCR; + uint8_t RESERVED1[3]; + __IO uint8_t MCR; + uint8_t RESERVED2[3]; + __IO uint8_t LSR; + uint8_t RESERVED3[3]; + __IO uint8_t MSR; + uint8_t RESERVED4[3]; + __IO uint8_t SCR; + uint8_t RESERVED5[3]; + __IO uint32_t ACR; + uint32_t RESERVED6; + __IO uint32_t FDR; + uint32_t RESERVED7; + __IO uint8_t TER; + uint8_t RESERVED8[27]; + __IO uint8_t RS485CTRL; + uint8_t RESERVED9[3]; + __IO uint8_t ADRMATCH; + uint8_t RESERVED10[3]; + __IO uint8_t RS485DLY; + uint8_t RESERVED11[3]; + __IO uint32_t FIFOLVL; +} UART1_TypeDef; + + +/*------------- Serial Peripheral Interface (SPI) ----------------------------*/ +/** + * @brief Serial Peripheral InterfaceStructure Type Definition + */ +typedef struct +{ + __IO uint32_t SPCR; + __I uint32_t SPSR; + __IO uint32_t SPDR; + __IO uint32_t SPCCR; + uint32_t RESERVED0[3]; + __IO uint32_t SPINT; +} SPI_TypeDef; + +/*------------- Synchronous Serial Communication (SSP) -----------------------*/ +/** + * @brief Synchronous Serial Communication Structure Type Definition + */ +typedef struct +{ + __IO uint32_t CR0; + __IO uint32_t CR1; + __IO uint32_t DR; + __I uint32_t SR; + __IO uint32_t CPSR; + __IO uint32_t IMSC; + __IO uint32_t RIS; + __IO uint32_t MIS; + __IO uint32_t ICR; + __IO uint32_t DMACR; +} SSP_TypeDef; + +/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ +/** + * @brief Inter-Intergrated Circuit Structure Type Definition + */ +typedef struct +{ + __IO uint32_t I2CONSET; + __I uint32_t I2STAT; + __IO uint32_t I2DAT; + __IO uint32_t I2ADR0; + __IO uint32_t I2SCLH; + __IO uint32_t I2SCLL; + __O uint32_t I2CONCLR; + __IO uint32_t MMCTRL; + __IO uint32_t I2ADR1; + __IO uint32_t I2ADR2; + __IO uint32_t I2ADR3; + __I uint32_t I2DATA_BUFFER; + __IO uint32_t I2MASK0; + __IO uint32_t I2MASK1; + __IO uint32_t I2MASK2; + __IO uint32_t I2MASK3; +} I2C_TypeDef; + +/*------------- Inter IC Sound (I2S) -----------------------------------------*/ +/** + * @brief Inter IC Sound Structure Type Definition + */ +typedef struct +{ + __IO uint32_t I2SDAO; + __IO uint32_t I2SDAI; + __O uint32_t I2STXFIFO; + __I uint32_t I2SRXFIFO; + __I uint32_t I2SSTATE; + __IO uint32_t I2SDMA1; + __IO uint32_t I2SDMA2; + __IO uint32_t I2SIRQ; + __IO uint32_t I2STXRATE; + __IO uint32_t I2SRXRATE; + __IO uint32_t I2STXBITRATE; + __IO uint32_t I2SRXBITRATE; + __IO uint32_t I2STXMODE; + __IO uint32_t I2SRXMODE; +} I2S_TypeDef; + +/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/ +/** + * @brief Repetitive Interrupt Timer Structure Type Definition + */ +typedef struct +{ + __IO uint32_t RICOMPVAL; + __IO uint32_t RIMASK; + __IO uint8_t RICTRL; + uint8_t RESERVED0[3]; + __IO uint32_t RICOUNTER; +} RIT_TypeDef; + +/*------------- Real-Time Clock (RTC) ----------------------------------------*/ +/** + * @brief Real Time Clock Structure Type Definition + */ +typedef struct +{ + __IO uint8_t ILR; + uint8_t RESERVED0[7]; + __IO uint8_t CCR; + uint8_t RESERVED1[3]; + __IO uint8_t CIIR; + uint8_t RESERVED2[3]; + __IO uint8_t AMR; + uint8_t RESERVED3[3]; + __I uint32_t CTIME0; + __I uint32_t CTIME1; + __I uint32_t CTIME2; + __IO uint8_t SEC; + uint8_t RESERVED4[3]; + __IO uint8_t MIN; + uint8_t RESERVED5[3]; + __IO uint8_t HOUR; + uint8_t RESERVED6[3]; + __IO uint8_t DOM; + uint8_t RESERVED7[3]; + __IO uint8_t DOW; + uint8_t RESERVED8[3]; + __IO uint16_t DOY; + uint16_t RESERVED9; + __IO uint8_t MONTH; + uint8_t RESERVED10[3]; + __IO uint16_t YEAR; + uint16_t RESERVED11; + __IO uint32_t CALIBRATION; + __IO uint32_t GPREG0; + __IO uint32_t GPREG1; + __IO uint32_t GPREG2; + __IO uint32_t GPREG3; + __IO uint32_t GPREG4; + __IO uint8_t WAKEUPDIS; + uint8_t RESERVED12[3]; + __IO uint8_t PWRCTRL; + uint8_t RESERVED13[3]; + __IO uint8_t ALSEC; + uint8_t RESERVED14[3]; + __IO uint8_t ALMIN; + uint8_t RESERVED15[3]; + __IO uint8_t ALHOUR; + uint8_t RESERVED16[3]; + __IO uint8_t ALDOM; + uint8_t RESERVED17[3]; + __IO uint8_t ALDOW; + uint8_t RESERVED18[3]; + __IO uint16_t ALDOY; + uint16_t RESERVED19; + __IO uint8_t ALMON; + uint8_t RESERVED20[3]; + __IO uint16_t ALYEAR; + uint16_t RESERVED21; +} RTC_TypeDef; + + +/*------------- Watchdog Timer (WDT) -----------------------------------------*/ +/** + * @brief Watchdog Timer Structure Type Definition + */ +typedef struct +{ + __IO uint8_t WDMOD; + uint8_t RESERVED0[3]; + __IO uint32_t WDTC; + __O uint8_t WDFEED; + uint8_t RESERVED1[3]; + __I uint32_t WDTV; + __IO uint32_t WDCLKSEL; +} WDT_TypeDef; + +/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ +/** + * @brief Analog to Digital Structure Type Definition + */ +typedef struct +{ + __IO uint32_t ADCR; + __IO uint32_t ADGDR; +#ifndef __LPC17XX_REV00 + uint32_t RESERVED0; +#endif + __IO uint32_t ADINTEN; + __I uint32_t ADDR0; + __I uint32_t ADDR1; + __I uint32_t ADDR2; + __I uint32_t ADDR3; + __I uint32_t ADDR4; + __I uint32_t ADDR5; + __I uint32_t ADDR6; + __I uint32_t ADDR7; + __I uint32_t ADSTAT; + __IO uint32_t ADTRM; +} ADC_TypeDef; + + +/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ +/** + * @brief Digital to Analog Structure Type Definition + */ +typedef struct +{ + __IO uint32_t DACR; + __IO uint32_t DACCTRL; + __IO uint16_t DACCNTVAL; +} DAC_TypeDef; + +/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ +/** + * @brief Motor Control Pulse Width Modulation Structure Type Definition + */ +typedef struct +{ + __I uint32_t MCCON; + __O uint32_t MCCON_SET; + __O uint32_t MCCON_CLR; + __I uint32_t MCCAPCON; + __O uint32_t MCCAPCON_SET; + __O uint32_t MCCAPCON_CLR; + __IO uint32_t MCTIM0; + __IO uint32_t MCTIM1; + __IO uint32_t MCTIM2; + __IO uint32_t MCPER0; + __IO uint32_t MCPER1; + __IO uint32_t MCPER2; + __IO uint32_t MCPW0; + __IO uint32_t MCPW1; + __IO uint32_t MCPW2; + __IO uint32_t MCDEADTIME; + __IO uint32_t MCCCP; + __IO uint32_t MCCR0; + __IO uint32_t MCCR1; + __IO uint32_t MCCR2; + __I uint32_t MCINTEN; + __O uint32_t MCINTEN_SET; + __O uint32_t MCINTEN_CLR; + __I uint32_t MCCNTCON; + __O uint32_t MCCNTCON_SET; + __O uint32_t MCCNTCON_CLR; + __I uint32_t MCINTFLAG; + __O uint32_t MCINTFLAG_SET; + __O uint32_t MCINTFLAG_CLR; + __O uint32_t MCCAP_CLR; +} MCPWM_TypeDef; + +/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ +/** + * @brief Quadrature Encoder Interface Structure Type Definition + */ +typedef struct +{ + __O uint32_t QEICON; + __I uint32_t QEISTAT; + __IO uint32_t QEICONF; + __I uint32_t QEIPOS; + __IO uint32_t QEIMAXPOS; + __IO uint32_t CMPOS0; + __IO uint32_t CMPOS1; + __IO uint32_t CMPOS2; + __I uint32_t INXCNT; + __IO uint32_t INXCMP; + __IO uint32_t QEILOAD; + __I uint32_t QEITIME; + __I uint32_t QEIVEL; + __I uint32_t QEICAP; + __IO uint32_t VELCOMP; + __IO uint32_t FILTER; + uint32_t RESERVED0[998]; + __O uint32_t QEIIEC; + __O uint32_t QEIIES; + __I uint32_t QEIINTSTAT; + __I uint32_t QEIIE; + __O uint32_t QEICLR; + __O uint32_t QEISET; +} QEI_TypeDef; + +/*------------- Controller Area Network (CAN) --------------------------------*/ +/** + * @brief Control Area Network Structure Type Definition + */ +typedef struct +{ + __IO uint32_t mask[512]; /* ID Masks */ +} CANAF_RAM_TypeDef; + +/** + * @brief Acceptance Filter Structure Type Definition + */ +typedef struct /* Acceptance Filter Registers */ +{ + __IO uint32_t AFMR; + __IO uint32_t SFF_sa; + __IO uint32_t SFF_GRP_sa; + __IO uint32_t EFF_sa; + __IO uint32_t EFF_GRP_sa; + __IO uint32_t ENDofTable; + __I uint32_t LUTerrAd; + __I uint32_t LUTerr; + __IO uint32_t FCANIE; + __I uint32_t FCANIC0; + __I uint32_t FCANIC1; +} CANAF_TypeDef; + +/** + * @brief CAN Central Structure Type Definition + */ +typedef struct /* Central Registers */ +{ + __I uint32_t CANTxSR; + __I uint32_t CANRxSR; + __I uint32_t CANMSR; +} CANCR_TypeDef; + +/** + * @brief CAN Controller Structure Type Definition + */ +typedef struct /* Controller Registers */ +{ + __IO uint32_t MOD; + __O uint32_t CMR; + __IO uint32_t GSR; + __I uint32_t ICR; + __IO uint32_t IER; + __IO uint32_t BTR; + __IO uint32_t EWL; + __I uint32_t SR; + __IO uint32_t RFS; + __IO uint32_t RID; + __IO uint32_t RDA; + __IO uint32_t RDB; + __IO uint32_t TFI1; + __IO uint32_t TID1; + __IO uint32_t TDA1; + __IO uint32_t TDB1; + __IO uint32_t TFI2; + __IO uint32_t TID2; + __IO uint32_t TDA2; + __IO uint32_t TDB2; + __IO uint32_t TFI3; + __IO uint32_t TID3; + __IO uint32_t TDA3; + __IO uint32_t TDB3; +} CAN_TypeDef; + +/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ +/** + * @brief General Purpose Direct Memory Access Structure Type Definition + */ +typedef struct /* Common Registers */ +{ + __I uint32_t DMACIntStat; + __I uint32_t DMACIntTCStat; + __O uint32_t DMACIntTCClear; + __I uint32_t DMACIntErrStat; + __O uint32_t DMACIntErrClr; + __I uint32_t DMACRawIntTCStat; + __I uint32_t DMACRawIntErrStat; + __I uint32_t DMACEnbldChns; + __IO uint32_t DMACSoftBReq; + __IO uint32_t DMACSoftSReq; + __IO uint32_t DMACSoftLBReq; + __IO uint32_t DMACSoftLSReq; + __IO uint32_t DMACConfig; + __IO uint32_t DMACSync; +} GPDMA_TypeDef; + +/** + * @brief GPDMA Channel Structure Type Definition + */ +typedef struct /* Channel Registers */ +{ + __IO uint32_t DMACCSrcAddr; + __IO uint32_t DMACCDestAddr; + __IO uint32_t DMACCLLI; + __IO uint32_t DMACCControl; + __IO uint32_t DMACCConfig; +} GPDMACH_TypeDef; + + +/*------------- Universal Serial Bus (USB) -----------------------------------*/ +/** + * @brief Universal Serial Bus Structure Type Definition + */ +typedef struct +{ + __I uint32_t HcRevision; /* USB Host Registers */ + __IO uint32_t HcControl; + __IO uint32_t HcCommandStatus; + __IO uint32_t HcInterruptStatus; + __IO uint32_t HcInterruptEnable; + __IO uint32_t HcInterruptDisable; + __IO uint32_t HcHCCA; + __I uint32_t HcPeriodCurrentED; + __IO uint32_t HcControlHeadED; + __IO uint32_t HcControlCurrentED; + __IO uint32_t HcBulkHeadED; + __IO uint32_t HcBulkCurrentED; + __I uint32_t HcDoneHead; + __IO uint32_t HcFmInterval; + __I uint32_t HcFmRemaining; + __I uint32_t HcFmNumber; + __IO uint32_t HcPeriodicStart; + __IO uint32_t HcLSTreshold; + __IO uint32_t HcRhDescriptorA; + __IO uint32_t HcRhDescriptorB; + __IO uint32_t HcRhStatus; + __IO uint32_t HcRhPortStatus1; + __IO uint32_t HcRhPortStatus2; + uint32_t RESERVED0[40]; + __I uint32_t Module_ID; + + __I uint32_t OTGIntSt; /* USB On-The-Go Registers */ + __IO uint32_t OTGIntEn; + __O uint32_t OTGIntSet; + __O uint32_t OTGIntClr; + __IO uint32_t OTGStCtrl; + __IO uint32_t OTGTmr; + uint32_t RESERVED1[58]; + + __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */ + __IO uint32_t USBDevIntEn; + __O uint32_t USBDevIntClr; + __O uint32_t USBDevIntSet; + + __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */ + __I uint32_t USBCmdData; + + __I uint32_t USBRxData; /* USB Device Transfer Registers */ + __O uint32_t USBTxData; + __I uint32_t USBRxPLen; + __O uint32_t USBTxPLen; + __IO uint32_t USBCtrl; + __O uint32_t USBDevIntPri; + + __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */ + __IO uint32_t USBEpIntEn; + __O uint32_t USBEpIntClr; + __O uint32_t USBEpIntSet; + __O uint32_t USBEpIntPri; + + __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/ + __O uint32_t USBEpInd; + __IO uint32_t USBMaxPSize; + + __I uint32_t USBDMARSt; /* USB Device DMA Registers */ + __O uint32_t USBDMARClr; + __O uint32_t USBDMARSet; + uint32_t RESERVED2[9]; + __IO uint32_t USBUDCAH; + __I uint32_t USBEpDMASt; + __O uint32_t USBEpDMAEn; + __O uint32_t USBEpDMADis; + __I uint32_t USBDMAIntSt; + __IO uint32_t USBDMAIntEn; + uint32_t RESERVED3[2]; + __I uint32_t USBEoTIntSt; + __O uint32_t USBEoTIntClr; + __O uint32_t USBEoTIntSet; + __I uint32_t USBNDDRIntSt; + __O uint32_t USBNDDRIntClr; + __O uint32_t USBNDDRIntSet; + __I uint32_t USBSysErrIntSt; + __O uint32_t USBSysErrIntClr; + __O uint32_t USBSysErrIntSet; + uint32_t RESERVED4[15]; + + __I uint32_t I2C_RX; /* USB OTG I2C Registers */ + __O uint32_t I2C_WO; + __I uint32_t I2C_STS; + __IO uint32_t I2C_CTL; + __IO uint32_t I2C_CLKHI; + __O uint32_t I2C_CLKLO; + uint32_t RESERVED5[823]; + + union { + __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ + __IO uint32_t OTGClkCtrl; + }; + union { + __I uint32_t USBClkSt; + __I uint32_t OTGClkSt; + }; +} USB_TypeDef; + +/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ +/** + * @brief Ethernet Media Access Controller Structure Type Definition + */ +typedef struct +{ + __IO uint32_t MAC1; /* MAC Registers */ + __IO uint32_t MAC2; + __IO uint32_t IPGT; + __IO uint32_t IPGR; + __IO uint32_t CLRT; + __IO uint32_t MAXF; + __IO uint32_t SUPP; + __IO uint32_t TEST; + __IO uint32_t MCFG; + __IO uint32_t MCMD; + __IO uint32_t MADR; + __O uint32_t MWTD; + __I uint32_t MRDD; + __I uint32_t MIND; + uint32_t RESERVED0[2]; + __IO uint32_t SA0; + __IO uint32_t SA1; + __IO uint32_t SA2; + uint32_t RESERVED1[45]; + __IO uint32_t Command; /* Control Registers */ + __I uint32_t Status; + __IO uint32_t RxDescriptor; + __IO uint32_t RxStatus; + __IO uint32_t RxDescriptorNumber; + __I uint32_t RxProduceIndex; + __IO uint32_t RxConsumeIndex; + __IO uint32_t TxDescriptor; + __IO uint32_t TxStatus; + __IO uint32_t TxDescriptorNumber; + __IO uint32_t TxProduceIndex; + __I uint32_t TxConsumeIndex; + uint32_t RESERVED2[10]; + __I uint32_t TSV0; + __I uint32_t TSV1; + __I uint32_t RSV; + uint32_t RESERVED3[3]; + __IO uint32_t FlowControlCounter; + __I uint32_t FlowControlStatus; + uint32_t RESERVED4[34]; + __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ + __IO uint32_t RxFilterWoLStatus; + __IO uint32_t RxFilterWoLClear; + uint32_t RESERVED5; + __IO uint32_t HashFilterL; + __IO uint32_t HashFilterH; + uint32_t RESERVED6[882]; + __I uint32_t IntStatus; /* Module Control Registers */ + __IO uint32_t IntEnable; + __O uint32_t IntClear; + __O uint32_t IntSet; + uint32_t RESERVED7; + __IO uint32_t PowerDown; + uint32_t RESERVED8; + __IO uint32_t Module_ID; +} EMAC_TypeDef; + +//#ifndef __IAR_SYSTEMS_ICC__ +//#pragma no_anon_unions +//#endif + +/** + * @} + */ + + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Base addresses */ +#define FLASH_BASE (0x00000000UL) +#define RAM_BASE (0x10000000UL) +#ifdef __LPC17XX_REV00 +#define AHBRAM0_BASE (0x20000000UL) +#define AHBRAM1_BASE (0x20004000UL) +#else +#define AHBRAM0_BASE (0x2007C000UL) +#define AHBRAM1_BASE (0x20080000UL) +#define GPIO_BASE (0x2009C000UL) +#endif +#define APB0_BASE (0x40000000UL) +#define APB1_BASE (0x40080000UL) +#define AHB_BASE (0x50000000UL) +#define CM3_BASE (0xE0000000UL) + +#ifdef __LPC17XX_REV00 +#define GPIO_BASE (AHB_BASE + 0x14000) +#endif + +/* APB0 peripherals */ +#define WDT_BASE (APB0_BASE + 0x00000) +#define TIM0_BASE (APB0_BASE + 0x04000) +#define TIM1_BASE (APB0_BASE + 0x08000) +#define UART0_BASE (APB0_BASE + 0x0C000) +#define UART1_BASE (APB0_BASE + 0x10000) +#define PWM1_BASE (APB0_BASE + 0x18000) +#define I2C0_BASE (APB0_BASE + 0x1C000) +#define SPI_BASE (APB0_BASE + 0x20000) +#define RTC_BASE (APB0_BASE + 0x24000) +#define GPIOINT_BASE (APB0_BASE + 0x28080) +#define PINCON_BASE (APB0_BASE + 0x2C000) +#define SSP1_BASE (APB0_BASE + 0x30000) +#define ADC_BASE (APB0_BASE + 0x34000) +#define CANAF_RAM_BASE (APB0_BASE + 0x38000) +#define CANAF_BASE (APB0_BASE + 0x3C000) +#define CANCR_BASE (APB0_BASE + 0x40000) +#define CAN1_BASE (APB0_BASE + 0x44000) +#define CAN2_BASE (APB0_BASE + 0x48000) +#define I2C1_BASE (APB0_BASE + 0x5C000) + +/* APB1 peripherals */ +#define SSP0_BASE (APB1_BASE + 0x08000) +#define DAC_BASE (APB1_BASE + 0x0C000) +#define TIM2_BASE (APB1_BASE + 0x10000) +#define TIM3_BASE (APB1_BASE + 0x14000) +#define UART2_BASE (APB1_BASE + 0x18000) +#define UART3_BASE (APB1_BASE + 0x1C000) +#define I2C2_BASE (APB1_BASE + 0x20000) +#define I2S_BASE (APB1_BASE + 0x28000) +#define RIT_BASE (APB1_BASE + 0x30000) +#define MCPWM_BASE (APB1_BASE + 0x38000) +#define QEI_BASE (APB1_BASE + 0x3C000) +#define SC_BASE (APB1_BASE + 0x7C000) + +/* AHB peripherals */ +#define EMAC_BASE (AHB_BASE + 0x00000) +#define GPDMA_BASE (AHB_BASE + 0x04000) +#define GPDMACH0_BASE (AHB_BASE + 0x04100) +#define GPDMACH1_BASE (AHB_BASE + 0x04120) +#define GPDMACH2_BASE (AHB_BASE + 0x04140) +#define GPDMACH3_BASE (AHB_BASE + 0x04160) +#define GPDMACH4_BASE (AHB_BASE + 0x04180) +#define GPDMACH5_BASE (AHB_BASE + 0x041A0) +#define GPDMACH6_BASE (AHB_BASE + 0x041C0) +#define GPDMACH7_BASE (AHB_BASE + 0x041E0) +#define USB_BASE (AHB_BASE + 0x0C000) + +/* GPIOs */ +#define GPIO0_BASE (GPIO_BASE + 0x00000) +#define GPIO1_BASE (GPIO_BASE + 0x00020) +#define GPIO2_BASE (GPIO_BASE + 0x00040) +#define GPIO3_BASE (GPIO_BASE + 0x00060) +#define GPIO4_BASE (GPIO_BASE + 0x00080) + +/** + * @} + */ + + +/** @addtogroup Peripheral_declaration + * @{ + */ + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define SC (( SC_TypeDef *) SC_BASE) +#define GPIO0 (( GPIO_TypeDef *) GPIO0_BASE) +#define GPIO1 (( GPIO_TypeDef *) GPIO1_BASE) +#define GPIO2 (( GPIO_TypeDef *) GPIO2_BASE) +#define GPIO3 (( GPIO_TypeDef *) GPIO3_BASE) +#define GPIO4 (( GPIO_TypeDef *) GPIO4_BASE) +#define WDT (( WDT_TypeDef *) WDT_BASE) +#define TIM0 (( TIM_TypeDef *) TIM0_BASE) +#define TIM1 (( TIM_TypeDef *) TIM1_BASE) +#define TIM2 (( TIM_TypeDef *) TIM2_BASE) +#define TIM3 (( TIM_TypeDef *) TIM3_BASE) +#define RIT (( RIT_TypeDef *) RIT_BASE) +#define UART0 (( UART_TypeDef *) UART0_BASE) +#define UART1 (( UART1_TypeDef *) UART1_BASE) +#define UART2 (( UART_TypeDef *) UART2_BASE) +#define UART3 (( UART_TypeDef *) UART3_BASE) +#define PWM1 (( PWM_TypeDef *) PWM1_BASE) +#define I2C0 (( I2C_TypeDef *) I2C0_BASE) +#define I2C1 (( I2C_TypeDef *) I2C1_BASE) +#define I2C2 (( I2C_TypeDef *) I2C2_BASE) +#define I2S (( I2S_TypeDef *) I2S_BASE) +#define SPI (( SPI_TypeDef *) SPI_BASE) +#define RTC (( RTC_TypeDef *) RTC_BASE) +#define GPIOINT ((GPIOINT_TypeDef *) GPIOINT_BASE) +#define PINCON (( PINCON_TypeDef *) PINCON_BASE) +#define SSP0 (( SSP_TypeDef *) SSP0_BASE) +#define SSP1 (( SSP_TypeDef *) SSP1_BASE) +#define ADC (( ADC_TypeDef *) ADC_BASE) +#define DAC (( DAC_TypeDef *) DAC_BASE) +#define CANAF_RAM ((CANAF_RAM_TypeDef *)CANAF_RAM_BASE) +#define CANAF (( CANAF_TypeDef *) CANAF_BASE) +#define CANCR (( CANCR_TypeDef *) CANCR_BASE) +#define CAN1 (( CAN_TypeDef *) CAN1_BASE) +#define CAN2 (( CAN_TypeDef *) CAN2_BASE) +#define MCPWM (( MCPWM_TypeDef *) MCPWM_BASE) +#define QEI (( QEI_TypeDef *) QEI_BASE) +#define EMAC (( EMAC_TypeDef *) EMAC_BASE) +#define GPDMA (( GPDMA_TypeDef *) GPDMA_BASE) +#define DMAREQSEL (*(__IO uint32_t *) ( 0x4000C1C4)) +#define GPDMACH0 ((GPDMACH_TypeDef *) GPDMACH0_BASE) +#define GPDMACH1 ((GPDMACH_TypeDef *) GPDMACH1_BASE) +#define GPDMACH2 ((GPDMACH_TypeDef *) GPDMACH2_BASE) +#define GPDMACH3 ((GPDMACH_TypeDef *) GPDMACH3_BASE) +#define GPDMACH4 ((GPDMACH_TypeDef *) GPDMACH4_BASE) +#define GPDMACH5 ((GPDMACH_TypeDef *) GPDMACH5_BASE) +#define GPDMACH6 ((GPDMACH_TypeDef *) GPDMACH6_BASE) +#define GPDMACH7 ((GPDMACH_TypeDef *) GPDMACH7_BASE) +#define USB (( USB_TypeDef *) USB_BASE) + +/** + * @} + */ + +#endif // __LPC17xx_H__ + +/* End Of File ---------------------------------------------------------------- */ diff --git a/embedded/arch/arm/mach-lpc17xx/defines/Makefile b/embedded/arch/arm/mach-lpc17xx/defines/Makefile new file mode 100644 index 0000000..76b56fd --- /dev/null +++ b/embedded/arch/arm/mach-lpc17xx/defines/Makefile @@ -0,0 +1,14 @@ +# Generic directory or leaf node makefile for OCERA make framework + +ifndef MAKERULES_DIR +MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) ) +endif + +ifeq ($(MAKERULES_DIR),) +all : default +.DEFAULT:: + @echo -e "\nThe Makefile.rules has not been found in this or parent directory\n" +else +include $(MAKERULES_DIR)/Makefile.rules +endif + diff --git a/embedded/arch/arm/mach-lpc17xx/defines/Makefile.omk b/embedded/arch/arm/mach-lpc17xx/defines/Makefile.omk new file mode 100644 index 0000000..8a43b18 --- /dev/null +++ b/embedded/arch/arm/mach-lpc17xx/defines/Makefile.omk @@ -0,0 +1,3 @@ +# -*- makefile -*- + +include_HEADERS = LPC17xx.h core_cm3.h lpcUSB.h diff --git a/embedded/arch/arm/mach-lpc17xx/defines/core_cm3.h b/embedded/arch/arm/mach-lpc17xx/defines/core_cm3.h new file mode 100644 index 0000000..b294e3d --- /dev/null +++ b/embedded/arch/arm/mach-lpc17xx/defines/core_cm3.h @@ -0,0 +1,978 @@ +/****************************************************************************//** + * @file : core_cm3.h + * @brief : CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version : V1.20 simplified for GCC only + * @date : 31. March 2010 + *---------------------------------------------------------------------------- + * + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * ARM Limited (ARM) is supplying this software for use with Cortex-Mx + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CM3_CORE_H__ +#define __CM3_CORE_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + +/** + * Lint configuration \n + * ----------------------- \n + * + * The following Lint messages will be suppressed and not shown: \n + * \n + * --- Error 10: --- \n + * register uint32_t __regBasePri __asm("basepri"); \n + * Error 10: Expecting ';' \n + * \n + * --- Error 530: --- \n + * return(__regBasePri); \n + * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n + * \n + * --- Error 550: --- \n + * __regBasePri = (basePri & 0x1ff); \n + * } \n + * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n + * \n + * --- Error 754: --- \n + * uint32_t RESERVED0[24]; \n + * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced \n + * \n + * --- Error 750: --- \n + * #define __CM3_CORE_H__ \n + * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n + * \n + * --- Error 528: --- \n + * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n + * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n + * \n + * --- Error 751: --- \n + * } InterruptType_Type; \n + * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n + * \n + * \n + * Note: To re-enable a Message, insert a space before 'lint' * \n + * + */ + +/*lint -save */ +/*lint -e10 */ +/*lint -e530 */ +/*lint -e550 */ +/*lint -e754 */ +/*lint -e750 */ +/*lint -e528 */ +/*lint -e751 */ + + +#include /* Include standard types */ + +#ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ +#endif + + + + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ + +#ifdef __cplusplus +#define __I volatile /*!< defines 'read only' permissions */ +#else +#define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ + + +/* System Reset */ +#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */ +#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */ +#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */ +#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */ + +/* Core Debug */ +#define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */ +#define ITM_TCR_ITMENA 1 /*!< ITM enable */ + + + + +/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Software Trigger Interrupt Register */ +} NVIC_Type; + + +/* memory mapping struct for System Control Block */ +typedef struct +{ + __I uint32_t CPUID; /*!< CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Interrupt Control State Register */ + __IO uint32_t VTOR; /*!< Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< System Control Register */ + __IO uint32_t CCR; /*!< Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Hard Fault Status Register */ + __IO uint32_t DFSR; /*!< Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Mem Manage Address Register */ + __IO uint32_t BFAR; /*!< Bus Fault Address Register */ + __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Processor Feature Register */ + __I uint32_t DFR; /*!< Debug Feature Register */ + __I uint32_t ADR; /*!< Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< ISA Feature Register */ +} SCB_Type; + + +/* memory mapping struct for SysTick */ +typedef struct +{ + __IO uint32_t CTRL; /*!< SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< SysTick Current Value Register */ + __I uint32_t CALIB; /*!< SysTick Calibration Register */ +} SysTick_Type; + + +/* memory mapping structur for ITM */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __IO uint32_t IWR; /*!< ITM Integration Write Register */ + __IO uint32_t IRR; /*!< ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __IO uint32_t LAR; /*!< ITM Lock Access Register */ + __IO uint32_t LSR; /*!< ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< ITM Product ID Registers */ + __I uint32_t PID5; + __I uint32_t PID6; + __I uint32_t PID7; + __I uint32_t PID0; + __I uint32_t PID1; + __I uint32_t PID2; + __I uint32_t PID3; + __I uint32_t CID0; + __I uint32_t CID1; + __I uint32_t CID2; + __I uint32_t CID3; +} ITM_Type; + + +/* memory mapped struct for Interrupt Type */ +typedef struct +{ + uint32_t RESERVED0; + __I uint32_t ICTR; /*!< Interrupt Control Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Auxiliary Control Register */ +#else + uint32_t RESERVED1; +#endif +} InterruptType_Type; + + +/* Memory Protection Unit */ +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) +typedef struct +{ + __I uint32_t TYPE; /*!< MPU Type Register */ + __IO uint32_t CTRL; /*!< MPU Control Register */ + __IO uint32_t RNR; /*!< MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; +#endif + + +/* Core Debug Register */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ + +#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ +#endif + + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +/* ################### Compiler specific Intrinsics ########################### */ + +/* GNU gcc specific functions */ + +static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } +static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } + +static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } +static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } + +static __INLINE void __NOP() { __ASM volatile ("nop"); } +static __INLINE void __WFI() { __ASM volatile ("wfi"); } +static __INLINE void __WFE() { __ASM volatile ("wfe"); } +static __INLINE void __SEV() { __ASM volatile ("sev"); } +static __INLINE void __ISB() { __ASM volatile ("isb"); } +static __INLINE void __DSB() { __ASM volatile ("dsb"); } +static __INLINE void __DMB() { __ASM volatile ("dmb"); } +static __INLINE void __CLREX() { __ASM volatile ("clrex"); } + + +/** + * @brief Return the Process Stack Pointer + * + * @param none + * @return uint32_t ProcessStackPointer + * + * Return the actual process stack pointer + */ +static __INLINE uint32_t __get_PSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param uint32_t Process Stack Pointer + * @return none + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) ); +} + +/** + * @brief Return the Main Stack Pointer + * + * @param none + * @return uint32_t Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +static __INLINE uint32_t __get_MSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param uint32_t Main Stack Pointer + * @return none + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +static __INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) ); +} + +/** + * @brief Return the Base Priority value + * + * @param none + * @return uint32_t BasePriority + * + * Return the content of the base priority register + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** + * @brief Set the Base Priority value + * + * @param uint32_t BasePriority + * @return none + * + * Set the base priority register + */ +static __INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + +/** + * @brief Return the Priority Mask value + * + * @param none + * @return uint32_t PriMask + * + * Return the state of the priority mask bit from the priority mask + * register + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** + * @brief Set the Priority Mask value + * + * @param uint32_t PriMask + * @return none + * + * Set the priority mask bit in the priority mask register + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + + +/** + * @brief Return the Fault Mask value + * + * @param none + * @return uint32_t FaultMask + * + * Return the content of the fault mask register + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** + * @brief Set the Fault Mask value + * + * @param uint32_t faultMask value + * @return none + * + * Set the fault mask register + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +/** + * @brief Return the Control Register value +* +* @param none +* @return uint32_t Control value + * + * Return the content of the control register + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Control Register value + * + * @param uint32_t Control value + * @return none + * + * Set the control register + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + +/** + * @brief Reverse byte order in integer value + * + * @param uint32_t value to reverse + * @return uint32_t reversed value + * + * Reverse byte order in integer value + */ +static __INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param uint16_t value to reverse + * @return uint32_t reversed value + * + * Reverse byte order in unsigned short value + */ +static __INLINE uint32_t __REV16(uint16_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * Reverse byte order in signed short value with sign extension to integer + * + * @param int16_t value to reverse + * @return int32_t reversed value + * + * @brief Reverse byte order in signed short value with sign extension to integer + */ +static __INLINE int32_t __REVSH(int16_t value) +{ + uint32_t result=0; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse bit order of value + * + * @param uint32_t value to reverse + * @return uint32_t reversed value + * + * Reverse bit order of value + */ +static __INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief LDR Exclusive + * + * @param uint8_t* address + * @return uint8_t value of (*address) + * + * Exclusive LDR command + */ +static __INLINE uint8_t __LDREXB(uint8_t *addr) +{ + uint8_t result=0; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive + * + * @param uint16_t* address + * @return uint16_t value of (*address) + * + * Exclusive LDR command + */ +static __INLINE uint16_t __LDREXH(uint16_t *addr) +{ + uint16_t result=0; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive + * + * @param uint32_t* address + * @return uint32_t value of (*address) + * + * Exclusive LDR command + */ +static __INLINE uint32_t __LDREXW(uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief STR Exclusive + * + * @param uint8_t *address + * @param uint8_t value to store + * @return uint32_t successful / failed + * + * Exclusive STR command + */ +static __INLINE uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive + * + * @param uint16_t *address + * @param uint16_t value to store + * @return uint32_t successful / failed + * + * Exclusive STR command + */ +static __INLINE uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive + * + * @param uint32_t *address + * @param uint32_t value to store + * @return uint32_t successful / failed + * + * Exclusive STR command + */ +static __INLINE uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/* ########################## NVIC functions #################################### */ + + +/** + * @brief Set the Priority Grouping in NVIC Interrupt Controller + * + * @param uint32_t priority_grouping is priority grouping field + * @return none + * + * Set the priority grouping field using the required unlock sequence. + * The parameter priority_grouping is assigned to the field + * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */ + reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (PriorityGroupTmp << 8))); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + +/** + * @brief Get the Priority Grouping from NVIC Interrupt Controller + * + * @param none + * @return uint32_t priority grouping field + * + * Get the priority grouping from NVIC Interrupt Controller. + * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR >> 8) & 0x07); /* read priority grouping field */ +} + +/** + * @brief Enable Interrupt in NVIC Interrupt Controller + * + * @param IRQn_Type IRQn specifies the interrupt number + * @return none + * + * Enable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + +/** + * @brief Disable the interrupt line for external interrupt specified + * + * @param IRQn_Type IRQn is the positive number of the external interrupt + * @return none + * + * Disable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + +/** + * @brief Read the interrupt pending bit for a device specific interrupt source + * + * @param IRQn_Type IRQn is the number of the device specifc interrupt + * @return uint32_t 1 if pending interrupt else 0 + * + * Read the pending register in NVIC and return 1 if its status is pending, + * otherwise it returns 0 + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + +/** + * @brief Set the pending bit for an external interrupt + * + * @param IRQn_Type IRQn is the Number of the interrupt + * @return none + * + * Set the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + +/** + * @brief Clear the pending bit for an external interrupt + * + * @param IRQn_Type IRQn is the Number of the interrupt + * @return none + * + * Clear the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + +/** + * @brief Read the active bit for an external interrupt + * + * @param IRQn_Type IRQn is the Number of the interrupt + * @return uint32_t 1 if active else 0 + * + * Read the active register in NVIC and returns 1 if its status is active, + * otherwise it returns 0. + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + +/** + * @brief Set the priority for an interrupt + * + * @param IRQn_Type IRQn is the Number of the interrupt + * @param priority is the priority for the interrupt + * @return none + * + * Set the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. \n + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + +/** + * @brief Read the priority for an interrupt + * + * @param IRQn_Type IRQn is the Number of the interrupt + * @return uint32_t priority is the priority for the interrupt + * + * Read the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * The returned priority value is automatically aligned to the implemented + * priority bits of the microcontroller. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** + * @brief Encode the priority for an interrupt + * + * @param uint32_t PriorityGroup is the used priority group + * @param uint32_t PreemptPriority is the preemptive priority value (starting from 0) + * @param uint32_t SubPriority is the sub priority value (starting from 0) + * @return uint32_t the priority for the interrupt + * + * Encode the priority for an interrupt with the given priority group, + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The returned priority value can be used for NVIC_SetPriority(...) function + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** + * @brief Decode the priority of an interrupt + * + * @param uint32_t Priority the priority for the interrupt + * @param uint32_t PrioGroup is the used priority group + * @param uint32_t* pPreemptPrio is the preemptive priority value (starting from 0) + * @param uint32_t* pSubPrio is the sub priority value (starting from 0) + * @return none + * + * Decode an interrupt priority value with the given priority group to + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The priority value can be retrieved with NVIC_GetPriority(...) function + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + + +/* ################################## SysTick function ############################################ */ + +#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) + +/* SysTick constants */ +#define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */ +#define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */ +#define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */ +#define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */ + +/** + * @brief Initialize and start the SysTick counter and its interrupt. + * + * @param uint32_t ticks is the number of ticks between two interrupts + * @return none + * + * Initialise the system tick timer and its interrupt and start the + * system tick timer / counter in free running mode to generate + * periodical interrupts. + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = (0x00); /* Load the SysTick Counter Value */ + SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<DEMCR & CoreDebug_DEMCR_TRCENA) && + (ITM->TCR & ITM_TCR_ITMENA) && + (ITM->TER & (1UL << 0)) ) + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + +#ifdef __cplusplus +} +#endif + +#endif /* __CM3_CORE_H__ */ + +/*lint -restore */ diff --git a/embedded/arch/arm/mach-lpc17xx/defines/lpc17xx-um2reg.sh b/embedded/arch/arm/mach-lpc17xx/defines/lpc17xx-um2reg.sh new file mode 100644 index 0000000..2e11eed --- /dev/null +++ b/embedded/arch/arm/mach-lpc17xx/defines/lpc17xx-um2reg.sh @@ -0,0 +1,12 @@ +#!/bin/sh + +#pdftotext -nopgbrk user.manual.lpc17xx.pdf lpc17xx-um.txt + +# 10.1.1 USB Clock Control register (USBClkCtrl - 0x5000 CFF4) +# #define USBDevIntSt_o 0x0000 /* USB Device Interrupt Status (RO) */ +# #define USBDevIntSt (*(REG32*)(USB_REGS_BASE+USBDevIntSt_o)) + +cat lpc17xx-um.txt | \ + sed -n -e 's/^[0-9.]* \+\([^(]*\) \+(\([^ ]*\) - 0x5000 C\([^)]*\)).*$/\3@#define \2_o\t0x0\3\t\/* \1 *\/\nx\3@#define \2\t(*(REG32*)(USB_REGS_BASE+\2_o))/p' | \ + sort -u | sed -e 's/^.*@\(.*\)$/\1/' + diff --git a/embedded/arch/arm/mach-lpc17xx/defines/lpcUSB.h b/embedded/arch/arm/mach-lpc17xx/defines/lpcUSB.h new file mode 100644 index 0000000..0c7cd41 --- /dev/null +++ b/embedded/arch/arm/mach-lpc17xx/defines/lpcUSB.h @@ -0,0 +1,366 @@ +/****************************************************************************** + * + * $RCSfile$ + * $Revision$ + * + * Header file for Philips LPC17xx USB enabled ARM Processors + * Copyright 2006-2009 Pavel Pisa + * Based on same author code for LPC214x + * + * No guarantees, warrantees, or promises, implied or otherwise. + * May be used for hobby or commercial purposes provided copyright + * notice remains intact or GPL license is applied. + * + *****************************************************************************/ + +#ifndef _lpcUSB_H +#define _lpcUSB_H + +#if !defined(REG_8) || !defined(REG16) || !defined(REG32) +#define REG_8 volatile unsigned char +#define REG16 volatile unsigned short +#define REG32 volatile unsigned long +#endif + +/* USBIntSt - USB Interrupt Status (R/W) */ +#define USB_INT_REQ_LP (1<<0) /*Low priority interrupt line status (RO) */ +#define USB_INT_REQ_HP (1<<1) /*High priority interrupt line status. (RO) */ +#define USB_INT_REQ_DMA (1<<2) /*DMA interrupt line status. This bit is read only. (LPC2146/8 only) */ +#define USB_need_clock (1<<8) /*USB need clock indicator*/ +#define USB_EN_USB_INTS (1<<31) /*Enable all USB interrupts*/ + +/* USB Host Controller Registers */ +#define HcControlHeadED_o 0x0020 /* PADDR of 1st EP desc. of control list (R/W) */ +#define HcControlCurrentED_o 0x0024 /* PADDR of curr. EP desc. of control list (R/W) */ +#define HcBulkHeadED_o 0x0028 /* PADDR of 1st EP desc. of bulk list (R/W) */ +#define HcBulkCurrentED_o 0x002C /* PADDR of curr. EP desc. of bulk list (R/W) */ +#define HcDoneHead_o 0x0030 /* PADDR of the last desct added to Done q. (R) */ +#define HcFmInterval_o 0x0034 /* full speed max frame time (R/W) */ +#define HcFmRemaining_o 0x0038 /* 14-bit counter of remaining in curr. frame (R) */ +#define HcFmNumber_o 0x003C /* 16-bit HC and HDC timing counter (R) */ +#define HcPeriodicStart_o 0x0040 /* 14-bit earliest time to start HC periodic list (R/W) */ +#define HcLSThreshold_o 0x0044 /* 11-bit HC timer for 8-byte LS packet before EOF (R/W) */ +#define HcRhDescriptorA_o 0x0048 /* Characteristics of the root hub - 1st part (R/W) */ +#define HcRhDescriptorB_o 0x004C /* Characteristics of the root hub - 2nd part (R/W) */ +#define HcRhStatus_o 0x0050 /* D-word hub info (low - status, high change) (R/W) */ +#define USB_MODULE_ID_o 0x00FC /* USB Module ID 0x3505yyzz - yy .. ver, zz .. rev (R) */ + +/* USB On-The-Go Registers */ +#define OTGIntSt_o 0x0100 /* OTG Interrupt Status (RO) */ +#define OTGIntEn_o 0x0104 /* OTG Interrupt Enable (R/W) */ +#define OTGIntSet_o 0x0108 /* OTG Interrupt Clear (WO) */ +#define OTGIntClr_o 0x010C /* OTG Interrupt Clear (WO) */ +#define OTGStCtrl_o 0x0110 /* OTG Status and Control (R/W) */ +#define OTGTmr_o 0x0114 /* OTG Timer (R/W) */ + +/* Device interrupt registers */ +#define USBDevIntSt_o 0x0200 /* USB Device Interrupt Status(R0) */ +#define USBDevIntEn_o 0x0204 /* USB Device Interrupt Enable (R/W) */ +#define USBDevIntClr_o 0x0208 /* USB Device Interrupt Clear (WO) */ +#define USBDevIntSet_o 0x020C /* USB Device Interrupt Set (WO) */ +#define USBDevInt_FRAME (1<<0) /*Frame interrupt @1kHz for ISO transfers*/ +#define USBDevInt_EP_FAST (1<<1) /*Fast interrupt transfer for the endpoint*/ +#define USBDevInt_EP_SLOW (1<<2) /*Slow interrupt transfer for the endpoint*/ +#define USBDevInt_DEV_STAT (1<<3) /*USB Bus reset, USB suspend change or Connect occured*/ +#define USBDevInt_CCEMTY (1<<4) /*Command code register is empty/ready for CMD*/ +#define USBDevInt_CDFULL (1<<5) /*Command data register is full/data available*/ +#define USBDevInt_RxENDPKT (1<<6) /*Current packet in the FIFO is transferred to the CPU*/ +#define USBDevInt_TxENDPKT (1<<7) /*TxPacket bytes written to FIFO*/ +#define USBDevInt_EP_RLZED (1<<8) /*Endpoints realized after Maxpacket size update*/ +#define USBDevInt_ERR_INT (1<<9) /*Error Interrupt - Use Read Error Status Command 0xFB*/ +#define USBDevIntPri_o 0x022C /* USB Device Interrupt Priority (WO) */ +#define USBDevIntPri_FRAME (1<<0) /*0/1 FRAME int routed to the low/high priority interrupt line*/ +#define USBDevIntPri_EP_FAST (1<<1) /*0/1 EP_FAST int routed to the low/high priority line*/ + +/* Endpoint interrupt registers - bits corresponds to EP0 to EP31 */ +#define USBEpIntSt_o 0x0230 /* USB Endpoint Interrupt Status (R0) */ +#define USBEpIntEn_o 0x0234 /* USB Endpoint Interrupt Enable (R/W) */ +#define USBEpIntClr_o 0x0238 /* USB Endpoint Interrupt Clear (WO) */ +#define USBEpIntSet_o 0x023C /* USB Endpoint Interrupt Set (WO) */ +#define USBEpIntPri_o 0x0240 /* USB Endpoint Interrupt Priority (WO) */ +/* Endpoint realization registers */ +#define USBReEp_o 0x0244 /* USB Realize Endpoint (R/W) */ +#define USBEpInd_o 0x0248 /* USB Endpoint Index (RO) */ +#define USBEpInd_Ind 0x001F /* Index for subsequent USBMaxPSize (WO) */ +#define USBMaxPSize_o 0x024C /* USB MaxPacketSize (R/W) */ +#define USBMaxPSize_Size 0x03FF /* The maximum packet size value */ +/* USB transfer registers */ +#define USBRxData_o 0x0218 /* USB Receive Data (RO) */ +#define USBRxPLen_o 0x0220 /* USB Receive Packet Length (RO) */ +#define USBRxPLen_PKT_LNGTH (0x03FF) /*Remaining amount of bytes to be read from RAM*/ +#define USBRxPLen_DV (1<<10) /*Data valid. 0 only for error ISO packet*/ +#define USBRxPLen_PKT_RDY (1<<11) /*Packet length valid and packet is ready for reading*/ +#define USBTxData_o 0x021C /* USB Transmit Data (WO) */ +#define USBTxPLen_o 0x0224 /* USB Transmit Packet Length (WO) */ +#define USBTxPLen_PKT_LNGTH (0x03FF) /*Remaining amount of bytes to be written to the EP_RAM*/ +#define USBCtrl_o 0x0228 /* USB Control (R/W) */ +#define USBCtrl_RD_EN (1<<0) /*Read mode control*/ +#define USBCtrl_WR_EN (1<<1) /*Write mode control*/ +#define USBCtrl_LOG_ENDPOINT 0x003C /*Logical Endpoint number*/ +/* Command registers */ +#define USBCmdCode_o 0x0210 /* USB Command Code (WO) */ +#define USBCmdCode_CMD_PHASE 0x0000FF00 /*The command phase*/ +#define USBCmdCode_CMD_CODE 0x00FF0000 /*The code for the command*/ +#define USBCmdData_o 0x0214 /* USB Command Data (RO) */ +/* DMA registers (LPC2146/8 and LPC17xx only) */ +#define USBDMARSt_o 0x0250 /* USB DMA Request Status (RO) */ +#define USBDMARClr_o 0x0254 /* USB DMA Request Clear (WO) */ +#define USBDMARSet_o 0x0258 /* USB DMA Request Set (WO) */ +#define USBUDCAH_o 0x0280 /* USB UDCA Head (R/W) has to be aligned to 128 bytes */ +#define USBEpDMASt_o 0x0284 /* USB Endpoint DMA Status (RO) */ +#define USBEpDMAEn_o 0x0288 /* USB Endpoint DMA Enable (WO) */ +#define USBEpDMADis_o 0x028C /* USB Endpoint DMA Disable (WO) */ +#define USBDMAIntSt_o 0x0290 /* USB DMA Interrupt Status (RO) */ +#define USBDMAIntEn_o 0x0294 /* USB DMA Interrupt Enable (R/W) */ +#define USBDMAInt_EoT (1<<0) /*End of Transfer Interrupt bit, 1 if USBEoTIntSt != 0*/ +#define USBDMAInt_New_DD_Rq (1<<1) /* New DD Request Interrupt bit, 1 if USBNDDRIntSt != 0*/ +#define USBDMAInt_SysError (1<<2) /*System Error Interrupt bit, 1 if USBSysErrIntSt != 0*/ +#define USBEoTIntSt_o 0x02A0 /* USB End of Transfer Interrupt Status (RO) */ +#define USBEoTIntClr_o 0x02A4 /* USB End of Transfer Interrupt Clear (WO) */ +#define USBEoTIntSet_o 0x02A8 /* USB End of Transfer Interrupt Set (WO) */ +#define USBNDDRIntSt_o 0x02AC /* USB New DD Request Interrupt Status (RO) */ +#define USBNDDRIntClr_o 0x02B0 /* USB New DD Request Interrupt Clear (WO) */ +#define USBNDDRIntSet_o 0x02B4 /* USB New DD Request Interrupt Set (WO) */ +#define USBSysErrIntSt_o 0x02B8 /* USB System Error Interrupt Status (RO) */ +#define USBSysErrIntClr_o 0x02BC /* USB System Error Interrupt Clear (WO) */ +#define USBSysErrIntSet_o 0x02C0 /* USB System Error Interrupt Set (WO) */ + +/* USB I2C registers */ +#define USB_I2C_RX_o 0x0300 /* I2C Receive (RO) */ +#define USB_I2C_TX_o 0x0300 /* I2C Transmit (WO) */ +#define USB_I2C_STS_o 0x0304 /* I2C Status (RO) */ +#define USB_I2C_CTL_o 0x0308 /* I2C Control (R/W) */ +#define USB_I2C_CLKHI_o 0x030C /* I2C Clock High (R/W) */ +#define USB_I2C_CLKLO_o 0x0310 /* I2C Clock Low (WO) */ + +/* Clock control registers */ +#define OTGClkCtrl_o 0x0FF4 /* OTG Clock Control (R/W) */ +#define USBClkCtrl_o 0x0FF4 /* USB Clock Control (R/W) */ +#define OTGClkSt_o 0x0FF8 /* OTG Clock Status (RO) */ +#define USBClkSt_o 0x0FF8 /* USB Clock Status (RO) */ + +/* Command Codes */ +#define USB_CMD_SET_ADDR 0x00D00500 +#define USB_CMD_CFG_DEV 0x00D80500 +#define USB_CMD_SET_MODE 0x00F30500 +#define USB_CMD_RD_FRAME 0x00F50500 +#define USB_DAT_RD_FRAME 0x00F50200 +#define USB_CMD_RD_TEST 0x00FD0500 +#define USB_DAT_RD_TEST 0x00FD0200 +#define USB_CMD_SET_DEV_STAT 0x00FE0500 +#define USB_CMD_GET_DEV_STAT 0x00FE0500 +#define USB_DAT_GET_DEV_STAT 0x00FE0200 +#define USB_CMD_GET_ERR_CODE 0x00FF0500 +#define USB_DAT_GET_ERR_CODE 0x00FF0200 +#define USB_CMD_RD_ERR_STAT 0x00FB0500 +#define USB_DAT_RD_ERR_STAT 0x00FB0200 +#define USB_DAT_WR_BYTE(x) (0x00000100 | ((x) << 16)) +#define USB_CMD_SEL_EP(x) (0x00000500 | ((x) << 16)) +#define USB_DAT_SEL_EP(x) (0x00000200 | ((x) << 16)) +#define USB_CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16)) +#define USB_DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16)) +#define USB_CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16)) +#define USB_CMD_CLR_BUF 0x00F20500 +#define USB_DAT_CLR_BUF 0x00F20200 +#define USB_CMD_VALID_BUF 0x00FA0500 + +/* Device Address Register Definitions */ +#define USBC_DEV_ADDR_MASK 0x7F +#define USBC_DEV_EN 0x80 + +/* Device Configure Register Definitions */ +#define USBC_CONF_DEVICE 0x01 + +/* Device Mode Register Definitions */ +#define USBC_AP_CLK 0x01 +#define USBC_INAK_CI 0x02 +#define USBC_INAK_CO 0x04 +#define USBC_INAK_II 0x08 +#define USBC_INAK_IO 0x10 +#define USBC_INAK_BI 0x20 +#define USBC_INAK_BO 0x40 + +/* Device Status Register Definitions */ +#define USBC_DEV_CON 0x01 +#define USBC_DEV_CON_CH 0x02 +#define USBC_DEV_SUS 0x04 +#define USBC_DEV_SUS_CH 0x08 +#define USBC_DEV_RST 0x10 + +/* Error Code Register Definitions */ +#define USBC_ERR_EC_MASK 0x0F +#define USBC_ERR_EA 0x10 + +/* Error Status Register Definitions */ +#define USBC_ERR_PID 0x01 +#define USBC_ERR_UEPKT 0x02 +#define USBC_ERR_DCRC 0x04 +#define USBC_ERR_TIMOUT 0x08 +#define USBC_ERR_EOP 0x10 +#define USBC_ERR_B_OVRN 0x20 +#define USBC_ERR_BTSTF 0x40 +#define USBC_ERR_TGL 0x80 + +/* Endpoint Select Register Definitions */ +#define USBC_EP_SEL_F 0x01 +#define USBC_EP_SEL_ST 0x02 +#define USBC_EP_SEL_STP 0x04 +#define USBC_EP_SEL_PO 0x08 +#define USBC_EP_SEL_EPN 0x10 +#define USBC_EP_SEL_B_1_FULL 0x20 +#define USBC_EP_SEL_B_2_FULL 0x40 + +/* Endpoint Status Register Definitions */ +#define USBC_EP_STAT_ST 0x01 +#define USBC_EP_STAT_DA 0x20 +#define USBC_EP_STAT_RF_MO 0x40 +#define USBC_EP_STAT_CND_ST 0x80 + +/* Clear Buffer Register Definitions */ +#define USBC_CLR_BUF_PO 0x01 + +typedef struct +{ + REG32 _padA[0x200]; +/* Device interrupt registers */ + REG32 DevIntSt; /* USB Device Interrupt Status (RO) 0000 */ + REG32 DevIntEn; /* USB Device Interrupt Enable (R/W) 0004 */ + REG32 DevIntClr; /* USB Device Interrupt Clear (WO) 0008 */ + REG32 DevIntSet; /* USB Device Interrupt Set (WO) 000C */ +/* Command registers */ + REG32 CmdCode; /* USB Command Code (WO) 0010 */ + REG32 CmdData; /* USB Command Data (RO) 0014 */ +/* USB transfer registers */ + REG32 RxData; /* USB Receive Data (RO) 0018 */ + REG32 TxData; /* USB Transmit Data (WO) 001C */ + REG32 RxPLen; /* USB Receive Packet Length (RO) 0020 */ + REG32 TxPLen; /* USB Transmit Packet Length (WO) 0024 */ + REG32 Ctrl; /* USB Control (R/W) 0028 */ +/* Device interrupt priority register */ + REG_8 USBDevIntPri; /* USB Device Interrupt Priority (WO) 002C */ + REG_8 _pad0[3]; +/* Endpoint interrupt registers */ + REG32 EpIntSt; /* USB Endpoint Interrupt Status (RO) 0030 */ + REG32 EpIntEn; /* USB Endpoint Interrupt Enable (R/W) 0034 */ + REG32 EpIntClr; /* USB Endpoint Interrupt Clear (WO) 0038 */ + REG32 EpIntSet; /* USB Endpoint Interrupt Set (WO) 003C */ + REG32 EpIntPri; /* USB Endpoint Priority (WO) 0040 */ +/* Endpoint realization registers */ + REG32 ReEp; /* USB Realize Endpoint (R/W) 0044 */ + REG32 EpInd; /* USB Endpoint Index (WO) 0048 */ + REG32 MaxPSize; /* USB MaxPacketSize (R/W) 004C */ +/* DMA registers (LPC2146/8 only) */ + REG32 DMARSt; /* USB DMA Request Status (RO) 0050 */ + REG32 DMARClr; /* USB DMA Request Clear (WO) 0054 */ + REG32 DMARSet; /* USB DMA Request Set (WO) 0058 */ + REG32 _pad1[9]; + REG32 UDCAH; /* USB UDCA Head (R/W) 0080 */ + REG32 EpDMASt; /* USB Endpoint DMA Status (RO) 0084 */ + REG32 EpDMAEn; /* USB Endpoint DMA Enable (WO) 0088 */ + REG32 EpDMADis; /* USB Endpoint DMA Disable (WO) 008C */ + REG32 DMAIntSt; /* USB DMA Interrupt Status (RO) 0090 */ + REG32 DMAIntEn; /* USB DMA Interrupt Enable (R/W) 0094 */ + REG32 _pad2[2]; + REG32 EoTIntSt; /* USB End of Transfer Interrupt Status (RO) 00A0 */ + REG32 EoTIntClr; /* USB End of Transfer Interrupt Clear (WO) 00A4 */ + REG32 EoTIntSet; /* USB End of Transfer Interrupt Set (WO) 00A8 */ + REG32 NDDRIntSt; /* USB New DD Request Interrupt Status (RO) 00AC */ + REG32 NDDRIntClr; /* USB New DD Request Interrupt Clear (WO) 00B0 */ + REG32 NDDRIntSet; /* USB New DD Request Interrupt Set (WO) 00B4 */ + REG32 SysErrIntSt; /* USB System Error Interrupt Status (RO) 00B8 */ + REG32 SysErrIntClr; /* USB System Error Interrupt Clear (WO) 00BC */ + REG32 SysErrIntSet; /* USB System Error Interrupt Set (WO) 00C0 */ +} usbRegs_t; + +#define USBIntSt (*(REG32*)0x400FC10) /* USB Interrupt Status (R/W) */ + +#define USB_REGS_BASE 0x5000C000UL + +#define HcControlHeadED_o 0x0020 /* PADDR of 1st EP desc. of control list (R/W) */ +#define HcControlCurrentED_o 0x0024 /* PADDR of curr. EP desc. of control list (R/W) */ +#define HcBulkHeadED_o 0x0028 /* PADDR of 1st EP desc. of bulk list (R/W) */ +#define HcBulkCurrentED_o 0x002C /* PADDR of curr. EP desc. of bulk list (R/W) */ +#define HcDoneHead_o 0x0030 /* PADDR of the last desct added to Done q. (R) */ +#define HcFmInterval_o 0x0034 /* full speed max frame time (R/W) */ +#define HcFmRemaining_o 0x0038 /* 14-bit counter of remaining in curr. frame (R) */ +#define HcFmNumber_o 0x003C /* 16-bit HC and HDC timing counter (R) */ +#define HcPeriodicStart_o 0x0040 /* 14-bit earliest time to start HC periodic list (R/W) */ +#define HcLSThreshold_o 0x0044 /* 11-bit HC timer for 8-byte LS packet before EOF (R/W) */ +#define HcRhDescriptorA_o 0x0048 /* Characteristics of the root hub - 1st part (R/W) */ +#define HcRhDescriptorB_o 0x004C /* Characteristics of the root hub - 2nd part (R/W) */ +#define HcRhStatus_o 0x0050 /* D-word hub info (low - status, high change) (R/W) */ + +#define HcControlHeadED (*(REG32*)(USB_REGS_BASE+HcControlHeadED_o)) +#define HcControlCurrentED (*(REG32*)(USB_REGS_BASE+HcControlCurrentED_o)) +#define HcBulkHeadED (*(REG32*)(USB_REGS_BASE+HcBulkHeadED_o)) +#define HcBulkCurrentED (*(REG32*)(USB_REGS_BASE+HcBulkCurrentED_o)) +#define HcDoneHead (*(REG32*)(USB_REGS_BASE+HcDoneHead_o)) +#define HcFmInterval (*(REG32*)(USB_REGS_BASE+HcFmInterval_o)) +#define HcFmRemaining (*(REG32*)(USB_REGS_BASE+HcFmRemaining_o)) +#define HcFmNumber (*(REG32*)(USB_REGS_BASE+HcFmNumber_o)) +#define HcPeriodicStart (*(REG32*)(USB_REGS_BASE+HcPeriodicStart_o)) +#define HcLSThreshold (*(REG32*)(USB_REGS_BASE+HcLSThreshold_o)) +#define HcRhDescriptorA (*(REG32*)(USB_REGS_BASE+HcRhDescriptorA_o)) +#define HcRhDescriptorB (*(REG32*)(USB_REGS_BASE+HcRhDescriptorB_o)) +#define HcRhStatus (*(REG32*)(USB_REGS_BASE+HcRhStatus_o)) + +#define USB_MODULE_ID (*(REG32*)(USB_REGS_BASE+USB_MODULE_ID_o)) + +#define OTGIntSt (*(REG32*)(USB_REGS_BASE+OTGIntSt_o)) +#define OTGIntEn (*(REG32*)(USB_REGS_BASE+OTGIntEn_o)) +#define OTGIntClr (*(REG32*)(USB_REGS_BASE+OTGIntClr_o)) +#define OTGIntSet (*(REG32*)(USB_REGS_BASE+OTGIntSet_o)) +#define OTGStCtrl (*(REG32*)(USB_REGS_BASE+OTGStCtrl_o)) +#define OTGTmr (*(REG32*)(USB_REGS_BASE+OTGTmr_o)) + +#define USBDevIntSt (*(REG32*)(USB_REGS_BASE+USBDevIntSt_o)) +#define USBDevIntEn (*(REG32*)(USB_REGS_BASE+USBDevIntEn_o)) +#define USBDevIntClr (*(REG32*)(USB_REGS_BASE+USBDevIntClr_o)) +#define USBDevIntSet (*(REG32*)(USB_REGS_BASE+USBDevIntSet_o)) +#define USBDevIntPri (*(REG32*)(USB_REGS_BASE+USBDevIntPri_o)) +#define USBEpIntSt (*(REG32*)(USB_REGS_BASE+USBEpIntSt_o)) +#define USBEpIntEn (*(REG32*)(USB_REGS_BASE+USBEpIntEn_o)) +#define USBEpIntClr (*(REG32*)(USB_REGS_BASE+USBEpIntClr_o)) +#define USBEpIntSet (*(REG32*)(USB_REGS_BASE+USBEpIntSet_o)) +#define USBEpIntPri (*(REG32*)(USB_REGS_BASE+USBEpIntPri_o)) +#define USBReEp (*(REG32*)(USB_REGS_BASE+USBReEp_o)) +#define USBEpInd (*(REG32*)(USB_REGS_BASE+USBEpInd_o)) +#define USBMaxPSize (*(REG32*)(USB_REGS_BASE+USBMaxPSize_o)) +#define USBRxData (*(REG32*)(USB_REGS_BASE+USBRxData_o)) +#define USBRxPLen (*(REG32*)(USB_REGS_BASE+USBRxPLen_o)) +#define USBTxData (*(REG32*)(USB_REGS_BASE+USBTxData_o)) +#define USBTxPLen (*(REG32*)(USB_REGS_BASE+USBTxPLen_o)) +#define USBCtrl (*(REG32*)(USB_REGS_BASE+USBCtrl_o)) +#define USBCmdCode (*(REG32*)(USB_REGS_BASE+USBCmdCode_o)) +#define USBCmdData (*(REG32*)(USB_REGS_BASE+USBCmdData_o)) +#define USBDMARSt (*(REG32*)(USB_REGS_BASE+USBDMARSt_o)) +#define USBDMARClr (*(REG32*)(USB_REGS_BASE+USBDMARClr_o)) +#define USBDMARSet (*(REG32*)(USB_REGS_BASE+USBDMARSet_o)) +#define USBUDCAH (*(REG32*)(USB_REGS_BASE+USBUDCAH_o)) +#define USBEpDMASt (*(REG32*)(USB_REGS_BASE+USBEpDMASt_o)) +#define USBEpDMAEn (*(REG32*)(USB_REGS_BASE+USBEpDMAEn_o)) +#define USBEpDMADis (*(REG32*)(USB_REGS_BASE+USBEpDMADis_o)) +#define USBDMAIntSt (*(REG32*)(USB_REGS_BASE+USBDMAIntSt_o)) +#define USBDMAIntEn (*(REG32*)(USB_REGS_BASE+USBDMAIntEn_o)) +#define USBEoTIntSt (*(REG32*)(USB_REGS_BASE+USBEoTIntSt_o)) +#define USBEoTIntClr (*(REG32*)(USB_REGS_BASE+USBEoTIntClr_o)) +#define USBEoTIntSet (*(REG32*)(USB_REGS_BASE+USBEoTIntSet_o)) +#define USBNDDRIntSt (*(REG32*)(USB_REGS_BASE+USBNDDRIntSt_o)) +#define USBNDDRIntClr (*(REG32*)(USB_REGS_BASE+USBNDDRIntClr_o)) +#define USBNDDRIntSet (*(REG32*)(USB_REGS_BASE+USBNDDRIntSet_o)) +#define USBSysErrIntSt (*(REG32*)(USB_REGS_BASE+USBSysErrIntSt_o)) +#define USBSysErrIntClr (*(REG32*)(USB_REGS_BASE+USBSysErrIntClr_o)) +#define USBSysErrIntSet (*(REG32*)(USB_REGS_BASE+USBSysErrIntSet_o)) + +#define USB_I2C_RX (*(REG32*)(USB_REGS_BASE+I2C_RX_o)) +#define USB_I2C_TX (*(REG32*)(USB_REGS_BASE+I2C_TX_o)) +#define USB_I2C_STS (*(REG32*)(USB_REGS_BASE+I2C_STS_o)) +#define USB_I2C_CTL (*(REG32*)(USB_REGS_BASE+I2C_CTL_o)) +#define USB_I2C_CLKHI (*(REG32*)(USB_REGS_BASE+I2C_CLKHI_o)) +#define USB_I2C_CLKLO (*(REG32*)(USB_REGS_BASE+I2C_CLKLO_o)) +#define OTGClkCtrl (*(REG32*)(USB_REGS_BASE+OTGClkCtrl_o)) +#define USBClkCtrl (*(REG32*)(USB_REGS_BASE+USBClkCtrl_o)) +#define OTGClkSt (*(REG32*)(USB_REGS_BASE+OTGClkSt_o)) +#define USBClkSt (*(REG32*)(USB_REGS_BASE+USBClkSt_o)) + +#endif /*_lpcUSB_H*/ diff --git a/embedded/arch/arm/mach-lpc17xx/libs/Makefile b/embedded/arch/arm/mach-lpc17xx/libs/Makefile new file mode 100644 index 0000000..76b56fd --- /dev/null +++ b/embedded/arch/arm/mach-lpc17xx/libs/Makefile @@ -0,0 +1,14 @@ +# Generic directory or leaf node makefile for OCERA make framework + +ifndef MAKERULES_DIR +MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) ) +endif + +ifeq ($(MAKERULES_DIR),) +all : default +.DEFAULT:: + @echo -e "\nThe Makefile.rules has not been found in this or parent directory\n" +else +include $(MAKERULES_DIR)/Makefile.rules +endif + diff --git a/embedded/arch/arm/mach-lpc17xx/libs/Makefile.omk b/embedded/arch/arm/mach-lpc17xx/libs/Makefile.omk new file mode 100644 index 0000000..778cdc0 --- /dev/null +++ b/embedded/arch/arm/mach-lpc17xx/libs/Makefile.omk @@ -0,0 +1,3 @@ +# -*- makefile -*- + +SUBDIRS = hal iap diff --git a/embedded/arch/arm/mach-lpc17xx/libs/hal/Makefile b/embedded/arch/arm/mach-lpc17xx/libs/hal/Makefile new file mode 100644 index 0000000..76b56fd --- /dev/null +++ b/embedded/arch/arm/mach-lpc17xx/libs/hal/Makefile @@ -0,0 +1,14 @@ +# Generic directory or leaf node makefile for OCERA make framework + +ifndef MAKERULES_DIR +MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) ) +endif + +ifeq ($(MAKERULES_DIR),) +all : default +.DEFAULT:: + @echo -e "\nThe Makefile.rules has not been found in this or parent directory\n" +else +include $(MAKERULES_DIR)/Makefile.rules +endif + diff --git a/embedded/arch/arm/mach-lpc17xx/libs/hal/Makefile.omk b/embedded/arch/arm/mach-lpc17xx/libs/hal/Makefile.omk new file mode 100644 index 0000000..cb622d3 --- /dev/null +++ b/embedded/arch/arm/mach-lpc17xx/libs/hal/Makefile.omk @@ -0,0 +1,10 @@ +# -*- makefile -*- + +lib_LIBRARIES = mach_hal + +include_HEADERS = hal_machperiph.h hal_gpio.h hal_gpio_def.h + +mach_hal_SOURCES = hal.c startup.c hal_machperiph.c hal_reserve_usb_ram.c hal_gpio.c + + + diff --git a/embedded/arch/arm/mach-lpc17xx/libs/hal/hal.c b/embedded/arch/arm/mach-lpc17xx/libs/hal/hal.c new file mode 100644 index 0000000..facf422 --- /dev/null +++ b/embedded/arch/arm/mach-lpc17xx/libs/hal/hal.c @@ -0,0 +1,53 @@ +#include +#include +#include + +#define IRQ_TABLE_SIZE (16+33) + +__attribute__ ((section(".irqarea"))) +irq_handler_t *irq_handler_table_start[IRQ_TABLE_SIZE]; +void *irq_context_table_start[IRQ_TABLE_SIZE]; + +void **irq_context_table = irq_context_table_start; +irq_handler_t **irq_handler_table = irq_handler_table_start; +unsigned int irq_table_size = IRQ_TABLE_SIZE; + +void disable_irq(unsigned int irqnum) +{ + NVIC_DisableIRQ(irqnum); + __memory_barrier(); +} +void enable_irq(unsigned int irqnum) +{ + __memory_barrier(); + NVIC_EnableIRQ(irqnum); +} + +int +request_irq(unsigned int irqnum, irq_handler_t *handler, unsigned long flags, + const char *name, void *context) +{ + unsigned int irqidx=irq_irqnum2irqidx(irqnum); + + if (irqidx>=irq_table_size) + return -1; + + disable_irq(irqnum); + irq_handler_table[irqidx]=handler; + irq_context_table[irqidx]=context; + enable_irq(irqnum); + + return 0; +} + +void free_irq(unsigned int irqnum, void *context) +{ + unsigned int irqidx=irq_irqnum2irqidx(irqnum); + + if (irqidx>=irq_table_size) + return; + + disable_irq(irqnum); + irq_handler_table[irqidx]=NULL; + irq_context_table[irqidx]=NULL; +} \ No newline at end of file diff --git a/embedded/arch/arm/mach-lpc17xx/libs/hal/hal_gpio.c b/embedded/arch/arm/mach-lpc17xx/libs/hal/hal_gpio.c new file mode 100644 index 0000000..b06ea7f --- /dev/null +++ b/embedded/arch/arm/mach-lpc17xx/libs/hal/hal_gpio.c @@ -0,0 +1,72 @@ +#include +#include + +#include + +int hal_pin_conf_fnc(unsigned gpio, int fnc) +{ + __IO uint32_t *p = &(PINCON->PINSEL0); + uint32_t mask; + + if(fnc & PORT_CONF_FNC_MASK) + fnc = __mfld2val(PORT_CONF_FNC_MASK, fnc); + + p += hal_gpio_get_port_num(gpio)*2; + if(gpio & 0x10) + p++; + gpio &= 0x0f; + gpio *= 2; + mask = 3 << gpio; + + *p = (*p & ~mask) | ((fnc << gpio) & mask); + + return 0; +} + +int hal_pin_conf_mode(unsigned gpio, int mode) +{ + __IO uint32_t *p = &(PINCON->PINMODE0); + uint32_t mask; + + if(mode & PORT_CONF_MODE_MASK) + mode = __mfld2val(PORT_CONF_MODE_MASK, mode); + + p += hal_gpio_get_port_num(gpio)*2; + if(gpio & 0x10) + p++; + gpio &= 0x0f; + gpio *= 2; + mask = 3 << gpio; + + *p = (*p & ~mask) | ((mode << gpio) & mask); + + return 0; +} + +int hal_pin_conf_od(unsigned gpio, int od) +{ + uint32_t mask = 1 << (gpio & 0x1f); + + if(od) + (&(PINCON->PINMODE_OD0))[hal_gpio_get_port_num(gpio)] |= mask; + else + (&(PINCON->PINMODE_OD0))[hal_gpio_get_port_num(gpio)] &= ~mask; + + return 0; +} + +int hal_pin_conf_set(unsigned gpio, int conf) +{ + gpio &= ~PORT_CONF_MASK; + hal_pin_conf_mode(gpio, conf & PORT_CONF_MODE_MASK); + hal_pin_conf_od(gpio, conf & PORT_CONF_OD_MASK); + if(conf & PORT_CONF_SET_DIR) { + if((conf & PORT_CONF_DIR_MASK) == (PORT_CONF_DIR_IN & PORT_CONF_DIR_MASK)) + hal_gpio_direction_input(gpio); + else + hal_gpio_direction_output(gpio, conf & PORT_CONF_INIT_HIGH); + } + hal_pin_conf_fnc(gpio, conf & PORT_CONF_FNC_MASK); + + return 0; +} diff --git a/embedded/arch/arm/mach-lpc17xx/libs/hal/hal_gpio.h b/embedded/arch/arm/mach-lpc17xx/libs/hal/hal_gpio.h new file mode 100644 index 0000000..17bb269 --- /dev/null +++ b/embedded/arch/arm/mach-lpc17xx/libs/hal/hal_gpio.h @@ -0,0 +1,75 @@ +#ifndef _HAL_GPIO_H_ +#define _HAL_GPIO_H_ + +#include +#include +#include + +#define HAL_GPIO_PORT_BITS 3 + +static inline +GPIO_TypeDef *hal_gpio_get_port_base(unsigned port) +{ + char *p = (char*)GPIO0_BASE; + p += ((char*)GPIO1_BASE - (char*)GPIO0_BASE) * port; + return (GPIO_TypeDef *)p; +} + +static inline +unsigned hal_gpio_get_port_num(unsigned gpio) +{ + gpio >>= PORT_SHIFT; + return gpio & ((1 << HAL_GPIO_PORT_BITS) - 1); +} + +static inline +GPIO_TypeDef *hal_gpio_get_base(unsigned gpio) +{ + return hal_gpio_get_port_base(hal_gpio_get_port_num(gpio)); +} + +static inline +int hal_gpio_get_value(unsigned gpio) +{ + return ((hal_gpio_get_base(gpio)->FIOPIN) >> (gpio & 0x1f)) & 1; +} + +static inline +void hal_gpio_set_value(unsigned gpio, int value) +{ + if(value) + hal_gpio_get_base(gpio)->FIOSET = 1 << (gpio & 0x1f); + else + hal_gpio_get_base(gpio)->FIOCLR = 1 << (gpio & 0x1f); +} + +static inline +int hal_gpio_direction_input(unsigned gpio) +{ + hal_gpio_get_base(gpio)->FIODIR &= ~(1 << (gpio & 0x1f)); + return 0; +} + +static inline +int hal_gpio_direction_output(unsigned gpio, int value) +{ + hal_gpio_set_value(gpio, value); + hal_gpio_get_base(gpio)->FIODIR |= (1 << (gpio & 0x1f)); + return 0; +} + +int hal_pin_conf_fnc(unsigned gpio, int fnc); + +int hal_pin_conf_mode(unsigned gpio, int mode); + +int hal_pin_conf_od(unsigned gpio, int od); + +int hal_pin_conf_set(unsigned gpio, int conf); + +static inline +int hal_pin_conf(unsigned gpio) +{ + return hal_pin_conf_set(gpio, gpio); +} + +#endif /*_HAL_GPIO_H_*/ diff --git a/embedded/arch/arm/mach-lpc17xx/libs/hal/hal_gpio_def.h b/embedded/arch/arm/mach-lpc17xx/libs/hal/hal_gpio_def.h new file mode 100644 index 0000000..b458151 --- /dev/null +++ b/embedded/arch/arm/mach-lpc17xx/libs/hal/hal_gpio_def.h @@ -0,0 +1,53 @@ +#ifndef _HAL_GPIO_DEF_H_ +#define _HAL_GPIO_DEF_H_ + +#ifndef PORT_SHIFT +#define PORT_SHIFT 5 +#endif +#ifndef PORT_PIN +#define PORT_PIN(p,n,conf) (((p)< +#include +#include + + +/*---------------------------------------------------------------------------- + Check the register settings + *----------------------------------------------------------------------------*/ +#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) +#define CHECK_RSVD(val, mask) (val & mask) + +/* Clock Configuration -------------------------------------------------------*/ +#if (CHECK_RSVD((SCS_Val), ~0x00000030)) + #error "SCS: Invalid values of reserved bits!" +#endif + +#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2)) + #error "CLKSRCSEL: Value out of range!" +#endif + +#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF)) + #error "PLL0CFG: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F)) + #error "PLL1CFG: Invalid values of reserved bits!" +#endif + +#if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2))) + #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!" +#endif + +#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F)) + #error "USBCLKCFG: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00)) + #error "PCLKSEL0: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300)) + #error "PCLKSEL1: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PCONP_Val), 0x10100821)) + #error "PCONP: Invalid values of reserved bits!" +#endif + +/* Flash Accelerator Configuration -------------------------------------------*/ +#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F)) + #error "FLASHCFG: Invalid values of reserved bits!" +#endif + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +unsigned int system_frequency = IRC_OSC; /*!< System Clock Frequency (Core Clock) */ + +void system_clock_init(void) +{ +#if (CLOCK_SETUP) /* Clock Setup */ + SC->SCS = SCS_Val; + if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */ + while ((SC->SCS & (1 << 6)) == 0); /* Wait for Oscillator to be ready */ + } + +#if (PLL0_SETUP) + SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */ + SC->PLL0CFG = PLL0CFG_Val; + SC->PLL0CON = 0x01; /* PLL0 Enable */ + SC->PLL0FEED = 0xAA; + SC->PLL0FEED = 0x55; + while (!(SC->PLL0STAT & (1 << 26))); /* Wait for PLOCK0 */ + SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */ + + SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */ + SC->PLL0FEED = 0xAA; + SC->PLL0FEED = 0x55; +#endif + +#if (PLL1_SETUP) + SC->PLL1CFG = PLL1CFG_Val; + SC->PLL1CON = 0x01; /* PLL1 Enable */ + SC->PLL1FEED = 0xAA; + SC->PLL1FEED = 0x55; + while (!(SC->PLL1STAT & (1 << 10))); /* Wait for PLOCK1 */ + + SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */ + SC->PLL1FEED = 0xAA; + SC->PLL1FEED = 0x55; +#endif + +#ifdef USBCLKCFG_Val +#if USBCLKCFG_Val != 0 + SC->USBCLKCFG = USBCLKCFG_Val; +#endif +#endif + +#endif + + /* Determine clock frequency according to clock register values */ + if (((SC->PLL0STAT >> 24) & 3) == 3) {/* If PLL0 enabled and connected */ + switch (SC->CLKSRCSEL & 0x03) { + case 0: /* Internal RC oscillator => PLL0 */ + case 3: /* Reserved, default to Internal RC */ + system_frequency = (IRC_OSC * + (((2 * ((SC->PLL0STAT & 0x7FFF) + 1))) / + (((SC->PLL0STAT >> 16) & 0xFF) + 1)) / + ((SC->CCLKCFG & 0xFF)+ 1)); + break; + case 1: /* Main oscillator => PLL0 */ + system_frequency = (OSC_CLK * + (((2 * ((SC->PLL0STAT & 0x7FFF) + 1))) / + (((SC->PLL0STAT >> 16) & 0xFF) + 1)) / + ((SC->CCLKCFG & 0xFF)+ 1)); + break; + case 2: /* RTC oscillator => PLL0 */ + system_frequency = (RTC_CLK * + (((2 * ((SC->PLL0STAT & 0x7FFF) + 1))) / + (((SC->PLL0STAT >> 16) & 0xFF) + 1)) / + ((SC->CCLKCFG & 0xFF)+ 1)); + break; + } + } else { + switch (SC->CLKSRCSEL & 0x03) { + case 0: /* Internal RC oscillator => PLL0 */ + case 3: /* Reserved, default to Internal RC */ + system_frequency = IRC_OSC / ((SC->CCLKCFG & 0xFF)+ 1); + break; + case 1: /* Main oscillator => PLL0 */ + system_frequency = OSC_CLK / ((SC->CCLKCFG & 0xFF)+ 1); + break; + case 2: /* RTC oscillator => PLL0 */ + system_frequency = RTC_CLK / ((SC->CCLKCFG & 0xFF)+ 1); + break; + } + } + +#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ + SC->FLASHCFG = FLASHCFG_Val; +#endif +} + +void lpc_watchdog_feed() +{ + unsigned long flags; + + save_and_cli(flags); + WDT->WDFEED = 0xAA; + WDT->WDFEED = 0x55; + restore_flags(flags); +} + +void lpc_watchdog_init(int on,int timeout_ms) +{ + if (!on) return; + WDT->WDCLKSEL = 1; + WDT->WDTC = (PCLK/4)/(1000/timeout_ms); + WDT->WDMOD = 0x03; /* Enable watchdog timer and reset */ +} diff --git a/embedded/arch/arm/mach-lpc17xx/libs/hal/hal_machperiph.h b/embedded/arch/arm/mach-lpc17xx/libs/hal/hal_machperiph.h new file mode 100644 index 0000000..aadc41d --- /dev/null +++ b/embedded/arch/arm/mach-lpc17xx/libs/hal/hal_machperiph.h @@ -0,0 +1,14 @@ +#ifndef _HAL_MACHPERIPH_H +#define _HAL_MACHPERIPH_H + +extern unsigned int system_frequency; +#define PCLK ((system_frequency+2)/4) + +void system_clock_init(void); + +void lpc_watchdog_init(int on,int timeout_ms); +void lpc_watchdog_feed(); +void *lpc_reserve_usb_ram(unsigned long size); + +#endif /* _HAL_MACHPERIPH_H */ + diff --git a/embedded/arch/arm/mach-lpc17xx/libs/hal/hal_reserve_usb_ram.c b/embedded/arch/arm/mach-lpc17xx/libs/hal/hal_reserve_usb_ram.c new file mode 100644 index 0000000..43ce840 --- /dev/null +++ b/embedded/arch/arm/mach-lpc17xx/libs/hal/hal_reserve_usb_ram.c @@ -0,0 +1,21 @@ +#include +#include +#include + +extern char _eusbram; + +void *lpc_reserve_usb_ram(unsigned long size) +{ + static char *usb_ram_avail=&_eusbram; + char *prev_avail; + + /*printf("usb reserve %lu at 0x%lx\n",size,(unsigned long)usb_ram_avail);*/ + + if(!usb_ram_avail) + return NULL; + + prev_avail=(char *)(((uintptr_t)usb_ram_avail+3)&~3); + usb_ram_avail=prev_avail+size; + + return prev_avail; +} \ No newline at end of file diff --git a/embedded/arch/arm/mach-lpc17xx/libs/hal/startup.c b/embedded/arch/arm/mach-lpc17xx/libs/hal/startup.c new file mode 100644 index 0000000..516785b --- /dev/null +++ b/embedded/arch/arm/mach-lpc17xx/libs/hal/startup.c @@ -0,0 +1,311 @@ +/****************************************************************************//** + * @file : startup_LPC17xx.c + * @brief : CMSIS Cortex-M3 Core Device Startup File + * @version : V1.01 + * @date : 4. Feb. 2009 + * + *---------------------------------------------------------------------------- + * + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * ARM Limited (ARM) is supplying this software for use with Cortex-Mx + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +// Mod by nio for the .fastcode part + +#include "cpu_def.h" +#include "LPC17xx.h" + +#define WEAK __attribute__ ((weak)) +//***************************************************************************** +// +// Forward declaration of the default fault handlers. +// +//***************************************************************************** +/* System exception vector handler */ +void WEAK Reset_Handler(void); /* Reset Handler */ +void WEAK NMI_Handler(void); /* NMI Handler */ +void WEAK HardFault_Handler(void); /* Hard Fault Handler */ +void WEAK MemManage_Handler(void); /* MPU Fault Handler */ +void WEAK BusFault_Handler(void); /* Bus Fault Handler */ +void WEAK UsageFault_Handler(void); /* Usage Fault Handler */ +void WEAK SVC_Handler(void); /* SVCall Handler */ +void WEAK DebugMon_Handler(void); /* Debug Monitor Handler */ +void WEAK PendSV_Handler(void); /* PendSV Handler */ +void WEAK SysTick_Handler(void); /* SysTick Handler */ + +/* External interrupt vector handler */ +void WEAK WDT_IRQHandler(void); /* Watchdog Timer */ +void WEAK TIMER0_IRQHandler(void); /* Timer0 */ +void WEAK TIMER1_IRQHandler(void); /* Timer1 */ +void WEAK TIMER2_IRQHandler(void); /* Timer2 */ +void WEAK TIMER3_IRQHandler(void); /* Timer3 */ +void WEAK UART0_IRQHandler(void); /* UART0 */ +void WEAK UART1_IRQHandler(void); /* UART1 */ +void WEAK UART2_IRQHandler(void); /* UART2 */ +void WEAK UART3_IRQHandler(void); /* UART3 */ +void WEAK PWM1_IRQHandler(void); /* PWM1 */ +void WEAK I2C0_IRQHandler(void); /* I2C0 */ +void WEAK I2C1_IRQHandler(void); /* I2C1 */ +void WEAK I2C2_IRQHandler(void); /* I2C2 */ +void WEAK SPI_IRQHandler(void); /* SPI */ +void WEAK SSP0_IRQHandler(void); /* SSP0 */ +void WEAK SSP1_IRQHandler(void); /* SSP1 */ +void WEAK PLL0_IRQHandler(void); /* PLL0 (Main PLL) */ +void WEAK RTC_IRQHandler(void); /* Real Time Clock */ +void WEAK EINT0_IRQHandler(void); /* External Interrupt 0 */ +void WEAK EINT1_IRQHandler(void); /* External Interrupt 1 */ +void WEAK EINT2_IRQHandler(void); /* External Interrupt 2 */ +void WEAK EINT3_IRQHandler(void); /* External Interrupt 3 */ +void WEAK ADC_IRQHandler(void); /* A/D Converter */ +void WEAK BOD_IRQHandler(void); /* Brown Out Detect */ +void WEAK USB_IRQHandler(void); /* USB */ +void WEAK CAN_IRQHandler(void); /* CAN */ +void WEAK DMA_IRQHandler(void); /* GP DMA */ +void WEAK I2S_IRQHandler(void); /* I2S */ +void WEAK ENET_IRQHandler(void); /* Ethernet */ +void WEAK RIT_IRQHandler(void); /* Repetitive Interrupt Timer */ +void WEAK MCPWM_IRQHandler(void); /* Motor Control PWM */ +void WEAK QEI_IRQHandler(void); /* Quadrature Encoder Interface */ +void WEAK PLL1_IRQHandler(void); /* PLL1 (USB PLL) */ + + + +/* Exported types --------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +extern unsigned long _etext; +extern unsigned long _sidata; /* start address for the initialization values of the .data section. defined in linker script */ +extern unsigned long _sdata; /* start address for the .data section. defined in linker script */ +extern unsigned long _edata; /* end address for the .data section. defined in linker script */ + +extern unsigned long _sifastcode; /* start address for the initialization values of the .fastcode section. defined in linker script */ +extern unsigned long _sfastcode; /* start address for the .fastcode section. defined in linker script */ +extern unsigned long _efastcode; /* end address for the .fastcode section. defined in linker script */ + +extern unsigned long _sbss; /* start address for the .bss section. defined in linker script */ +extern unsigned long _ebss; /* end address for the .bss section. defined in linker script */ + +extern void _estack; /* init value for the stack pointer. defined in linker script */ + +extern void (_setup_board)(void); /* setup_board adress function */ +extern unsigned long _mem_app_start; + + + +/* Private typedef -----------------------------------------------------------*/ +/* function prototypes ------------------------------------------------------*/ +void Reset_Handler(void) __attribute__((__interrupt__)); +extern int main(void); + +typedef void (*FNC)(void); +FNC fnc_entry; + +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + +extern unsigned long _stack; + +__attribute__ ((section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = +{ + (void (*)(void))&_stack, /* The initial stack pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* NMI Handler */ + HardFault_Handler, /* Hard Fault Handler */ + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, /* Bus Fault Handler */ + UsageFault_Handler, /* Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* SVCall Handler */ + DebugMon_Handler, /* Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* PendSV Handler */ + SysTick_Handler, /* SysTick Handler */ + + // External Interrupts + WDT_IRQHandler, /* Watchdog Timer */ + TIMER0_IRQHandler, /* Timer0 */ + TIMER1_IRQHandler, /* Timer1 */ + TIMER2_IRQHandler, /* Timer2 */ + TIMER3_IRQHandler, /* Timer3 */ + UART0_IRQHandler, /* UART0 */ + UART1_IRQHandler, /* UART1 */ + UART2_IRQHandler, /* UART2 */ + UART3_IRQHandler, /* UART3 */ + PWM1_IRQHandler, /* PWM1 */ + I2C0_IRQHandler, /* I2C0 */ + I2C1_IRQHandler, /* I2C1 */ + I2C2_IRQHandler, /* I2C2 */ + SPI_IRQHandler, /* SPI */ + SSP0_IRQHandler, /* SSP0 */ + SSP1_IRQHandler, /* SSP1 */ + PLL0_IRQHandler, /* PLL0 (Main PLL) */ + RTC_IRQHandler, /* Real Time Clock */ + EINT0_IRQHandler, /* External Interrupt 0 */ + EINT1_IRQHandler, /* External Interrupt 1 */ + EINT2_IRQHandler, /* External Interrupt 2 */ + EINT3_IRQHandler, /* External Interrupt 3 */ + ADC_IRQHandler, /* A/D Converter */ + BOD_IRQHandler, /* Brown Out Detect */ + USB_IRQHandler, /* USB */ + CAN_IRQHandler, /* CAN */ + DMA_IRQHandler, /* GP DMA */ + I2S_IRQHandler, /* I2S */ + ENET_IRQHandler, /* Ethernet */ + RIT_IRQHandler, /* Repetitive Interrupt Timer */ + MCPWM_IRQHandler, /* Motor Control PWM */ + QEI_IRQHandler, /* Quadrature Encoder Interface */ + PLL1_IRQHandler, /* PLL1 (USB PLL) */ +}; + +/******************************************************************************* +* Function Name : Reset_Handler +* Description : This is the code that gets called when the processor first starts execution +* following a reset event. Only the absolutely necessary set is performed, +* after which the application supplied main() routine is called. +* Input : +* Output : +* Return : +*******************************************************************************/ + +void Reset_Handler(void) +{ + unsigned long *pulDest; + unsigned long *pulSrc; + + // + // Copy the data segment initializers from flash to SRAM in ROM mode + // + + if (&_sidata != &_sdata) { // only if needed + pulSrc = &_sidata; + for(pulDest = &_sdata; pulDest < &_edata; ) { + *(pulDest++) = *(pulSrc++); + } + } + + // Copy the .fastcode code from ROM to SRAM + + if (&_sifastcode != &_sfastcode) { // only if needed + pulSrc = &_sifastcode; + for(pulDest = &_sfastcode; pulDest < &_efastcode; ) { + *(pulDest++) = *(pulSrc++); + } + } + + // + // Zero fill the bss segment. + // + for(pulDest = &_sbss; pulDest < &_ebss; ) + { + *(pulDest++) = 0; + } + + // copy initial values and set irq table + if(irq_handler_table && irq_table_size) { + int i; + pulSrc = (unsigned long*)g_pfnVectors; + pulDest = (unsigned long*)irq_handler_table; + for(i = irq_table_size; i--; ) { + *(pulDest++) = *(pulSrc++); + } + /*SCB->VTOR=0x10000000;*/ + SCB->VTOR=(uint32_t)irq_handler_table; + } + + //if (_setup_board!=0) + _setup_board(); + + // + // Call the application's entry point. + // + main(); + + /* disable interrupts */ + NVIC->ICER[0] = 0xffffffff; + NVIC->ICER[1] = 0x00000007; + __set_MSP(*(unsigned long *)(&_mem_app_start)); /* Stack pointer */ + fnc_entry = (FNC)*(unsigned long *)(&_mem_app_start+1); /* Reset handler */ + fnc_entry(); +} + +//***************************************************************************** +// +// Provide weak aliases for each Exception handler to the Default_Handler. +// As they are weak aliases, any function with the same name will override +// this definition. +// +//***************************************************************************** +#pragma weak MemManage_Handler = Default_Handler /* MPU Fault Handler */ +#pragma weak BusFault_Handler = Default_Handler /* Bus Fault Handler */ +#pragma weak UsageFault_Handler = Default_Handler /* Usage Fault Handler */ +#pragma weak SVC_Handler = Default_Handler /* SVCall Handler */ +#pragma weak DebugMon_Handler = Default_Handler /* Debug Monitor Handler */ +#pragma weak PendSV_Handler = Default_Handler /* PendSV Handler */ +#pragma weak SysTick_Handler = Default_Handler /* SysTick Handler */ + +/* External interrupt vector handler */ +#pragma weak WDT_IRQHandler = Default_Handler /* Watchdog Timer */ +#pragma weak TIMER0_IRQHandler = Default_Handler /* Timer0 */ +#pragma weak TIMER1_IRQHandler = Default_Handler /* Timer1 */ +#pragma weak TIMER2_IRQHandler = Default_Handler /* Timer2 */ +#pragma weak TIMER3_IRQHandler = Default_Handler /* Timer3 */ +#pragma weak UART0_IRQHandler = Default_Handler /* UART0 */ +#pragma weak UART1_IRQHandler = Default_Handler /* UART1 */ +#pragma weak UART2_IRQHandler = Default_Handler /* UART2 */ +#pragma weak UART3_IRQHandler = Default_Handler /* UART3 */ +#pragma weak PWM1_IRQHandler = Default_Handler /* PWM1 */ +#pragma weak I2C0_IRQHandler = Default_Handler /* I2C0 */ +#pragma weak I2C1_IRQHandler = Default_Handler /* I2C1 */ +#pragma weak I2C2_IRQHandler = Default_Handler /* I2C2 */ +#pragma weak SPI_IRQHandler = Default_Handler /* SPI */ +#pragma weak SSP0_IRQHandler = Default_Handler /* SSP0 */ +#pragma weak SSP1_IRQHandler = Default_Handler /* SSP1 */ +#pragma weak PLL0_IRQHandler = Default_Handler /* PLL0 (Main PLL) */ +#pragma weak RTC_IRQHandler = Default_Handler /* Real Time Clock */ +#pragma weak EINT0_IRQHandler = Default_Handler /* External Interrupt 0 */ +#pragma weak EINT1_IRQHandler = Default_Handler /* External Interrupt 1 */ +#pragma weak EINT2_IRQHandler = Default_Handler /* External Interrupt 2 */ +#pragma weak EINT3_IRQHandler = Default_Handler /* External Interrupt 3 */ +#pragma weak ADC_IRQHandler = Default_Handler /* A/D Converter */ +#pragma weak BOD_IRQHandler = Default_Handler /* Brown Out Detect */ +#pragma weak USB_IRQHandler = Default_Handler /* USB */ +#pragma weak CAN_IRQHandler = Default_Handler /* CAN */ +#pragma weak DMA_IRQHandler = Default_Handler /* GP DMA */ +#pragma weak I2S_IRQHandler = Default_Handler /* I2S */ +#pragma weak ENET_IRQHandler = Default_Handler /* Ethernet */ +#pragma weak RIT_IRQHandler = Default_Handler /* Repetitive Interrupt Timer */ +#pragma weak MCPWM_IRQHandler = Default_Handler /* Motor Control PWM */ +#pragma weak QEI_IRQHandler = Default_Handler /* Quadrature Encoder Interface */ +#pragma weak PLL1_IRQHandler = Default_Handler /* PLL1 (USB PLL) */ + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +void Default_Handler(void) { + // Go into an infinite loop. + // + while (1) { + } +} diff --git a/embedded/arch/arm/mach-lpc17xx/libs/iap/Makefile b/embedded/arch/arm/mach-lpc17xx/libs/iap/Makefile new file mode 100644 index 0000000..76b56fd --- /dev/null +++ b/embedded/arch/arm/mach-lpc17xx/libs/iap/Makefile @@ -0,0 +1,14 @@ +# Generic directory or leaf node makefile for OCERA make framework + +ifndef MAKERULES_DIR +MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) ) +endif + +ifeq ($(MAKERULES_DIR),) +all : default +.DEFAULT:: + @echo -e "\nThe Makefile.rules has not been found in this or parent directory\n" +else +include $(MAKERULES_DIR)/Makefile.rules +endif + diff --git a/embedded/arch/arm/mach-lpc17xx/libs/iap/Makefile.omk b/embedded/arch/arm/mach-lpc17xx/libs/iap/Makefile.omk new file mode 100644 index 0000000..b5db2c7 --- /dev/null +++ b/embedded/arch/arm/mach-lpc17xx/libs/iap/Makefile.omk @@ -0,0 +1,6 @@ +# -*- makefile -*- + +include_HEADERS = lpciap.h +lib_LIBRARIES = lpciap +lpciap_SOURCES = iap.c + diff --git a/embedded/arch/arm/mach-lpc17xx/libs/iap/iap.c b/embedded/arch/arm/mach-lpc17xx/libs/iap/iap.c new file mode 100644 index 0000000..b43653e --- /dev/null +++ b/embedded/arch/arm/mach-lpc17xx/libs/iap/iap.c @@ -0,0 +1,109 @@ +#include +#include +#include + +#define CMD_SUCCESS 0 +#define BUSY 11 + +#define IAP_CMD_PREPARE 50 +#define IAP_CMD_WRITE 51 +#define IAP_CMD_ERASE 52 +#define IAP_CMD_READ_PARTID 54 + +unsigned int command[5]; +unsigned int result[5]; + +#define IAP_LOCATION 0x1FFF1FF1 + +typedef void (*IAP)(unsigned int [],unsigned int[]); +IAP iap_entry = (IAP) IAP_LOCATION; + +static inline int addr2sec(unsigned long addr) +{ + if (addr<0x10000) { + return (addr>>12); + } else { + addr-=0x10000; + return (addr>>15)+16; + } +} + +int lpcisp_read_partid() +{ + command[0] = IAP_CMD_READ_PARTID; + iap_entry(command, result); + return result[1]; +} + +int lpcisp_prepare_sectors(unsigned char start, unsigned char end) +{ + command[0] = IAP_CMD_PREPARE; + command[1] = start; + command[2] = end; + + iap_entry(command, result); + + return (CMD_SUCCESS == *result); +} + +int lpcisp_erase_sectors(unsigned char start, unsigned char end) +{ + command[0] = IAP_CMD_ERASE; + command[1] = start; + command[2] = end; + command[3] = system_frequency/1000; + + iap_entry(command, result); + + return (CMD_SUCCESS == *result); +} + +int lpcisp_erase(void *addr, int len) +{ + int start,end; + unsigned long flags; + + start=addr2sec((unsigned long)addr); + end=addr2sec((unsigned long)addr+len-1); + + if (end/dev/null ; fi ; done ; pwd ) ) +endif + +ifeq ($(MAKERULES_DIR),) +all : default +.DEFAULT:: + @echo -e "\nThe Makefile.rules has not been found in this or parent directory\n" +else +include $(MAKERULES_DIR)/Makefile.rules +endif + diff --git a/embedded/board/arm/lpc17xx-common/Makefile.omk b/embedded/board/arm/lpc17xx-common/Makefile.omk new file mode 100644 index 0000000..dba8475 --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/Makefile.omk @@ -0,0 +1,3 @@ +# -*- makefile -*- + +SUBDIRS = defines libs diff --git a/embedded/board/arm/lpc17xx-common/config/config.lmc1 b/embedded/board/arm/lpc17xx-common/config/config.lmc1 new file mode 100644 index 0000000..2b5710a --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/config/config.lmc1 @@ -0,0 +1,83 @@ +# -*- makefile -*- + +ARCH=arm +MACH=lpc17xx +BOARD=lpc17xx-common +LD_SCRIPT=lpc1768 + +CONFIG_BOARD_VARIANT=lmc1 + +link_VARIANTS ?= app + +CONFIG_OC_UL_DRV_SYSLESS=y +CONFIG_OC_UL_DRV_U450_VARPINS=y +CONFIG_OC_UL_DRV_U450_VARPINS_MSRSWAP=n +CONFIG_OC_UL_DRV_U450_VARPINS_DIRNEG=n +CONFIG_OC_UL_DRV_U450_LOOPBACK=y +CONFIG_KEYVAL=y +CONFIG_ULAN_DY=y + +#CONFIG_STDIO_COM_PORT=y + +CROSS_COMPILE = arm-elf- +TARGET_ARCH = -mthumb -mcpu=cortex-m3 + +# Set default C flags. If theese are set elsewhere (e.g. on a command +# line), these default flags are not used. +DEBUG ?= -ggdb +#OPTIMIZE ?= -O2 + +# Set default C flags. If theese are set elsewhere (e.g. on a command +# line), these default flags are not used. +#DEBUG ?= -g +OPTIMIZE ?= -Os -ffunction-sections -fdata-sections -Wl,--gc-section +LDFLAGS += -Wl,--cref +LDFLAGS += -Wl,--gc-section + +LPC21ISP=lpc21isp-179 +LPC_BAUD = 38400 +LPC_TTY = /dev/ttyUSB0 +CPU_SYS_KHZ=12000 + +LOAD_CMD-boot = load() { $(LPC21ISP) -bin $$1 $(LPC_TTY) $(LPC_BAUD) $(CPU_SYS_KHZ); }; load + +PROG_BASE=0x09000 +PROG_SIZE=0x37000 + + +OUTPUT_FORMATS = bin + +LOAD_EXTENSION-app = .bin + +ifeq ($(USB),) + +UL_SENDHEX ?= ul_sendhex +MOD ?= 3 + +LOAD_CMD-app = \ + $(UL_SENDHEX) -m $(MOD) -r -o 0 ; \ + $(UL_SENDHEX) -m $(MOD) -o 0 -t 0x101 -s $(PROG_BASE) -l $(PROG_SIZE) -e; \ + $(UL_SENDHEX) -m $(MOD) -o 0 -t 0x101 -b 256 -s $(PROG_BASE) -f binary + +RUN_CMD-app = \ + $(UL_SENDHEX) -m $(MOD) -r + +else + +USB_SENDHEX ?= usb_sendhex +USB_APP_VID ?= 0x1669 +USB_APP_PID ?= 0x1001 +USB_BOOT_VID ?= 0xdead +USB_BOOT_PID ?= 0x2263 + +LOAD_CMD-app = \ + $(USB_SENDHEX) -d $(USB_APP_VID):$(USB_APP_PID) -r ; \ + $(USB_SENDHEX) -w -d $(USB_BOOT_VID):$(USB_BOOT_PID) -s $(PROG_BASE) -l $(PROG_SIZE) -e; sleep 2 ; \ + $(USB_SENDHEX) -d $(USB_BOOT_VID):$(USB_BOOT_PID) -s $(PROG_BASE) -f binary + +RUN_CMD-app = \ + $(USB_SENDHEX) -d $(USB_BOOT_VID):$(USB_BOOT_PID) -r + +endif + + diff --git a/embedded/board/arm/lpc17xx-common/config/config.u2uv2 b/embedded/board/arm/lpc17xx-common/config/config.u2uv2 new file mode 100644 index 0000000..34c5da2 --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/config/config.u2uv2 @@ -0,0 +1,88 @@ +# -*- makefile -*- + +ARCH=arm +MACH=lpc17xx +BOARD=lpc17xx-common + +CONFIG_BOARD_VARIANT=mpx-uu-pc + +ULAN_ID = mpx-bu + +CONFIG_APP_U2U_V2=y +CONFIG_APP_U2U_V2_WITH_KEYVAL=y + +CONFIG_OC_UL_DRV_SYSLESS=y +CONFIG_OC_UL_DRV_U450_VARPINS=y +CONFIG_OC_UL_DRV_U450_VARPINS_MSRSWAP=n +CONFIG_OC_UL_DRV_U450_VARPINS_DIRNEG=n +CONFIG_OC_UL_DRV_U450_LOOPBACK=y +CONFIG_KEYVAL=y +CONFIG_USB_BASE=y +CONFIG_USB_LPCUSB=y +CONFIG_USB_MORE=y + +#CONFIG_STDIO_COM_PORT=y + +CROSS_COMPILE = arm-elf- +TARGET_ARCH = -mthumb -mcpu=cortex-m3 + +# Set default C flags. If theese are set elsewhere (e.g. on a command +# line), these default flags are not used. +DEBUG ?= -g +OPTIMIZE ?= -O2 + +# Set default C flags. If theese are set elsewhere (e.g. on a command +# line), these default flags are not used. +#DEBUG ?= -g +#OPTIMIZE ?= -Os -ffunction-sections -fdata-sections -Wl,--gc-section +#LDFLAGS += -Wl,--cref +#LDFLAGS += -Wl,--gc-section + +# This selects linker script +LD_SCRIPT=lpc1758 + +LPC21ISP=~/projects/cf/lpc21isp_v179/lpc21isp +LPC_BAUD = 38400 +LPC_TTY = /dev/ttyUSB0 +CPU_SYS_KHZ=12000 + +LOAD_CMD-boot = load() { $(LPC21ISP) -bin $$1 $(LPC_TTY) $(LPC_BAUD) $(CPU_SYS_KHZ); }; load + +PROG_BASE=0x09000 +PROG_SIZE=0x77000 + + +OUTPUT_FORMATS = bin + +LOAD_EXTENSION-app = .bin + +ifeq ($(USB),) + +UL_SENDHEX ?= ul_sendhex +MOD ?= 3 + +LOAD_CMD-app = \ + $(UL_SENDHEX) -m $(MOD) -r -o 0 ; \ + $(UL_SENDHEX) -m $(MOD) -o 0 -t 0x101 -s $(PROG_BASE) -l $(PROG_SIZE) -e; \ + $(UL_SENDHEX) -m $(MOD) -o 0 -t 0x101 -b 256 -s $(PROG_BASE) -f binary + +RUN_CMD-app = \ + $(UL_SENDHEX) -m $(MOD) -r + +else + +USB_SENDHEX ?= usb_sendhex +USB_APP_VID ?= 0xdead +USB_APP_PID ?= 0x2263 +USB_BOOT_VID ?= 0xdead +USB_BOOT_PID ?= 0x2263 + +LOAD_CMD-app = \ + $(USB_SENDHEX) -d $(USB_APP_VID):$(USB_APP_PID) -r ; \ + $(USB_SENDHEX) -w -d $(USB_BOOT_VID):$(USB_BOOT_PID) -s $(PROG_BASE) -l $(PROG_SIZE) -e; sleep 2 ; \ + $(USB_SENDHEX) -d $(USB_BOOT_VID):$(USB_BOOT_PID) -s $(PROG_BASE) -f binary + +RUN_CMD-app = \ + $(USB_SENDHEX) -d $(USB_BOOT_VID):$(USB_BOOT_PID) -r + +endif diff --git a/embedded/board/arm/lpc17xx-common/config/config.ulboot b/embedded/board/arm/lpc17xx-common/config/config.ulboot new file mode 100644 index 0000000..796859d --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/config/config.ulboot @@ -0,0 +1,47 @@ +# -*- makefile -*- + +ARCH=arm +MACH=lpc17xx +BOARD=lpc17xx-common + +CONFIG_BOARD_VARIANT=ulmi + +CONFIG_ULBOOT=y + +CONFIG_OC_UL_DRV_SYSLESS=y +CONFIG_OC_UL_DRV_U450_VARPINS=y +CONFIG_OC_UL_DRV_U450_VARPINS_MSRSWAP=y +CONFIG_OC_UL_DRV_U450_VARPINS_DIRNEG=y +CONFIG_OC_UL_DRV_U450_LOOPBACK=y +CONFIG_KEYVAL=y +CONFIG_ULAN_DY=y + +#CONFIG_STDIO_COM_PORT=y + +CROSS_COMPILE = arm-elf- +TARGET_ARCH = -mthumb -mcpu=cortex-m3 + +# Set default C flags. If theese are set elsewhere (e.g. on a command +# line), these default flags are not used. +DEBUG ?= -g +OPTIMIZE ?= -O2 + +# Set default C flags. If theese are set elsewhere (e.g. on a command +# line), these default flags are not used. +#DEBUG ?= -g +#OPTIMIZE ?= -Os -ffunction-sections -fdata-sections -Wl,--gc-section +#LDFLAGS += -Wl,--cref +#LDFLAGS += -Wl,--gc-section + +TOHIT=~/projects/cf/lpc21isp_v179/lpc21isp +LPC_BAUD = 38400 +LPC_TTY = /dev/ttyUSB0 +CPU_SYS_KHZ=14745 + +LOAD_CMD-boot = load() { $(TOHIT) -bin $$1 $(LPC_TTY) $(LPC_BAUD) $(CPU_SYS_KHZ); }; load + +# This selects linker script +LD_SCRIPT=lpc1754 + +OUTPUT_FORMATS = bin + diff --git a/embedded/board/arm/lpc17xx-common/config/config.ulboot-mpx-uu-pc b/embedded/board/arm/lpc17xx-common/config/config.ulboot-mpx-uu-pc new file mode 100644 index 0000000..5610783 --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/config/config.ulboot-mpx-uu-pc @@ -0,0 +1,47 @@ +# -*- makefile -*- + +ARCH=arm +MACH=lpc17xx +BOARD=lpc17xx-common + +CONFIG_BOARD_VARIANT=mpx-uu-pc + +CONFIG_ULBOOT=y + +CONFIG_OC_UL_DRV_SYSLESS=y +CONFIG_OC_UL_DRV_U450_VARPINS=y +CONFIG_OC_UL_DRV_U450_VARPINS_MSRSWAP=n +CONFIG_OC_UL_DRV_U450_VARPINS_DIRNEG=n +CONFIG_OC_UL_DRV_U450_LOOPBACK=y +CONFIG_KEYVAL=y +CONFIG_ULAN_DY=y + +#CONFIG_STDIO_COM_PORT=y + +CROSS_COMPILE = arm-elf- +TARGET_ARCH = -mthumb -mcpu=cortex-m3 + +# Set default C flags. If theese are set elsewhere (e.g. on a command +# line), these default flags are not used. +DEBUG ?= -g +OPTIMIZE ?= -O2 + +# Set default C flags. If theese are set elsewhere (e.g. on a command +# line), these default flags are not used. +#DEBUG ?= -g +#OPTIMIZE ?= -Os -ffunction-sections -fdata-sections -Wl,--gc-section +#LDFLAGS += -Wl,--cref +#LDFLAGS += -Wl,--gc-section + +TOHIT=~/projects/cf/lpc21isp_v179/lpc21isp +LPC_BAUD = 38400 +LPC_TTY = /dev/ttyUSB0 +CPU_SYS_KHZ=14745 + +LOAD_CMD-boot = load() { $(TOHIT) -bin $$1 $(LPC_TTY) $(LPC_BAUD) $(CPU_SYS_KHZ); }; load + +# This selects linker script +LD_SCRIPT=lpc1758 + +OUTPUT_FORMATS = bin + diff --git a/embedded/board/arm/lpc17xx-common/defines/Makefile b/embedded/board/arm/lpc17xx-common/defines/Makefile new file mode 100644 index 0000000..76b56fd --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/defines/Makefile @@ -0,0 +1,14 @@ +# Generic directory or leaf node makefile for OCERA make framework + +ifndef MAKERULES_DIR +MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) ) +endif + +ifeq ($(MAKERULES_DIR),) +all : default +.DEFAULT:: + @echo -e "\nThe Makefile.rules has not been found in this or parent directory\n" +else +include $(MAKERULES_DIR)/Makefile.rules +endif + diff --git a/embedded/board/arm/lpc17xx-common/defines/Makefile.omk b/embedded/board/arm/lpc17xx-common/defines/Makefile.omk new file mode 100644 index 0000000..4ed4e2d --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/defines/Makefile.omk @@ -0,0 +1,15 @@ +# -*- makefile -*- + +default_CONFIG = CONFIG_BOARD_VARIANT=x + +#include_HEADERS = $(notdir $(wildcard $(SOURCES_DIR)/*.h)) + +ifneq ($(CONFIG_BOARD_VARIANT),) + +renamed_include_HEADERS = system_def-$(CONFIG_BOARD_VARIANT).h->system_def.h + +else + +include_HEADERS = system_def.h + +endif # CONFIG_BOARD_VARIANT diff --git a/embedded/board/arm/lpc17xx-common/defines/system_def-lmc1.h b/embedded/board/arm/lpc17xx-common/defines/system_def-lmc1.h new file mode 100644 index 0000000..87b8192 --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/defines/system_def-lmc1.h @@ -0,0 +1,666 @@ +/******************************************************************* + Components for embedded applications builded for + laboratory and medical instruments firmware + + system_def.h - common cover for definition of hardware adresses, + registers, timing and other hardware dependant + parts of embedded hardware + + Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz + (C) 2002 by PiKRON Ltd. http://www.pikron.com + + *******************************************************************/ + +#ifndef _SYSTEM_DEF_H_ +#define _SYSTEM_DEF_H_ + +#include +#include +#include +#include +#include + +#ifndef MACH_LPC17XX +#define MACH_LPC17XX +#endif + +#ifndef NULL +#define NULL 0 +#endif + +#define VER_CODE(major,minor,patch) (major*0x10000+minor*0x100+patch) +/* Software version */ +#define SW_VER_ID "LMC1" +#define SW_VER_MAJOR 0 +#define SW_VER_MINOR 1 +#define SW_VER_PATCH 0 +#define SW_VER_CODE VER_CODE(SW_VER_MAJOR,SW_VER_MINOR,SW_VER_PATCH) +/* Hardware version */ +#define HW_VER_ID "LMC1" +#define HW_VER_MAJOR 1 +#define HW_VER_MINOR 0 +#define HW_VER_PATCH 0 +#define HW_VER_CODE VER_CODE(HW_VER_MAJOR,HW_VER_MINOR,HW_VER_PATCH) +/* Version of mechanical */ +#define MECH_VER_ID "LMC1" +#define MECH_VER_MAJOR 0 +#define MECH_VER_MINOR 0 +#define MECH_VER_PATCH 0 +#define MECH_VER_CODE VER_CODE(MECH_VER_MAJOR,MECH_VER_MINOR,MECH_VER_PATCH) + + +/*--------------------- Clock Configuration ---------------------------------- +// +// Clock Configuration +// System Controls and Status Register (SCS) +// OSCRANGE: Main Oscillator Range Select +// <0=> 1 MHz to 20 MHz +// <1=> 15 MHz to 24 MHz +// OSCEN: Main Oscillator Enable +// +// +// +// Clock Source Select Register (CLKSRCSEL) +// CLKSRC: PLL Clock Source Selection +// <0=> Internal RC oscillator +// <1=> Main oscillator +// <2=> RTC oscillator +// +// +// PLL0 Configuration (Main PLL) +// PLL0 Configuration Register (PLL0CFG) +// F_cco0 = (2 * M * F_in) / N +// F_in must be in the range of 32 kHz to 50 MHz +// F_cco0 must be in the range of 275 MHz to 550 MHz +// MSEL: PLL Multiplier Selection +// <6-32768><#-1> +// M Value +// NSEL: PLL Divider Selection +// <1-256><#-1> +// N Value +// +// +// +// PLL1 Configuration (USB PLL) +// PLL1 Configuration Register (PLL1CFG) +// F_usb = M * F_osc or F_usb = F_cco1 / (2 * P) +// F_cco1 = F_osc * M * 2 * P +// F_cco1 must be in the range of 156 MHz to 320 MHz +// MSEL: PLL Multiplier Selection +// <1-32><#-1> +// M Value (for USB maximum value is 4) +// PSEL: PLL Divider Selection +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// P Value +// +// +// +// CPU Clock Configuration Register (CCLKCFG) +// CCLKSEL: Divide Value for CPU Clock from PLL0 +// <2-256:2><#-1> +// +// +// USB Clock Configuration Register (USBCLKCFG) +// USBSEL: Divide Value for USB Clock from PLL1 +// <0-15> +// Divide is USBSEL + 1 +// +// +// Peripheral Clock Selection Register 0 (PCLKSEL0) +// PCLK_WDT: Peripheral Clock Selection for WDT +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_TIMER0: Peripheral Clock Selection for TIMER0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_TIMER1: Peripheral Clock Selection for TIMER1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_UART0: Peripheral Clock Selection for UART0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_UART1: Peripheral Clock Selection for UART1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_PWM1: Peripheral Clock Selection for PWM1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_I2C0: Peripheral Clock Selection for I2C0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_SPI: Peripheral Clock Selection for SPI +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_SSP1: Peripheral Clock Selection for SSP1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_DAC: Peripheral Clock Selection for DAC +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_ADC: Peripheral Clock Selection for ADC +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_CAN1: Peripheral Clock Selection for CAN1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 6 +// PCLK_CAN2: Peripheral Clock Selection for CAN2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 6 +// PCLK_ACF: Peripheral Clock Selection for ACF +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 6 +// +// +// Peripheral Clock Selection Register 1 (PCLKSEL1) +// PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_GPIO: Peripheral Clock Selection for GPIOs +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_I2C1: Peripheral Clock Selection for I2C1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_SSP0: Peripheral Clock Selection for SSP0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_TIMER2: Peripheral Clock Selection for TIMER2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_TIMER3: Peripheral Clock Selection for TIMER3 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_UART2: Peripheral Clock Selection for UART2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_UART3: Peripheral Clock Selection for UART3 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_I2C2: Peripheral Clock Selection for I2C2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_I2S: Peripheral Clock Selection for I2S +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_SYSCON: Peripheral Clock Selection for the System Control Block +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_MC: Peripheral Clock Selection for the Motor Control PWM +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// +// +// Power Control for Peripherals Register (PCONP) +// PCTIM0: Timer/Counter 0 power/clock enable +// PCTIM1: Timer/Counter 1 power/clock enable +// PCUART0: UART 0 power/clock enable +// PCUART1: UART 1 power/clock enable +// PCPWM1: PWM 1 power/clock enable +// PCI2C0: I2C interface 0 power/clock enable +// PCSPI: SPI interface power/clock enable +// PCRTC: RTC power/clock enable +// PCSSP1: SSP interface 1 power/clock enable +// PCAD: A/D converter power/clock enable +// PCCAN1: CAN controller 1 power/clock enable +// PCCAN2: CAN controller 2 power/clock enable +// PCGPIO: GPIOs power/clock enable +// PCRIT: Repetitive interrupt timer power/clock enable +// PCMC: Motor control PWM power/clock enable +// PCQEI: Quadrature encoder interface power/clock enable +// PCI2C1: I2C interface 1 power/clock enable +// PCSSP0: SSP interface 0 power/clock enable +// PCTIM2: Timer 2 power/clock enable +// PCTIM3: Timer 3 power/clock enable +// PCUART2: UART 2 power/clock enable +// PCUART3: UART 3 power/clock enable +// PCI2C2: I2C interface 2 power/clock enable +// PCI2S: I2S interface power/clock enable +// PCGPDMA: GP DMA function power/clock enable +// PCENET: Ethernet block power/clock enable +// PCUSB: USB interface power/clock enable +// +// +*/ + +#define CLOCK_SETUP 1 + +#define SCS_Val 0x00000020 /* OSCEN */ +#define CLKSRCSEL_Val 0x00000001 /* XTAL */ + +#define PLL0_SETUP 1 +#define PLL0CFG_Val 0x0000000B /* 288000000Hz - must be in the range 275HMz-550MHz */ + +#define PLL1_SETUP 0 +#define PLL1CFG_Val 0x00000023 + +#define CCLKCFG_Val 0x00000003 /* ppl0clk/(CCLKCFG_Val+1)=72000000Hz */ +#define USBCLKCFG_Val 0x00000005 /* divide ppl0clk by 6 to 48MHz */ + +//#define PCLKSEL0_Val 0x00000000 /* all peripherial sysclk/4 */ +//#define PCLKSEL1_Val 0x00000000 +//#define PCONP_Val 0x042887DE + +#define PCONP_CLK_DIV(x) ((x)==0?4:((x)==1?1:((x)==2?2:8))) + +/*--------------------- Flash Accelerator Configuration ---------------------- +// +// Flash Accelerator Configuration +// FETCHCFG: Fetch Configuration +// <0=> Instruction fetches from flash are not buffered +// <1=> One buffer is used for all instruction fetch buffering +// <2=> All buffers may be used for instruction fetch buffering +// <3=> Reserved (do not use this setting) +// DATACFG: Data Configuration +// <0=> Data accesses from flash are not buffered +// <1=> One buffer is used for all data access buffering +// <2=> All buffers may be used for data access buffering +// <3=> Reserved (do not use this setting) +// ACCEL: Acceleration Enable +// PREFEN: Prefetch Enable +// PREFOVR: Prefetch Override +// FLASHTIM: Flash Access Time +// <0=> 1 CPU clock (for CPU clock up to 20 MHz) +// <1=> 2 CPU clocks (for CPU clock up to 40 MHz) +// <2=> 3 CPU clocks (for CPU clock up to 60 MHz) +// <3=> 4 CPU clocks (for CPU clock up to 80 MHz) +// <4=> 5 CPU clocks (for CPU clock up to 100 MHz) +// <5=> 6 CPU clocks (for any CPU clock) +// +*/ +#define FLASH_SETUP 1 +#define FLASHCFG_Val 0x0000403A + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (12000000UL) /* Oscillator frequency */ +#define OSC_CLK ( XTAL) /* Main oscillator frequency */ +#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */ +#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */ + +#define SYS_TIMER_HZ 1000 + +#ifndef BIT +#define BIT(n) (1 << (n)) +#endif + +// Port Bit Definitions & Macros: Description - initial conditions +#define CAN1_RX_BIT BIT(0) // CAN1 RX +#define CAN1_TX_BIT BIT(1) // CAN1 TX +#define TXD0_BIT BIT(2) // used by UART0 +#define RXD0_BIT BIT(3) // used by UART0 +#define CAN2_RX_BIT BIT(4) // CAN2 RX +#define CAN2_TX_BIT BIT(5) // CAN2 TX +#define LED2_BIT BIT(6) // active low/SSEL1 +#define LED2_PIN PORT_PIN(0,6,PORT_CONF_GPIO_OUT_LO) +#define SSP1_CS0_BIT BIT(6) // active low/ LMC_GRAD CS +#define SSP1_CS0_PIN PORT_PIN(0,6,PORT_CONF_GPIO_OUT_HI) +#define SCK1_BIT BIT(7) // clock SSP1 to gradient valves +#define SCK1_PIN PORT_PIN(0,7,PORT_CONF_FNC_2|PORT_CONF_OUT_LO_NORM) +#define MISO1_BIT BIT(8) // master input +#define MISO1_PIN PORT_PIN(0,8,PORT_CONF_FNC_2|PORT_CONF_IN_PU) +#define MOSI1_BIT BIT(9) // master output +#define MOSI1_PIN PORT_PIN(0,9,PORT_CONF_FNC_2|PORT_CONF_OUT_LO_NORM) +#define P0_10_UNUSED_BIT BIT(10) // P0.10 unused (SDA2/TXD2) +#define P0_11_UNUSED_BIT BIT(11) // P0.11 unused (SCL2/RXD2) +#define SCK0_BIT BIT(15) // clock SSP0 to display panel +#define SCK0_PIN PORT_PIN(0,15,PORT_CONF_FNC_2|PORT_CONF_OUT_LO_NORM) +#define SSEL0_BIT BIT(16) // slave select SSP0 +#define SSP0_CS0_BIT BIT(16) // slave select SSP0 / display chip select +#define SSP0_CS0_PIN PORT_PIN(0,16,PORT_CONF_GPIO_OUT_HI) +#define MISO0_BIT BIT(17) // master input SSP0 +#define MISO0_PIN PORT_PIN(0,17,PORT_CONF_FNC_2|PORT_CONF_IN_PU) +#define MOSI0_BIT BIT(18) // master output SSP0 +#define MOSI0_PIN PORT_PIN(0,18,PORT_CONF_FNC_2|PORT_CONF_OUT_LO_NORM) +#define SDA1_BIT BIT(19) // I2C data - memory/connector +#define SCL1_BIT BIT(20) // I2C clock +#define SSP0_CS1_BIT BIT(21) // chip select 1 SSP0/ A/D for display +#define SSP0_CS1_PIN PORT_PIN(0,21,PORT_CONF_GPIO_OUT_HI) +#define SSP0_CS2_BIT BIT(22) // chip select 2 SSP0 for keyboard and LED +#define SSP0_CS2_PIN PORT_PIN(0,22,PORT_CONF_GPIO_OUT_HI) +#define ADC0_BIT BIT(23) // ADC motor current +#define ADC0_PIN PORT_PIN(0,23,PORT_CONF_FNC_1|PORT_CONF_DIR_IN) +#define ADC1_BIT BIT(24) // ADC motor current +#define ADC1_PIN PORT_PIN(0,24,PORT_CONF_FNC_1|PORT_CONF_DIR_IN) +#define ADC2_BIT BIT(25) // ADC motor current +#define ADC2_PIN PORT_PIN(0,25,PORT_CONF_FNC_1|PORT_CONF_DIR_IN) +#define ADC3_BIT BIT(26) // ADC motor current +#define ADC3_PIN PORT_PIN(0,26,PORT_CONF_FNC_1|PORT_CONF_DIR_IN) +#define P0_27_UNUSED_BIT BIT(27) // P0.27 unused +#define P0_28_UNUSED_BIT BIT(28) // P0.28 unused +#define USBDPLUS_BIT BIT(29) // P0.29 USBD+ +#define USBDMINUS_BIT BIT(30) // P0.30 USBD- + + +// Port Bit Definitions & Macros: Description - initial conditions + +#define P1_ETH_BITS (BIT(0)|BIT(1)|BIT(4)|BIT(8)|BIT(9)|\ + BIT(10)|BIT(14)|BIT(15)|BIT(16)|BIT(17)) + +#define P1_0_UNUSED_BIT BIT(0) // P1.0 unused - low output +#define P1_1_UNUSED_BIT BIT(1) // P1.1 unused - low output +#define P1_4_UNUSED_BIT BIT(4) // P1.4 unused - low output +#define P1_8_UNUSED_BIT BIT(8) // P1.8 unused - low output +#define P1_9_UNUSED_BIT BIT(9) // P1.9 unused - low output +#define P1_10_UNUSED_BIT BIT(10) // P1.10 unused - low output +#define P1_14_UNUSED_BIT BIT(14) // P1.14 unused - low output +#define P1_15_UNUSED_BIT BIT(15) // P1.15 unused - low output +#define PWM1_BIT BIT(18) // motor pwm 0 / ADC0 +#define PWM1_PIN PORT_PIN(1,18,PORT_CONF_FNC_2|PORT_CONF_OUT_LO_NORM) +#define BLDC_HAL_A_BIT BIT(19) // motor HAL input A +#define BLDC_HAL_A_PIN PORT_PIN(1,19,PORT_CONF_GPIO_IN_PU) +#define IRC_A_BIT BIT(20) // motor IRC channel A (MCI0) +#define IRC_M_BIT BIT(21) // motor IRC channel mark (GPIO) +#define IRC_M_PIN PORT_PIN(1,21,PORT_CONF_FNC_1|PORT_CONF_IN_PU) +#define BLDC_HAL_B_BIT BIT(22) // motor HAL input B +#define BLDC_HAL_B_PIN PORT_PIN(1,22,PORT_CONF_GPIO_IN_PU) +#define IRC_B_BIT BIT(23) // motor IRC channel B (MCI1) +#define IRC_I_BIT BIT(24) // motor IRC index (MCI2) +#define BLDC_HAL_C_BIT BIT(25) // motor HAL input C +#define BLDC_HAL_C_PIN PORT_PIN(1,25,PORT_CONF_GPIO_IN_PU) +#define PWM1_EN_BIT BIT(26) // motor pwm 0 enable +#define PWM1_EN_PIN PORT_PIN(1,26,PORT_CONF_GPIO_OUT_LO) +#define PWM2_EN_BIT BIT(27) // motor pwm 1 enable +#define PWM2_EN_PIN PORT_PIN(1,27,PORT_CONF_GPIO_OUT_LO) +#define PWM4_EN_BIT BIT(28) // motor pwm 2 enable +#define PWM4_EN_PIN PORT_PIN(1,28,PORT_CONF_GPIO_OUT_LO) +#define PWM6_EN_BIT BIT(29) // motor pwm 3 enable +#define PWM6_EN_PIN PORT_PIN(1,29,PORT_CONF_GPIO_OUT_LO) +#define ADC4_BIT BIT(30) // ADC4 tensometer +#define ADC4_PIN PORT_PIN(1,30,PORT_CONF_FNC_3|PORT_CONF_DIR_IN) +#define ADC5_BIT BIT(31) // ADC5 external input +#define ADC5_PIN PORT_PIN(1,31,PORT_CONF_FNC_3|PORT_CONF_DIR_IN) + +// Port Bit Definitions & Macros: Description - initial conditions +#define TXD1_BIT BIT(0) // P2.0 TXD +#define RXD1_BIT BIT(1) // P2.1 RXD +#define CTS1_BIT BIT(2) // P2.2 CTS connected to RXD1 +#define PWM4_BIT BIT(3) // P2.3 motor pwm 2 / ADC2 +#define PWM4_PIN PORT_PIN(2,3,PORT_CONF_FNC_1|PORT_CONF_OUT_LO_NORM) +#define DSR1_BIT BIT(4) // P2.4 DSR connected to TXD1 +#define PWM6_BIT BIT(5) // P2.5 motor pwm 3 / ADC3 +#define PWM6_PIN PORT_PIN(2,5,PORT_CONF_FNC_1|PORT_CONF_OUT_LO_NORM) +#define LED1_BIT BIT(6) // P2.6 LED1 - error +#define LED1_PIN PORT_PIN(2,6,PORT_CONF_GPIO_OUT_LO) +#define RTS1_BIT BIT(7) // P2.7 RTS1 used as DIR1 +#define AUX_OUT2_BIT BIT(8) // P2.8 auxual TLL port +#define AUX_OUT2_PIN PORT_PIN(2,8,PORT_CONF_GPIO_OUT_HI) +#define USB_CONNECT_BIT BIT(9) // P2.9 USB output for soft connect +#define BOOT_BIT BIT(10) // P2.10 Boot input +#define AUX_IN2_BIT BIT(11) // P2.11 auxual TLL port +#define AUX_IN2_PIN PORT_PIN(2,11,PORT_CONF_GPIO_IN_PU) +#define AUX_OUT4_BIT BIT(12) // P2.12 auxual TLL port +#define AUX_OUT4_PIN PORT_PIN(2,12,PORT_CONF_GPIO_OUT_HI) +#define ETH_PD_IRQ_BIT BIT(13) // P2.13 power down/int + +// Port Bit Definitions & Macros: Description - initial conditions +#define PWM2_BIT BIT(25) // P3.25 motor pwm 1 / ADC1 +#define PWM2_PIN PORT_PIN(3,25,PORT_CONF_FNC_3|PORT_CONF_OUT_LO_NORM) +#define AUX_OUT1_BIT BIT(26) // P3.26 auxual TLL port +#define AUX_OUT1_PIN PORT_PIN(3,26,PORT_CONF_GPIO_OUT_HI) + +// Port Bit Definitions & Macros: Description - initial conditions +#define AUX_OUT3_BIT BIT(28) // P4.28 auxual TLL port / TXD3 +#define AUX_OUT3_PIN PORT_PIN(4,28,PORT_CONF_GPIO_OUT_HI) +#define AUX_IN1_BIT BIT(29) // P4.29 auxual TLL port / RXD3 +#define AUX_IN1_PIN PORT_PIN(4,29,PORT_CONF_GPIO_IN_PU) + +#define P0IO_INPUT_BITS (uint32_t) ( \ + CAN1_RX_BIT | \ + RXD0_BIT | \ + CAN2_RX_BIT | \ + MISO1_BIT | \ + P0_10_UNUSED_BIT | \ + P0_11_UNUSED_BIT | \ + MISO0_BIT | \ + SDA1_BIT | \ + SCL1_BIT | \ + ADC0_BIT | \ + ADC1_BIT | \ + ADC2_BIT | \ + ADC3_BIT | \ + USBDPLUS_BIT | \ + USBDMINUS_BIT | \ + 0 ) + +#define P1IO_INPUT_BITS (uint32_t) ( \ + P1_ETH_BITS | \ + BLDC_HAL_A_BIT | \ + IRC_A_BIT | \ + IRC_M_BIT | \ + BLDC_HAL_B_BIT | \ + IRC_B_BIT | \ + IRC_I_BIT | \ + BLDC_HAL_C_BIT | \ + ADC4_BIT | \ + ADC5_BIT | \ + 0 ) + +#define P2IO_INPUT_BITS (uint32_t) ( \ + RXD1_BIT | \ + CTS1_BIT | \ + DSR1_BIT | \ + BOOT_BIT | \ + AUX_IN2_BIT | \ + ETH_PD_IRQ_BIT | \ + 0 ) + +#define P3IO_INPUT_BITS (uint32_t) ( \ + 0 ) + +#define P4IO_INPUT_BITS (uint32_t) ( \ + AUX_IN1_BIT | \ + 0 ) + +#define P0IO_ZERO_BITS (uint32_t) ( \ + P0_27_UNUSED_BIT | \ + P0_28_UNUSED_BIT | \ + 0 ) + +#define P1IO_ZERO_BITS (uint32_t) ( \ + PWM1_BIT | \ + PWM1_EN_BIT | \ + PWM2_EN_BIT | \ + PWM4_EN_BIT | \ + PWM6_EN_BIT | \ + 0 ) + +#define P2IO_ZERO_BITS (uint32_t) ( \ + PWM4_BIT | \ + PWM6_BIT | \ + 0 ) + +#define P3IO_ZERO_BITS (uint32_t) ( \ + PWM2_BIT | \ + 0 ) + +#define P4IO_ZERO_BITS (uint32_t) ( \ + 0 ) + +#define P0IO_ONE_BITS (uint32_t) ( \ + CAN1_TX_BIT | \ + TXD0_BIT | \ + CAN2_TX_BIT | \ + LED2_BIT | \ + SCK1_BIT | \ + MOSI1_BIT | \ + SCK0_BIT | \ + SSEL0_BIT | \ + MOSI0_BIT | \ + SSP0_CS0_BIT | \ + SSP0_CS1_BIT | \ + 0 ) + +#define P1IO_ONE_BITS (uint32_t) ( \ + 0 ) + +#define P2IO_ONE_BITS (uint32_t) ( \ + TXD1_BIT | \ + LED1_BIT | \ + RTS1_BIT | \ + AUX_OUT2_BIT | \ + USB_CONNECT_BIT | \ + AUX_OUT4_BIT | \ + 0 ) + +#define P3IO_ONE_BITS (uint32_t) ( \ + AUX_OUT1_BIT | \ + 0 ) + +#define P4IO_ONE_BITS (uint32_t) ( \ + AUX_OUT3_BIT | \ + 0 ) + +#define P0IO_OUTPUT_BITS (uint32_t) ( \ + P0IO_ZERO_BITS | \ + P0IO_ONE_BITS ) + +#define P1IO_OUTPUT_BITS (uint32_t) ( \ + P1IO_ZERO_BITS | \ + P1IO_ONE_BITS ) + +#define P2IO_OUTPUT_BITS (uint32_t) ( \ + P2IO_ZERO_BITS | \ + P2IO_ONE_BITS ) + +#define P3IO_OUTPUT_BITS (uint32_t) ( \ + P3IO_ZERO_BITS | \ + P3IO_ONE_BITS ) + +#define P4IO_OUTPUT_BITS (uint32_t) ( \ + P4IO_ZERO_BITS | \ + P4IO_ONE_BITS ) + + + +/***************************************************************************/ +/* io functions */ +#define LED_GP LED2_BIT /* GENREAL PURPOSE LED */ +#define LED_ERR LED1_BIT + +/***************************************************************************/ +/* io functions */ +#define IN_PORT GPIO0->FIO +#define OUT_PORT GPIO1->FIO +#define LED_PORT GPIO2->FIO + +#define CREATE_PORT_NAME_PIN(port) port##PIN +#define CREATE_PORT_NAME_CLR(port) port##CLR +#define CREATE_PORT_NAME_SET(port) port##SET + +#define GET_IN_PIN(port,in) ((CREATE_PORT_NAME_PIN(port) & in)?1:0) +#define GET_IN_PORT(port) (CREATE_PORT_NAME_PIN(port)) +#define SET_OUT_PIN(port,out) (CREATE_PORT_NAME_SET(port)=out) +#define CLR_OUT_PIN(port,out) (CREATE_PORT_NAME_CLR(port)=out) + +/***************************************************************************/ +/* watchdog */ +#define WATCHDOG_ENABLED +#define WATCHDOG_TIMEOUT_MS 1000 + +/***************************************************************************/ +/* uLan configuration */ + +#ifdef UL_LOG_ENABLE + #undef UL_LOG_ENABLE +#endif + +#ifdef ULD_DEFAULT_BUFFER_SIZE + #undef ULD_DEFAULT_BUFFER_SIZE + #define ULD_DEFAULT_BUFFER_SIZE 0x2000 +#endif + +#define UL_DRV_SYSLESS_PORT UART1_BASE +#define UL_DRV_SYSLESS_BAUD 19200 +#define UL_DRV_SYSLESS_IRQ UART1_IRQn +#define UL_DRV_SYSLESS_MY_ADR_DEFAULT 1 + +#define watchdog_feed lpc_watchdog_feed +#define kvpb_erase lpcisp_kvpb_erase +#define kvpb_copy lpcisp_kvpb_copy +#define kvpb_flush lpcisp_kvpb_flush +#define KVPB_DEFAULT_FLAGS KVPB_DESC_DOUBLE|KVPB_DESC_CHUNKWO + +/***************************************************************************/ +/* USB configuration */ +#define USB_WITH_UDEV_FNC +#define USB_EP_NUM 32 +#define USB_MAX_PACKET0 64 +#define USB_MAX_PACKET 8 +#define USB_DMA_EP 0x00000000 + +#define USB_VBUS_PIN_USED 0 + +/***************************************************************************/ +/* I2C1 configuration */ +#define I2C_DRV_SYSLESS_IRQ I2C1_IRQn +#define I2C_DRV_SYSLESS_PORT I2C1_BASE +#define I2C_DRV_SYSLESS_BITRATE 10000 +#define I2C_DRV_SYSLESS_SLADR 0 + +#endif /* _SYSTEM_DEF_H_ */ diff --git a/embedded/board/arm/lpc17xx-common/defines/system_def-mpx-uu-pc.h b/embedded/board/arm/lpc17xx-common/defines/system_def-mpx-uu-pc.h new file mode 100644 index 0000000..f39dc9f --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/defines/system_def-mpx-uu-pc.h @@ -0,0 +1,591 @@ +/******************************************************************* + Components for embedded applications builded for + laboratory and medical instruments firmware + + system_def.h - common cover for definition of hardware adresses, + registers, timing and other hardware dependant + parts of embedded hardware + + Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz + (C) 2002 by PiKRON Ltd. http://www.pikron.com + + *******************************************************************/ + +#ifndef _SYSTEM_DEF_H_ +#define _SYSTEM_DEF_H_ + +#include +#include +#include +#include + +#ifndef MACH_LPC17XX +#define MACH_LPC17XX +#endif + +#ifndef NULL +#define NULL 0 +#endif + +#define VER_CODE(major,minor,patch) (major*0x10000+minor*0x100+patch) +/* Software version */ +#define SW_VER_ID "MPX-UU-PC" +#define SW_VER_MAJOR 0 +#define SW_VER_MINOR 2 +#define SW_VER_PATCH 0 +#define SW_VER_CODE VER_CODE(SW_VER_MAJOR,SW_VER_MINOR,SW_VER_PATCH) +/* Hardware version */ +#define HW_VER_ID "MPX-UU-PC" +#define HW_VER_MAJOR 1 +#define HW_VER_MINOR 0 +#define HW_VER_PATCH 0 +#define HW_VER_CODE VER_CODE(HW_VER_MAJOR,HW_VER_MINOR,HW_VER_PATCH) +/* Version of mechanical */ +#define MECH_VER_ID "MPX-UU-PC" +#define MECH_VER_MAJOR 0 +#define MECH_VER_MINOR 0 +#define MECH_VER_PATCH 0 +#define MECH_VER_CODE VER_CODE(MECH_VER_MAJOR,MECH_VER_MINOR,MECH_VER_PATCH) + + +/*--------------------- Clock Configuration ---------------------------------- +// +// Clock Configuration +// System Controls and Status Register (SCS) +// OSCRANGE: Main Oscillator Range Select +// <0=> 1 MHz to 20 MHz +// <1=> 15 MHz to 24 MHz +// OSCEN: Main Oscillator Enable +// +// +// +// Clock Source Select Register (CLKSRCSEL) +// CLKSRC: PLL Clock Source Selection +// <0=> Internal RC oscillator +// <1=> Main oscillator +// <2=> RTC oscillator +// +// +// PLL0 Configuration (Main PLL) +// PLL0 Configuration Register (PLL0CFG) +// F_cco0 = (2 * M * F_in) / N +// F_in must be in the range of 32 kHz to 50 MHz +// F_cco0 must be in the range of 275 MHz to 550 MHz +// MSEL: PLL Multiplier Selection +// <6-32768><#-1> +// M Value +// NSEL: PLL Divider Selection +// <1-256><#-1> +// N Value +// +// +// +// PLL1 Configuration (USB PLL) +// PLL1 Configuration Register (PLL1CFG) +// F_usb = M * F_osc or F_usb = F_cco1 / (2 * P) +// F_cco1 = F_osc * M * 2 * P +// F_cco1 must be in the range of 156 MHz to 320 MHz +// MSEL: PLL Multiplier Selection +// <1-32><#-1> +// M Value (for USB maximum value is 4) +// PSEL: PLL Divider Selection +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// P Value +// +// +// +// CPU Clock Configuration Register (CCLKCFG) +// CCLKSEL: Divide Value for CPU Clock from PLL0 +// <2-256:2><#-1> +// +// +// USB Clock Configuration Register (USBCLKCFG) +// USBSEL: Divide Value for USB Clock from PLL1 +// <0-15> +// Divide is USBSEL + 1 +// +// +// Peripheral Clock Selection Register 0 (PCLKSEL0) +// PCLK_WDT: Peripheral Clock Selection for WDT +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_TIMER0: Peripheral Clock Selection for TIMER0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_TIMER1: Peripheral Clock Selection for TIMER1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_UART0: Peripheral Clock Selection for UART0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_UART1: Peripheral Clock Selection for UART1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_PWM1: Peripheral Clock Selection for PWM1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_I2C0: Peripheral Clock Selection for I2C0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_SPI: Peripheral Clock Selection for SPI +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_SSP1: Peripheral Clock Selection for SSP1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_DAC: Peripheral Clock Selection for DAC +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_ADC: Peripheral Clock Selection for ADC +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_CAN1: Peripheral Clock Selection for CAN1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 6 +// PCLK_CAN2: Peripheral Clock Selection for CAN2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 6 +// PCLK_ACF: Peripheral Clock Selection for ACF +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 6 +// +// +// Peripheral Clock Selection Register 1 (PCLKSEL1) +// PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_GPIO: Peripheral Clock Selection for GPIOs +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_I2C1: Peripheral Clock Selection for I2C1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_SSP0: Peripheral Clock Selection for SSP0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_TIMER2: Peripheral Clock Selection for TIMER2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_TIMER3: Peripheral Clock Selection for TIMER3 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_UART2: Peripheral Clock Selection for UART2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_UART3: Peripheral Clock Selection for UART3 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_I2C2: Peripheral Clock Selection for I2C2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_I2S: Peripheral Clock Selection for I2S +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_SYSCON: Peripheral Clock Selection for the System Control Block +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_MC: Peripheral Clock Selection for the Motor Control PWM +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// +// +// Power Control for Peripherals Register (PCONP) +// PCTIM0: Timer/Counter 0 power/clock enable +// PCTIM1: Timer/Counter 1 power/clock enable +// PCUART0: UART 0 power/clock enable +// PCUART1: UART 1 power/clock enable +// PCPWM1: PWM 1 power/clock enable +// PCI2C0: I2C interface 0 power/clock enable +// PCSPI: SPI interface power/clock enable +// PCRTC: RTC power/clock enable +// PCSSP1: SSP interface 1 power/clock enable +// PCAD: A/D converter power/clock enable +// PCCAN1: CAN controller 1 power/clock enable +// PCCAN2: CAN controller 2 power/clock enable +// PCGPIO: GPIOs power/clock enable +// PCRIT: Repetitive interrupt timer power/clock enable +// PCMC: Motor control PWM power/clock enable +// PCQEI: Quadrature encoder interface power/clock enable +// PCI2C1: I2C interface 1 power/clock enable +// PCSSP0: SSP interface 0 power/clock enable +// PCTIM2: Timer 2 power/clock enable +// PCTIM3: Timer 3 power/clock enable +// PCUART2: UART 2 power/clock enable +// PCUART3: UART 3 power/clock enable +// PCI2C2: I2C interface 2 power/clock enable +// PCI2S: I2S interface power/clock enable +// PCGPDMA: GP DMA function power/clock enable +// PCENET: Ethernet block power/clock enable +// PCUSB: USB interface power/clock enable +// +// +*/ + +#define CLOCK_SETUP 1 + +#define SCS_Val 0x00000020 /* OSCEN */ +#define CLKSRCSEL_Val 0x00000001 /* XTAL */ + +#define PLL0_SETUP 1 +#define PLL0CFG_Val 0x0000000B /* 324403200Hz - must be in the range 275HMz-550MHz */ + +#define PLL1_SETUP 0 +#define PLL1CFG_Val 0x00000023 + +#define CCLKCFG_Val 0x00000003 /* pplclk/(CCLKCFG_Val+1)=81100800Hz */ +#define USBCLKCFG_Val 0x00000005 + +//#define PCLKSEL0_Val 0x00000000 /* all peripherial sysclk/4 */ +//#define PCLKSEL1_Val 0x00000000 +//#define PCONP_Val 0x042887DE + +#define PCONP_CLK_DIV(x) ((x)==0?4:((x)==1?1:((x)==2?2:8))) + +/*--------------------- Flash Accelerator Configuration ---------------------- +// +// Flash Accelerator Configuration +// FETCHCFG: Fetch Configuration +// <0=> Instruction fetches from flash are not buffered +// <1=> One buffer is used for all instruction fetch buffering +// <2=> All buffers may be used for instruction fetch buffering +// <3=> Reserved (do not use this setting) +// DATACFG: Data Configuration +// <0=> Data accesses from flash are not buffered +// <1=> One buffer is used for all data access buffering +// <2=> All buffers may be used for data access buffering +// <3=> Reserved (do not use this setting) +// ACCEL: Acceleration Enable +// PREFEN: Prefetch Enable +// PREFOVR: Prefetch Override +// FLASHTIM: Flash Access Time +// <0=> 1 CPU clock (for CPU clock up to 20 MHz) +// <1=> 2 CPU clocks (for CPU clock up to 40 MHz) +// <2=> 3 CPU clocks (for CPU clock up to 60 MHz) +// <3=> 4 CPU clocks (for CPU clock up to 80 MHz) +// <4=> 5 CPU clocks (for CPU clock up to 100 MHz) +// <5=> 6 CPU clocks (for any CPU clock) +// +*/ +#define FLASH_SETUP 1 +#define FLASHCFG_Val 0x0000403A + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (12000000UL) /* Oscillator frequency */ +#define OSC_CLK ( XTAL) /* Main oscillator frequency */ +#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */ +#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */ + + + + +#define SYS_TIMER_HZ 1000 + +#ifndef BIT +#define BIT(n) (1 << (n)) +#endif + +// Port Bit Definitions & Macros: Description - initial conditions +#define P0_0_UNUSED_BIT BIT(0) // P0.0 unused - low output +#define P0_1_UNUSED_BIT BIT(1) // P0.1 unused - low output +#define TXD0_BIT BIT(2) // used by UART0 +#define RXD0_BIT BIT(3) // used by UART0 +#define P0_6_UNUSED_BIT BIT(6) // P0.6 unused - low output +#define P0_7_UNUSED_BIT BIT(7) // P0.7 unused - low output +#define P0_8_UNUSED_BIT BIT(8) // P0.8 unused - low output +#define P0_9_UNUSED_BIT BIT(9) // P0.9 unused - low output +#define P0_10_UNUSED_BIT BIT(10) // P0.10 unused - low output +#define P0_11_UNUSED_BIT BIT(11) // P0.11 unused - low output +#define P0_15_UNUSED_BIT BIT(15) // P0.15 unused - low output +#define P0_16_UNUSED_BIT BIT(16) // P0.16 unused - low output +#define LED1_BIT BIT(17) // P0.17 LED1 +#define LED2_BIT BIT(18) // P0.18 LED2 +#define P0_22_UNUSED_BIT BIT(22) // P0.22 unused - low output +#define P0_25_UNUSED_BIT BIT(25) // P0.25 unused - low output +#define P0_26_UNUSED_BIT BIT(26) // P0.26 unused - low output +#define USBDPLUS_BIT BIT(29) // P0.29 USBD+ +#define USBDMINUS_BIT BIT(30) // P0.30 USBD- + + +// Port Bit Definitions & Macros: Description - initial conditions +#define P1_0_UNUSED_BIT BIT(0) // P1.0 unused - low output +#define P1_1_UNUSED_BIT BIT(1) // P1.1 unused - low output +#define P1_4_UNUSED_BIT BIT(4) // P1.4 unused - low output +#define P1_8_UNUSED_BIT BIT(8) // P1.8 unused - low output +#define P1_9_UNUSED_BIT BIT(9) // P1.9 unused - low output +#define P1_10_UNUSED_BIT BIT(10) // P1.10 unused - low output +#define P1_14_UNUSED_BIT BIT(14) // P1.14 unused - low output +#define P1_15_UNUSED_BIT BIT(15) // P1.15 unused - low output +#define P1_18_UNUSED_BIT BIT(18) // P1.18 unused - low output +#define WDT_BIT BIT(19) // P1.19 WDT +#define P1_20_UNUSED_BIT BIT(20) // P1.20 unused - low output +#define P1_22_UNUSED_BIT BIT(22) // P1.22 unused - low output +#define P1_23_UNUSED_BIT BIT(23) // P1.23 unused - low output +#define P1_24_UNUSED_BIT BIT(24) // P1.24 unused - low output +#define P1_25_UNUSED_BIT BIT(25) // P1.25 unused - low output +#define P1_26_UNUSED_BIT BIT(26) // P1.26 unused - low output +#define P1_28_UNUSED_BIT BIT(28) // P1.28 unused - low output +#define P1_29_UNUSED_BIT BIT(29) // P1.29 unused - low output +#define VBUS_BIT BIT(30) // P1.30 +#define P1_31_UNUSED_BIT BIT(31) // P1.31 unused - low output + +// Port Bit Definitions & Macros: Description - initial conditions +#define TXD1_BIT BIT(0) // P2.0 TXD +#define RXD1_BIT BIT(1) // P2.1 RXD +#define CTS1_BIT BIT(2) // P2.2 CTS connected to RXD1 +#define P2_3_UNUSED_BIT BIT(3) // P2.3 unused - low output +#define DSR1_BIT BIT(4) // P2.4 DSR connected to TXD1 +#define P2_5_UNUSED_BIT BIT(5) // P2.5 unused - low output +#define P2_6_UNUSED_BIT BIT(6) // P2.6 unused - low output +#define RTS1_BIT BIT(7) // P2.7 RTS1 used as DIR1 +#define P2_8_UNUSED_BIT BIT(8) // P2.8 unused - low output +#define USB_CONNECT_BIT BIT(9) // P2.9 USB output for soft connect +#define BOOT_BIT BIT(10) // P2.10 Boot input + +#define P4_28_UNUSED_BIT BIT(28) // P4.28 unused - low output +#define P4_29_UNUSED_BIT BIT(29) // P4.29 unused - low output + +#define P0IO_INPUT_BITS (uint32_t) ( \ + RXD0_BIT | \ + USBDPLUS_BIT | \ + USBDMINUS_BIT | \ + 0 ) + +#define P1IO_INPUT_BITS (uint32_t) ( \ + VBUS_BIT | \ + 0 ) + +#define P2IO_INPUT_BITS (uint32_t) ( \ + RXD1_BIT | \ + CTS1_BIT | \ + DSR1_BIT | \ + BOOT_BIT | \ + 0 ) + +#define P3IO_INPUT_BITS (uint32_t) ( \ + 0 ) + +#define P4IO_INPUT_BITS (uint32_t) ( \ + 0 ) + +#define P0IO_ZERO_BITS (uint32_t) ( \ + P0_0_UNUSED_BIT | \ + P0_1_UNUSED_BIT | \ + P0_6_UNUSED_BIT | \ + P0_7_UNUSED_BIT | \ + P0_8_UNUSED_BIT | \ + P0_9_UNUSED_BIT | \ + P0_10_UNUSED_BIT | \ + P0_11_UNUSED_BIT | \ + P0_15_UNUSED_BIT | \ + P0_16_UNUSED_BIT | \ + P0_22_UNUSED_BIT | \ + P0_25_UNUSED_BIT | \ + P0_26_UNUSED_BIT | \ + 0 ) + +#define P1IO_ZERO_BITS (uint32_t) ( \ + P1_0_UNUSED_BIT | \ + P1_1_UNUSED_BIT | \ + P1_4_UNUSED_BIT | \ + P1_8_UNUSED_BIT | \ + P1_9_UNUSED_BIT | \ + P1_10_UNUSED_BIT | \ + P1_14_UNUSED_BIT | \ + P1_15_UNUSED_BIT | \ + P1_18_UNUSED_BIT | \ + P1_20_UNUSED_BIT | \ + P1_22_UNUSED_BIT | \ + P1_23_UNUSED_BIT | \ + P1_24_UNUSED_BIT | \ + P1_25_UNUSED_BIT | \ + P1_26_UNUSED_BIT | \ + P1_28_UNUSED_BIT | \ + P1_29_UNUSED_BIT | \ + P1_31_UNUSED_BIT | \ + 0 ) + +#define P2IO_ZERO_BITS (uint32_t) ( \ + P2_3_UNUSED_BIT | \ + P2_5_UNUSED_BIT | \ + P2_6_UNUSED_BIT | \ + P2_8_UNUSED_BIT | \ + 0 ) + +#define P3IO_ZERO_BITS (uint32_t) ( \ + 0 ) + +#define P4IO_ZERO_BITS (uint32_t) ( \ + P4_28_UNUSED_BIT | \ + P4_29_UNUSED_BIT | \ + 0 ) + +#define P0IO_ONE_BITS (uint32_t) ( \ + TXD0_BIT | \ + LED1_BIT | \ + LED2_BIT | \ + 0 ) + +#define P1IO_ONE_BITS (uint32_t) ( \ + WDT_BIT | \ + 0 ) + +#define P2IO_ONE_BITS (uint32_t) ( \ + TXD1_BIT | \ + RTS1_BIT | \ + USB_CONNECT_BIT | \ + 0 ) + +#define P3IO_ONE_BITS (uint32_t) ( \ + 0 ) + +#define P4IO_ONE_BITS (uint32_t) ( \ + 0 ) + +#define P0IO_OUTPUT_BITS (uint32_t) ( \ + P0IO_ZERO_BITS | \ + P0IO_ONE_BITS ) + +#define P1IO_OUTPUT_BITS (uint32_t) ( \ + P1IO_ZERO_BITS | \ + P1IO_ONE_BITS ) + +#define P2IO_OUTPUT_BITS (uint32_t) ( \ + P2IO_ZERO_BITS | \ + P2IO_ONE_BITS ) + +#define P3IO_OUTPUT_BITS (uint32_t) ( \ + P3IO_ZERO_BITS | \ + P3IO_ONE_BITS ) + +#define P4IO_OUTPUT_BITS (uint32_t) ( \ + P4IO_ZERO_BITS | \ + P4IO_ONE_BITS ) + + + +/***************************************************************************/ +/* io functions */ +#define LED_GP LED1_BIT /* GENREAL PURPOSE LED */ +#define LED_ERR LED2_BIT + +/***************************************************************************/ +/* io functions */ +#define LED_PORT GPIO0->FIO +#define OUT_PORT GPIO1->FIO + +#define CREATE_PORT_NAME_PIN(port) port##PIN +#define CREATE_PORT_NAME_CLR(port) port##CLR +#define CREATE_PORT_NAME_SET(port) port##SET + +#define GET_IN_PIN(port,in) ((CREATE_PORT_NAME_PIN(port) & in)?1:0) +#define GET_IN_PORT(port) (CREATE_PORT_NAME_PIN(port)) +#define SET_OUT_PIN(port,out) (CREATE_PORT_NAME_SET(port)=out) +#define CLR_OUT_PIN(port,out) (CREATE_PORT_NAME_CLR(port)=out) + +/***************************************************************************/ +/* watchdog */ +#define WATCHDOG_ENABLED +#define WATCHDOG_TIMEOUT_MS 1000 + +/***************************************************************************/ +/* uLan configuration */ + +#ifdef UL_LOG_ENABLE + #undef UL_LOG_ENABLE +#endif + +#ifdef ULD_DEFAULT_BUFFER_SIZE + #undef ULD_DEFAULT_BUFFER_SIZE + #define ULD_DEFAULT_BUFFER_SIZE 0x2000 +#endif + +#define UL_DRV_SYSLESS_PORT UART1_BASE +#define UL_DRV_SYSLESS_BAUD 19200 +#define UL_DRV_SYSLESS_IRQ UART1_IRQn +#define UL_DRV_SYSLESS_MY_ADR_DEFAULT 1 + +#define watchdog_feed lpc_watchdog_feed +#define kvpb_erase lpcisp_kvpb_erase +#define kvpb_copy lpcisp_kvpb_copy +#define kvpb_flush lpcisp_kvpb_flush +#define KVPB_DEFAULT_FLAGS KVPB_DESC_DOUBLE|KVPB_DESC_CHUNKWO + +/***************************************************************************/ +/* USB configuration */ +#define USB_WITH_UDEV_FNC +#define USB_EP_NUM 32 +#define USB_MAX_PACKET0 64 +#define USB_MAX_PACKET 8 +#define USB_DMA_EP 0x00000000 + +#define USB_VBUS_PIN_USED 1 + + +#endif /* _SYSTEM_DEF_H_ */ diff --git a/embedded/board/arm/lpc17xx-common/defines/system_def-ulmi.h b/embedded/board/arm/lpc17xx-common/defines/system_def-ulmi.h new file mode 100644 index 0000000..6d40a9a --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/defines/system_def-ulmi.h @@ -0,0 +1,584 @@ +/******************************************************************* + Components for embedded applications builded for + laboratory and medical instruments firmware + + system_def.h - common cover for definition of hardware adresses, + registers, timing and other hardware dependant + parts of embedded hardware + + Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz + (C) 2002 by PiKRON Ltd. http://www.pikron.com + + *******************************************************************/ + +#ifndef _SYSTEM_DEF_H_ +#define _SYSTEM_DEF_H_ + +#include +#include +#include +#include + +#ifndef NULL +#define NULL 0 +#endif + +#define VER_CODE(major,minor,patch) (major*0x10000+minor*0x100+patch) +/* Software version */ +#define SW_VER_ID "ULMO_1M1I" +#define SW_VER_MAJOR 0 +#define SW_VER_MINOR 2 +#define SW_VER_PATCH 0 +#define SW_VER_CODE VER_CODE(SW_VER_MAJOR,SW_VER_MINOR,SW_VER_PATCH) +/* Hardware version */ +#define HW_VER_ID "ULMO_1M1I" +#define HW_VER_MAJOR 1 +#define HW_VER_MINOR 0 +#define HW_VER_PATCH 0 +#define HW_VER_CODE VER_CODE(HW_VER_MAJOR,HW_VER_MINOR,HW_VER_PATCH) +/* Version of mechanical */ +#define MECH_VER_ID "ULMO_1M1I" +#define MECH_VER_MAJOR 0 +#define MECH_VER_MINOR 0 +#define MECH_VER_PATCH 0 +#define MECH_VER_CODE VER_CODE(MECH_VER_MAJOR,MECH_VER_MINOR,MECH_VER_PATCH) + + +/*--------------------- Clock Configuration ---------------------------------- +// +// Clock Configuration +// System Controls and Status Register (SCS) +// OSCRANGE: Main Oscillator Range Select +// <0=> 1 MHz to 20 MHz +// <1=> 15 MHz to 24 MHz +// OSCEN: Main Oscillator Enable +// +// +// +// Clock Source Select Register (CLKSRCSEL) +// CLKSRC: PLL Clock Source Selection +// <0=> Internal RC oscillator +// <1=> Main oscillator +// <2=> RTC oscillator +// +// +// PLL0 Configuration (Main PLL) +// PLL0 Configuration Register (PLL0CFG) +// F_cco0 = (2 * M * F_in) / N +// F_in must be in the range of 32 kHz to 50 MHz +// F_cco0 must be in the range of 275 MHz to 550 MHz +// MSEL: PLL Multiplier Selection +// <6-32768><#-1> +// M Value +// NSEL: PLL Divider Selection +// <1-256><#-1> +// N Value +// +// +// +// PLL1 Configuration (USB PLL) +// PLL1 Configuration Register (PLL1CFG) +// F_usb = M * F_osc or F_usb = F_cco1 / (2 * P) +// F_cco1 = F_osc * M * 2 * P +// F_cco1 must be in the range of 156 MHz to 320 MHz +// MSEL: PLL Multiplier Selection +// <1-32><#-1> +// M Value (for USB maximum value is 4) +// PSEL: PLL Divider Selection +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// P Value +// +// +// +// CPU Clock Configuration Register (CCLKCFG) +// CCLKSEL: Divide Value for CPU Clock from PLL0 +// <2-256:2><#-1> +// +// +// USB Clock Configuration Register (USBCLKCFG) +// USBSEL: Divide Value for USB Clock from PLL1 +// <0-15> +// Divide is USBSEL + 1 +// +// +// Peripheral Clock Selection Register 0 (PCLKSEL0) +// PCLK_WDT: Peripheral Clock Selection for WDT +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_TIMER0: Peripheral Clock Selection for TIMER0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_TIMER1: Peripheral Clock Selection for TIMER1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_UART0: Peripheral Clock Selection for UART0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_UART1: Peripheral Clock Selection for UART1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_PWM1: Peripheral Clock Selection for PWM1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_I2C0: Peripheral Clock Selection for I2C0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_SPI: Peripheral Clock Selection for SPI +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_SSP1: Peripheral Clock Selection for SSP1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_DAC: Peripheral Clock Selection for DAC +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_ADC: Peripheral Clock Selection for ADC +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_CAN1: Peripheral Clock Selection for CAN1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 6 +// PCLK_CAN2: Peripheral Clock Selection for CAN2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 6 +// PCLK_ACF: Peripheral Clock Selection for ACF +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 6 +// +// +// Peripheral Clock Selection Register 1 (PCLKSEL1) +// PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_GPIO: Peripheral Clock Selection for GPIOs +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_I2C1: Peripheral Clock Selection for I2C1 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_SSP0: Peripheral Clock Selection for SSP0 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_TIMER2: Peripheral Clock Selection for TIMER2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_TIMER3: Peripheral Clock Selection for TIMER3 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_UART2: Peripheral Clock Selection for UART2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_UART3: Peripheral Clock Selection for UART3 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_I2C2: Peripheral Clock Selection for I2C2 +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_I2S: Peripheral Clock Selection for I2S +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_SYSCON: Peripheral Clock Selection for the System Control Block +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// PCLK_MC: Peripheral Clock Selection for the Motor Control PWM +// <0=> Pclk = Cclk / 4 +// <1=> Pclk = Cclk +// <2=> Pclk = Cclk / 2 +// <3=> Pclk = Hclk / 8 +// +// +// Power Control for Peripherals Register (PCONP) +// PCTIM0: Timer/Counter 0 power/clock enable +// PCTIM1: Timer/Counter 1 power/clock enable +// PCUART0: UART 0 power/clock enable +// PCUART1: UART 1 power/clock enable +// PCPWM1: PWM 1 power/clock enable +// PCI2C0: I2C interface 0 power/clock enable +// PCSPI: SPI interface power/clock enable +// PCRTC: RTC power/clock enable +// PCSSP1: SSP interface 1 power/clock enable +// PCAD: A/D converter power/clock enable +// PCCAN1: CAN controller 1 power/clock enable +// PCCAN2: CAN controller 2 power/clock enable +// PCGPIO: GPIOs power/clock enable +// PCRIT: Repetitive interrupt timer power/clock enable +// PCMC: Motor control PWM power/clock enable +// PCQEI: Quadrature encoder interface power/clock enable +// PCI2C1: I2C interface 1 power/clock enable +// PCSSP0: SSP interface 0 power/clock enable +// PCTIM2: Timer 2 power/clock enable +// PCTIM3: Timer 3 power/clock enable +// PCUART2: UART 2 power/clock enable +// PCUART3: UART 3 power/clock enable +// PCI2C2: I2C interface 2 power/clock enable +// PCI2S: I2S interface power/clock enable +// PCGPDMA: GP DMA function power/clock enable +// PCENET: Ethernet block power/clock enable +// PCUSB: USB interface power/clock enable +// +// +*/ + +#define CLOCK_SETUP 1 + +#define SCS_Val 0x00000020 /* OSCEN */ +#define CLKSRCSEL_Val 0x00000001 /* XTAL */ + +#define PLL0_SETUP 1 +#define PLL0CFG_Val 0x0000000B /* 324403200Hz - must be in the range 275HMz-550MHz */ + +#define PLL1_SETUP 0 +#define PLL1CFG_Val 0x00000023 + +#define CCLKCFG_Val 0x00000003 /* pplclk/(CCLKCFG_Val+1)=81100800Hz */ +#define USBCLKCFG_Val 0x00000000 + +//#define PCLKSEL0_Val 0x00000000 /* all peripherial sysclk/4 */ +//#define PCLKSEL1_Val 0x00000000 +//#define PCONP_Val 0x042887DE + +#define PCONP_CLK_DIV(x) ((x)==0?4:((x)==1?1:((x)==2?2:8))) + +/*--------------------- Flash Accelerator Configuration ---------------------- +// +// Flash Accelerator Configuration +// FETCHCFG: Fetch Configuration +// <0=> Instruction fetches from flash are not buffered +// <1=> One buffer is used for all instruction fetch buffering +// <2=> All buffers may be used for instruction fetch buffering +// <3=> Reserved (do not use this setting) +// DATACFG: Data Configuration +// <0=> Data accesses from flash are not buffered +// <1=> One buffer is used for all data access buffering +// <2=> All buffers may be used for data access buffering +// <3=> Reserved (do not use this setting) +// ACCEL: Acceleration Enable +// PREFEN: Prefetch Enable +// PREFOVR: Prefetch Override +// FLASHTIM: Flash Access Time +// <0=> 1 CPU clock (for CPU clock up to 20 MHz) +// <1=> 2 CPU clocks (for CPU clock up to 40 MHz) +// <2=> 3 CPU clocks (for CPU clock up to 60 MHz) +// <3=> 4 CPU clocks (for CPU clock up to 80 MHz) +// <4=> 5 CPU clocks (for CPU clock up to 100 MHz) +// <5=> 6 CPU clocks (for any CPU clock) +// +*/ +#define FLASH_SETUP 1 +#define FLASHCFG_Val 0x0000403A + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (14745600UL) /* Oscillator frequency */ +#define OSC_CLK ( XTAL) /* Main oscillator frequency */ +#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */ +#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */ + + + + +#define SYS_TIMER_HZ 1000 + +#ifndef BIT +#define BIT(n) (1 << (n)) +#endif + +// Port Bit Definitions & Macros: Description - initial conditions +#define P0_0_UNUSED_BIT BIT(0) // P0.0 unused - low output +#define P0_1_UNUSED_BIT BIT(1) // P0.1 unused - low output +#define TXD0_BIT BIT(2) // used by UART0 +#define RXD0_BIT BIT(3) // used by UART0 +#define OVER_LOAD_BIT BIT(6) // OVER_LOAD +#define P0_7_UNUSED_BIT BIT(7) // P0.7 unused - low output +#define P0_8_UNUSED_BIT BIT(8) // P0.8 unused - low output +#define P0_9_UNUSED_BIT BIT(9) // P0.9 unused - low output +#define P0_10_UNUSED_BIT BIT(10) // P0.10 unused - low output +#define P0_11_UNUSED_BIT BIT(11) // P0.11 unused - low output +#define IN2_BIT BIT(15) // P0.15 input 2 +#define IN1_BIT BIT(16) // P0.16 input 1 +#define IN3_BIT BIT(17) // P0.17 input 3 +#define IN4_BIT BIT(18) // P0.18 input 4 +#define RTS1_BIT BIT(22) // P0.22 uDIR +#define EXT_TEMP_SENS_BIT BIT(25) // P0.25 +#define EXT_TEMP_TYPE_BIT BIT(26) // P0.26 +#define USBDPLUS_BIT BIT(29) // P0.29 USBD+ +#define USBDMINUS_BIT BIT(30) // P0.30 USBD- + + +// Port Bit Definitions & Macros: Description - initial conditions +#define P1_0_UNUSED_BIT BIT(0) // P1.0 unused - low output +#define P1_1_UNUSED_BIT BIT(1) // P1.1 unused - low output +#define P1_4_UNUSED_BIT BIT(4) // P1.4 unused - low output +#define P1_8_UNUSED_BIT BIT(8) // P1.8 unused - low output +#define P1_9_UNUSED_BIT BIT(9) // P1.9 unused - low output +#define P1_10_UNUSED_BIT BIT(10) // P1.10 unused - low output +#define P1_14_UNUSED_BIT BIT(14) // P1.14 unused - low output +#define P1_15_UNUSED_BIT BIT(15) // P1.15 unused - low output +#define P1_18_UNUSED_BIT BIT(18) // P1.18 unused - low output +#define P1_19_UNUSED_BIT BIT(19) // P1.19 unused - low output +#define P1_20_UNUSED_BIT BIT(20) // P1.20 unused - low output +#define P1_22_UNUSED_BIT BIT(22) // P1.22 unused - low output +#define OUT1_BIT BIT(23) // Output 1 +#define OUT2_BIT BIT(24) // Output 2 +#define P1_25_UNUSED_BIT BIT(25) // P1.25 unused - low output +#define P1_26_UNUSED_BIT BIT(26) // P1.26 unused - low output +#define P1_28_UNUSED_BIT BIT(28) // P1.28 unused - low output +#define P1_29_UNUSED_BIT BIT(29) // P1.29 unused - low output +#define EXT_TEMP_SW_BIT BIT(30) // P1.30 +#define P1_31_UNUSED_BIT BIT(31) // P1.31 unused - low output + +// Port Bit Definitions & Macros: Description - initial conditions +#define TXD1_BIT BIT(0) // P2.0 TXD +#define RXD1_BIT BIT(1) // P2.1 RXD +#define P2_2_UNUSED_BIT BIT(2) // P2.2 unused - low output +#define P2_3_UNUSED_BIT BIT(3) // P2.3 unused - low output +#define DSR1_BIT BIT(4) // P2.4 DSR +#define LED1_BIT BIT(5) // P2.5 LED1 +#define LED2_BIT BIT(6) // P2.6 LED2 +#define LED3_BIT BIT(7) // P2.7 LED3 +#define LED4_BIT BIT(8) // P2.8 LED4 +#define P2_9_UNUSED_BIT BIT(9) // P2.9 unused - low output +#define BOOT_BIT BIT(10) // P2.10 Boot input + +#define P4_28_UNUSED_BIT BIT(28) // P4.28 unused - low output +#define P4_29_UNUSED_BIT BIT(29) // P4.29 unused - low output + +#define P0IO_INPUT_BITS (uint32_t) ( \ + RXD0_BIT | \ + OVER_LOAD_BIT | \ + IN2_BIT | \ + IN1_BIT | \ + IN3_BIT | \ + IN4_BIT | \ + EXT_TEMP_SENS_BIT | \ + USBDPLUS_BIT | \ + USBDMINUS_BIT | \ + 0 ) + +#define P1IO_INPUT_BITS (uint32_t) ( \ + 0 ) + +#define P2IO_INPUT_BITS (uint32_t) ( \ + RXD1_BIT | \ + DSR1_BIT | \ + BOOT_BIT | \ + 0 ) + +#define P3IO_INPUT_BITS (uint32_t) ( \ + 0 ) + +#define P4IO_INPUT_BITS (uint32_t) ( \ + 0 ) + +#define P0IO_ZERO_BITS (uint32_t) ( \ + P0_0_UNUSED_BIT | \ + P0_1_UNUSED_BIT | \ + P0_7_UNUSED_BIT | \ + P0_8_UNUSED_BIT | \ + P0_9_UNUSED_BIT | \ + P0_10_UNUSED_BIT | \ + P0_11_UNUSED_BIT | \ + RTS1_BIT | \ + 0 ) + +#define P1IO_ZERO_BITS (uint32_t) ( \ + P1_0_UNUSED_BIT | \ + P1_1_UNUSED_BIT | \ + P1_4_UNUSED_BIT | \ + P1_8_UNUSED_BIT | \ + P1_9_UNUSED_BIT | \ + P1_10_UNUSED_BIT | \ + P1_14_UNUSED_BIT | \ + P1_15_UNUSED_BIT | \ + P1_18_UNUSED_BIT | \ + P1_19_UNUSED_BIT | \ + P1_20_UNUSED_BIT | \ + P1_22_UNUSED_BIT | \ + P1_25_UNUSED_BIT | \ + P1_26_UNUSED_BIT | \ + P1_28_UNUSED_BIT | \ + P1_29_UNUSED_BIT | \ + P1_31_UNUSED_BIT | \ + 0 ) + +#define P2IO_ZERO_BITS (uint32_t) ( \ + P2_2_UNUSED_BIT | \ + P2_3_UNUSED_BIT | \ + P2_9_UNUSED_BIT | \ + 0 ) + +#define P3IO_ZERO_BITS (uint32_t) ( \ + 0 ) + +#define P4IO_ZERO_BITS (uint32_t) ( \ + P4_28_UNUSED_BIT | \ + P4_29_UNUSED_BIT | \ + 0 ) + +#define P0IO_ONE_BITS (uint32_t) ( \ + TXD0_BIT | \ + EXT_TEMP_TYPE_BIT | \ + 0 ) + +#define P1IO_ONE_BITS (uint32_t) ( \ + OUT1_BIT | \ + OUT2_BIT | \ + EXT_TEMP_SW_BIT | \ + 0 ) + +#define P2IO_ONE_BITS (uint32_t) ( \ + TXD1_BIT | \ + LED1_BIT | \ + LED2_BIT | \ + LED3_BIT | \ + LED4_BIT | \ + 0 ) + +#define P3IO_ONE_BITS (uint32_t) ( \ + 0 ) + +#define P4IO_ONE_BITS (uint32_t) ( \ + 0 ) + +#define P0IO_OUTPUT_BITS (uint32_t) ( \ + P0IO_ZERO_BITS | \ + P0IO_ONE_BITS ) + +#define P1IO_OUTPUT_BITS (uint32_t) ( \ + P1IO_ZERO_BITS | \ + P1IO_ONE_BITS ) + +#define P2IO_OUTPUT_BITS (uint32_t) ( \ + P2IO_ZERO_BITS | \ + P2IO_ONE_BITS ) + +#define P3IO_OUTPUT_BITS (uint32_t) ( \ + P3IO_ZERO_BITS | \ + P3IO_ONE_BITS ) + +#define P4IO_OUTPUT_BITS (uint32_t) ( \ + P4IO_ZERO_BITS | \ + P4IO_ONE_BITS ) + + + +/***************************************************************************/ +/* io functions */ +#define LED_GP LED2_BIT /* GENREAL PURPOSE LED */ +#define LED_ERR LED3_BIT + +/***************************************************************************/ +/* io functions */ +#define IN_PORT GPIO0->FIO +#define OUT_PORT GPIO1->FIO +#define LED_PORT GPIO2->FIO + +#define CREATE_PORT_NAME_PIN(port) port##PIN +#define CREATE_PORT_NAME_CLR(port) port##CLR +#define CREATE_PORT_NAME_SET(port) port##SET + +#define GET_IN_PIN(port,in) ((CREATE_PORT_NAME_PIN(port) & in)?1:0) +#define GET_IN_PORT(port) (CREATE_PORT_NAME_PIN(port)) +#define SET_OUT_PIN(port,out) (CREATE_PORT_NAME_SET(port)=out) +#define CLR_OUT_PIN(port,out) (CREATE_PORT_NAME_CLR(port)=out) + +/***************************************************************************/ +/* watchdog */ +#define WATCHDOG_ENABLED +#define WATCHDOG_TIMEOUT_MS 1000 + +/***************************************************************************/ +/* uLan configuration */ + +#ifdef UL_LOG_ENABLE + #undef UL_LOG_ENABLE +#endif + +#ifdef ULD_DEFAULT_BUFFER_SIZE + #undef ULD_DEFAULT_BUFFER_SIZE + #define ULD_DEFAULT_BUFFER_SIZE 0x0800 +#endif + +#define UL_DRV_SYSLESS_PORT UART1_BASE +#define UL_DRV_SYSLESS_BAUD 19200 +#define UL_DRV_SYSLESS_IRQ UART1_IRQn +#define UL_DRV_SYSLESS_MY_ADR_DEFAULT 1 + +#define watchdog_feed lpc_watchdog_feed +#define kvpb_erase lpcisp_kvpb_erase +#define kvpb_copy lpcisp_kvpb_copy +#define kvpb_flush lpcisp_kvpb_flush +#define KVPB_DEFAULT_FLAGS KVPB_DESC_DOUBLE|KVPB_DESC_CHUNKWO + + + + + + + + +#endif /* _SYSTEM_DEF_H_ */ diff --git a/embedded/board/arm/lpc17xx-common/libs/Makefile b/embedded/board/arm/lpc17xx-common/libs/Makefile new file mode 100644 index 0000000..76b56fd --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/Makefile @@ -0,0 +1,14 @@ +# Generic directory or leaf node makefile for OCERA make framework + +ifndef MAKERULES_DIR +MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) ) +endif + +ifeq ($(MAKERULES_DIR),) +all : default +.DEFAULT:: + @echo -e "\nThe Makefile.rules has not been found in this or parent directory\n" +else +include $(MAKERULES_DIR)/Makefile.rules +endif + diff --git a/embedded/board/arm/lpc17xx-common/libs/Makefile.omk b/embedded/board/arm/lpc17xx-common/libs/Makefile.omk new file mode 100644 index 0000000..1e281da --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/Makefile.omk @@ -0,0 +1,3 @@ +# -*- makefile -*- + +SUBDIRS = bspbase ldscripts diff --git a/embedded/board/arm/lpc17xx-common/libs/bspbase/Makefile b/embedded/board/arm/lpc17xx-common/libs/bspbase/Makefile new file mode 100644 index 0000000..76b56fd --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/bspbase/Makefile @@ -0,0 +1,14 @@ +# Generic directory or leaf node makefile for OCERA make framework + +ifndef MAKERULES_DIR +MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) ) +endif + +ifeq ($(MAKERULES_DIR),) +all : default +.DEFAULT:: + @echo -e "\nThe Makefile.rules has not been found in this or parent directory\n" +else +include $(MAKERULES_DIR)/Makefile.rules +endif + diff --git a/embedded/board/arm/lpc17xx-common/libs/bspbase/Makefile.omk b/embedded/board/arm/lpc17xx-common/libs/bspbase/Makefile.omk new file mode 100644 index 0000000..c0d6e4d --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/bspbase/Makefile.omk @@ -0,0 +1,23 @@ +# -*- makefile -*- + +default_CONFIG += CONFIG_OC_UL_DRV_SYSLESS=x +default_CONFIG += CONFIG_KEYVAL=x +default_CONFIG += CONFIG_STDIO_COM_PORT=x +default_CONFIG += CONFIG_OC_UL_DRV_U450_VARPINS=x +default_CONFIG += CONFIG_OC_UL_DRV_U450_VARPINS_MSRSWAP=x +default_CONFIG += CONFIG_OC_UL_DRV_U450_VARPINS_DIRNEG=x +default_CONFIG += CONFIG_OC_I2C_DRV_SYSLESS=x + +LOCAL_CONFIG_H = local_config.h + +INCLUDES += -I . + +include_HEADERS = bspbase.h + +lib_LIBRARIES = bspbase + +bspbase_SOURCES = bsp0hwinit.c + +ifneq ($(CONFIG_STDIO_COM_PORT),) +bspbase_SOURCES += uart.c +endif #CONFIG_STDIO_COM_PORT diff --git a/embedded/board/arm/lpc17xx-common/libs/bspbase/bsp0hwinit.c b/embedded/board/arm/lpc17xx-common/libs/bspbase/bsp0hwinit.c new file mode 100644 index 0000000..8525b16 --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/bspbase/bsp0hwinit.c @@ -0,0 +1,463 @@ +#include "local_config.h" +#include +#include +#include +#include +#ifdef CONFIG_KEYVAL + #include + #include + #include +#endif /* CONFIG_KEYVAL */ +#ifdef CONFIG_STDIO_COM_PORT + #include +#endif +#ifdef CONFIG_OC_UL_DRV_SYSLESS + #include + #include + #include + #include + #include + extern long int uld_jiffies; +#endif /* CONFIG_OC_UL_DRV_SYSLESS */ +#ifdef CONFIG_OC_I2C_DRV_SYSLESS + #include +#endif /* CONFIG_OC_I2C_DRV_SYSLESS */ + + +/* timers */ +volatile lt_ticks_t sys_timer_ticks; +void (*timer0_isr_appl_call)(void); + +#ifdef CONFIG_OC_I2C_DRV_SYSLESS +#define I2C_DRV_NA_MSTIMEOUT 10 +i2c_drv_t i2c_drv; +int i2c_drv_na_timer=0; +#endif /* CONFIG_OC_I2C_DRV_SYSLESS */ + +static void sysInit(void) +{ + + //lpc_pll_off(); + //lpc_pll_on(); + system_clock_init(); + + // setup the parallel port pin + GPIO0->FIOCLR = P0IO_ZERO_BITS; // clear the ZEROs output + GPIO0->FIOSET = P0IO_ONE_BITS; // set the ONEs output + GPIO0->FIODIR = P0IO_OUTPUT_BITS; // set the output bit direction + + GPIO1->FIOCLR = P1IO_ZERO_BITS; // clear the ZEROs output + GPIO1->FIOSET = P1IO_ONE_BITS; // set the ONEs output + GPIO1->FIODIR = P1IO_OUTPUT_BITS; // set the output bit direction + + GPIO2->FIOCLR = P2IO_ZERO_BITS; // clear the ZEROs output + GPIO2->FIOSET = P2IO_ONE_BITS; // set the ONEs output + GPIO2->FIODIR = P2IO_OUTPUT_BITS; // set the output bit direction + + GPIO3->FIOCLR = P3IO_ZERO_BITS; // clear the ZEROs output + GPIO3->FIOSET = P3IO_ONE_BITS; // set the ONEs output + GPIO3->FIODIR = P3IO_OUTPUT_BITS; // set the output bit direction + + GPIO4->FIOCLR = P4IO_ZERO_BITS; // clear the ZEROs output + GPIO4->FIOSET = P4IO_ONE_BITS; // set the ONEs output + GPIO4->FIODIR = P4IO_OUTPUT_BITS; // set the output bit direction +} + +IRQ_HANDLER_FNC(timer0_isr) +{ + unsigned int ir; + + ir=TIM0->IR; + if (ir&0x01) { + do { + if(timer0_isr_appl_call!=NULL) + timer0_isr_appl_call(); + TIM0->MR0 += PCLK / SYS_TIMER_HZ; + TIM0->IR=0x01; // Clear match0 interrupt + #ifdef CONFIG_OC_UL_DRV_SYSLESS + uld_jiffies++; + #endif + #ifdef CONFIG_OC_I2C_DRV_SYSLESS + if (i2c_drv.flags&I2C_DRV_MS_INPR) { + if (i2c_drv.flags&I2C_DRV_NA) { + i2c_drv_na_timer++; + if (i2c_drv_na_timer>I2C_DRV_NA_MSTIMEOUT) { + if (i2c_drv.stroke_fnc) + i2c_drv.stroke_fnc(&i2c_drv); + i2c_drv_na_timer=0; + } + } else { + i2c_drv_na_timer=0; + } + i2c_drv.flags|=I2C_DRV_NA; + } + #endif + sys_timer_ticks++; + } while (((int32_t)(TIM0->MR0-TIM0->TC))<0); + } + return IRQ_HANDLED; +} + +void timerInit(void) +{ + sys_timer_ticks=0; + + request_irq(TIMER0_IRQn, timer0_isr, 0, NULL,NULL); + enable_irq(TIMER0_IRQn); + + TIM0->TC=0; + TIM0->MCR=0; + + TIM0->MR0= PCLK / SYS_TIMER_HZ; + TIM0->MCR|=1; /* TMCR_MR0_I; */ + + TIM0->TCR = 1; /* Run timer 0*/ +} + +#ifdef CONFIG_STDIO_COM_PORT + +int uartcon_write(int file, const char * ptr, int len) +{ + int cnt; + unsigned char ch; + for(cnt=0;cntlen=0; + + if(ul_iac_mem_head_rd((uint8_t *)ibuff, msginfo->len,&mtype,&start,&len)) + return UL_IAC_RC_PROC; + + if (mtype==0x00) { + data->len=len; + data->buff=(char*)start; + return UL_IAC_RC_FREEMSG; + } + return UL_IAC_RC_PROC; +} + +int ul_iac_call_erm(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data) +{ + uint32_t mtype,start,len; + + data->len=0; + + if(ul_iac_mem_head_rd((uint8_t *)ibuff, msginfo->len,&mtype,&start,&len)) + return UL_IAC_RC_PROC; + + #ifdef CONFIG_KEYVAL + if (mtype==0x01) { + lpcisp_erase((void*)start,len); + data->len=0; + return UL_IAC_RC_FREEMSG; + } + #endif /* CONFIG_KEYVAL */ + return UL_IAC_RC_PROC; +} + +int ul_iac_call_wrm(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data) +{ + uint32_t mtype,start,len; + + data->len=0; + + if(ul_iac_mem_head_rd((uint8_t *)ibuff, msginfo->len,&mtype,&start,&len)) + return UL_IAC_RC_PROC; + + if (mtype==0x00) { + memcpy((void*)start,data->buff,data->len); + return UL_IAC_RC_FREEMSG; + } + #ifdef CONFIG_KEYVAL + if (mtype==0x01) { + lpcisp_write((char*)start, data->buff, ISP_RAM2FLASH_BLOCK_SIZE); + return UL_IAC_RC_FREEMSG; + } + #endif /* CONFIG_KEYVAL */ + return UL_IAC_RC_PROC; +} + + +int ul_iac_call_deb(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data) +{ + uint32_t debcmd,mtype,start; + uint8_t *p=(uint8_t*)ibuff; + + if (msginfo->len<1) return UL_IAC_RC_PROC; + debcmd=*(p++); + switch (debcmd) { + case 0x10: /* goto */ + data->len=0; + if (msginfo->len<5) return UL_IAC_RC_PROC; + mtype=*(p++); + mtype+=*(p++)<<8; + start=*(p++); + start+=*(p++)<<8; + if(mtype&UL_MTYPE_START32BIT){ + mtype&=~UL_MTYPE_START32BIT; + if (msginfo->len<7) return UL_IAC_RC_PROC; + start+=(uint32_t)*(p++)<<16; + start+=(uint32_t)*(p++)<<24; + } + if (mtype==0x00) + ((void (*)())start)(); + default:break; + } + return UL_IAC_RC_PROC; +} + +int ul_iac_call_res(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data) +{ + uint32_t rescmd,pass; + uint8_t *p=(uint8_t*)ibuff; + + if (msginfo->len<1) return UL_IAC_RC_PROC; + rescmd=*(p++); + switch (rescmd) { + case ULRES_CPU: /* CPU */ + data->len=0; + if (msginfo->len<3) return UL_IAC_RC_PROC; + pass=*(p++); + pass+=*(p++)<<8; + if (pass==0xaa55) { +// MEMMAP=MEMMAP_FLASH; + lpc_watchdog_init(1,10); /* 10ms */ + lpc_watchdog_feed(); + while(1); + } + default:break; + } + return UL_IAC_RC_PROC; +} + +int uLanInit() +{ + struct ul_drv *udrv; + unsigned int pinsel1_mask = 0; + unsigned int pinsel1_set = 0; + unsigned int pinsel4_mask = 0; + unsigned int pinsel4_set = 0; + + /* set rs485 mode for UART1 */ + #if TXD1_BIT == BIT(15) + PINCON->PINSEL0 = (PINCON->PINSEL0 & ~0xC0000000) | 0x40000000; /* rxd on P0.15 */ + #elif TXD1_BIT == BIT(0) + pinsel4_mask |= 3 << (0*2); + pinsel4_set |= 2 << (0*2); + #else + #error TXD1_BIT is not set or valid + #endif + + #if RXD1_BIT == BIT(16) + pinsel1_mask |= 3 << ((16-16)*2); + pinsel1_set |= 1 << ((16-16)*2); + #elif RXD1_BIT == BIT(1) + pinsel4_mask |= 3 << (1*2); + pinsel4_set |= 2 << (1*2); + #else + #error RXD1_BIT is not set or valid + #endif + + #ifdef CTS1_BIT + #if CTS1_BIT == BIT(17) + pinsel1_mask |= 3 << ((17-16)*2); + pinsel1_set |= 1 << ((17-16)*2); + #elif CTS1_BIT == BIT(2) + pinsel4_mask |= 3 << (2*2); + pinsel4_set |= 2 << (2*2); + #else + #error CTS1_BIT is not valid + #endif + #endif + + #ifdef DSR1_BIT + #if DSR1_BIT == BIT(19) + pinsel1_mask |= 3 << ((19-16)*2); + pinsel1_set |= 1 << ((19-16)*2); + #elif DSR1_BIT == BIT(4) + pinsel4_mask |= 3 << (4*2); + pinsel4_set |= 2 << (4*2); + #else + #error CTS1_BIT is not valid + #endif + #endif + + #if RTS1_BIT == BIT(22) + pinsel1_mask |= 3 << ((22-16)*2); + pinsel1_set |= 1 << ((22-16)*2); + #elif RTS1_BIT == BIT(7) + pinsel4_mask |= 3 << (7*2); + pinsel4_set |= 2 << (7*2); + #else + #error RTS1_BIT is not set or valid + #endif + + /* port 0 .. 0x00003000; 0x00001000; rts(uDIR) */ + PINCON->PINSEL1 = (PINCON->PINSEL1 & ~pinsel1_mask) | pinsel1_set; + /* port 2 .. 0x00000C0F; 0x0000080A; dsr(rxd), rxd, txd */ + PINCON->PINSEL4 = (PINCON->PINSEL4 & ~pinsel4_mask) | pinsel4_set; + + udrv=ul_drv_new(UL_DRV_SYSLESS_PORT, /* port */ + UL_DRV_SYSLESS_IRQ, /* irq */ + UL_DRV_SYSLESS_BAUD, /* baud */ + UL_DRV_SYSLESS_MY_ADR_DEFAULT, /* my adr */ + #ifdef CONFIG_OC_UL_DRV_U450_VARPINS + #if defined(CONFIG_OC_UL_DRV_U450_VARPINS_DIRNEG) && defined(CONFIG_OC_UL_DRV_U450_VARPINS_MSRSWAP) + "16450-dirneg-msrswap", /* chip name */ + #elif defined(CONFIG_OC_UL_DRV_U450_VARPINS_MSRSWAP) + "16450-msrswap", /* chip name */ + #elif defined(CONFIG_OC_UL_DRV_U450_VARPINS_DIRNEG) + "16450-dirneg", /* chip name */ + #else + "16450", /* chip name */ + #endif + #else /*CONFIG_OC_UL_DRV_U450_VARPINS*/ + "16450", /* chip name */ + #endif /*CONFIG_OC_UL_DRV_U450_VARPINS*/ + 0); /* baud base - default */ + + if (udrv==NULL) + return -1; + + ul_drv_add_iac(udrv,UL_CMD_RDM,UL_IAC_OP_SND,ul_iac_call_rdm,NULL,0,0,NULL,0); + ul_drv_add_iac(udrv,UL_CMD_ERM,UL_IAC_OP_CALLBACK,ul_iac_call_erm,NULL,0,UL_IAC_BFL_CB_OFFLT,NULL,0); + ul_drv_add_iac(udrv,UL_CMD_WRM,UL_IAC_OP_REC,ul_iac_call_wrm,(char*)lpciap_buff,0,UL_IAC_BFL_CB_OFFLT,NULL,0); + ul_drv_add_iac(udrv,UL_CMD_DEB,UL_IAC_OP_CALLBACK,ul_iac_call_deb,NULL,0,UL_IAC_BFL_CB_OFFLT,NULL,0); + ul_drv_add_iac(udrv,UL_CMD_RES,UL_IAC_OP_CALLBACK,ul_iac_call_res,NULL,0,UL_IAC_BFL_CB_OFFLT,NULL,0); + + return ul_drv_add_dev(udrv); +} +#endif /* CONFIG_OC_UL_DRV_SYSLESS */ + +#ifdef CONFIG_OC_I2C_DRV_SYSLESS + +int +i2cInit(void) +{ + #if I2C_DRV_SYSLESS_PORT == I2C0_BASE + SC->PCONP |= (1 << 7); /*PI2C0*/ + /* SDA0 P0.27, SCL0 P0.28 */ + PINCON->PINSEL1 = (PINCON->PINSEL0 & ~0x03c00000) | 0x01400000; + + #elif I2C_DRV_SYSLESS_PORT == I2C1_BASE + SC->PCONP |= (1 << 19); /*PI2C1*/ + #if SCL1_BIT == BIT(1) + /* SDA1 P0.0, SCL1 P0.1 */ + PINCON->PINSEL0 |= 0x0000000f; + PINCON->PINMODE0 = (PINCON->PINMODE0 & ~0x0000000f) | 0x0000000A; + PINCON->PINMODE_OD0 |= 0x00000003; + #elif SCL1_BIT == BIT(20) + /* SDA1 P0.19, SCL1 P0.20 */ + PINCON->PINSEL1 |= 0x000003c0; + PINCON->PINMODE1 = (PINCON->PINMODE1 & ~0x000003c0) | 0x00000280; + PINCON->PINMODE_OD0 |= 0x00180000; + #else + #error Unknown SCL1_BIT pin position + #endif + + #elif I2C_DRV_SYSLESS_PORT == I2C2_BASE + SC->PCONP |= (1 << 26); /*PI2C2*/ + /* SDA2 P0.10, SCL2 P0.11 */ + PINCON->PINSEL0 = (PINCON->PINSEL0 & ~0x00f00000) | 0x00A00000; + PINCON->PINMODE0 = (PINCON->PINMODE0 & ~0x00f00000) | 0x00A00000; + PINCON->PINMODE_OD0 |= 0x00000c00; + #else + #error unknown I2C_DRV_SYSLESS_PORT address + #endif + + if (i2c_drv_init(&i2c_drv, + I2C_DRV_SYSLESS_PORT, + I2C_DRV_SYSLESS_IRQ, + I2C_DRV_SYSLESS_BITRATE, + I2C_DRV_SYSLESS_SLADR)<0) return -1; + + return 1; +} + +#endif /*CONFIG_OC_I2C_DRV_SYSLESS*/ + + +void _setup_board() +{ + + // initialize the system + sysInit(); + + #ifdef WATCHDOG_ENABLED + lpc_watchdog_init(1,WATCHDOG_TIMEOUT_MS); + lpc_watchdog_feed(); + #endif /* WATCHDOG_ENABLED */ + + #ifdef CONFIG_STDIO_COM_PORT + uart0Init( B57600 , UART_8N1, UART_FIFO_8); + init_system_stub(); + #endif /* CONFIG_STDIO_COM_PORT */ + + // initialize the system timer + timerInit(); + + #ifdef CONFIG_OC_UL_DRV_SYSLESS +// uld_debug_flg=0x3ff; + uLanInit(); + #endif /* CONFIG_OC_UL_DRV_SYSLESS */ + + #ifdef CONFIG_OC_I2C_DRV_SYSLESS + i2cInit(); + #endif /* CONFIG_OC_I2C_DRV_SYSLESS */ + +} diff --git a/embedded/board/arm/lpc17xx-common/libs/bspbase/bspbase.h b/embedded/board/arm/lpc17xx-common/libs/bspbase/bspbase.h new file mode 100644 index 0000000..5369f81 --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/bspbase/bspbase.h @@ -0,0 +1,11 @@ +#ifndef _BSPBASE_H +#define _BSPBASE_H + +#include +#include + +extern volatile lt_ticks_t sys_timer_ticks; + +#define get_sys_timer_ticks() sys_timer_ticks + +#endif /* _BSPBASE_H */ diff --git a/embedded/board/arm/lpc17xx-common/libs/bspbase/serial_reg.h b/embedded/board/arm/lpc17xx-common/libs/bspbase/serial_reg.h new file mode 100644 index 0000000..09feb95 --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/bspbase/serial_reg.h @@ -0,0 +1,282 @@ +/* + * include/linux/serial_reg.h + * + * Copyright (C) 1992, 1994 by Theodore Ts'o. + * + * Redistribution of this file is permitted under the terms of the GNU + * Public License (GPL) + * + * These are the UART port assignments, expressed as offsets from the base + * register. These assignments should hold for any serial port based on + * a 8250, 16450, or 16550(A). + */ + +#ifndef _LINUX_SERIAL_REG_H +#define _LINUX_SERIAL_REG_H + +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */ +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */ +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */ +#define UART_TRG 0 /* (LCR=BF) FCTR bit 7 selects Rx or Tx + * In: Fifo count + * Out: Fifo custom trigger levels + * XR16C85x only */ + +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */ +#define UART_IER 1 /* Out: Interrupt Enable Register */ +#define UART_FCTR 1 /* (LCR=BF) Feature Control Register + * XR16C85x only */ + +#define UART_IIR 2 /* In: Interrupt ID Register */ +#define UART_FCR 2 /* Out: FIFO Control Register */ +#define UART_EFR 2 /* I/O: Extended Features Register */ + /* (DLAB=1, 16C660 only) */ + +#define UART_LCR 3 /* Out: Line Control Register */ +#define UART_MCR 4 /* Out: Modem Control Register */ +#define UART_LSR 5 /* In: Line Status Register */ +#define UART_MSR 6 /* In: Modem Status Register */ +#define UART_SCR 7 /* I/O: Scratch Register */ +#define UART_EMSR 7 /* (LCR=BF) Extended Mode Select Register + * FCTR bit 6 selects SCR or EMSR + * XR16c85x only */ + +/* + * These are the definitions for the FIFO Control Register + * (16650 only) + */ +#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ +/* 16650 redefinitions */ +#define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */ +#define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */ +#define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */ +#define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */ +#define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */ +#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */ +#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */ +#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */ +/* TI 16750 definitions */ +#define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode */ + +/* + * These are the definitions for the Line Control Register + * + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting + * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. + */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ +#define UART_LCR_SBC 0x40 /* Set break control */ +#define UART_LCR_SPAR 0x20 /* Stick parity (?) */ +#define UART_LCR_EPAR 0x10 /* Even parity select */ +#define UART_LCR_PARITY 0x08 /* Parity Enable */ +#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ +#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ +#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ +#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ + +/* + * These are the definitions for the Line Status Register + */ +#define UART_LSR_TEMT 0x40 /* Transmitter empty */ +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ +#define UART_LSR_BI 0x10 /* Break interrupt indicator */ +#define UART_LSR_FE 0x08 /* Frame error indicator */ +#define UART_LSR_PE 0x04 /* Parity error indicator */ +#define UART_LSR_OE 0x02 /* Overrun error indicator */ +#define UART_LSR_DR 0x01 /* Receiver data ready */ + +/* + * These are the definitions for the Interrupt Identification Register + */ +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ + +#define UART_IIR_MSI 0x00 /* Modem status interrupt */ +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ + +/* + * These are the definitions for the Interrupt Enable Register + */ +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ +/* + * Sleep mode for ST16650 and TI16750. + * Note that for 16650, EFR-bit 4 must be selected as well. + */ +#define UART_IERX_SLEEP 0x10 /* Enable sleep mode */ + +/* + * These are the definitions for the Modem Control Register + */ +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define UART_MCR_OUT2 0x08 /* Out2 complement */ +#define UART_MCR_OUT1 0x04 /* Out1 complement */ +#define UART_MCR_RTS 0x02 /* RTS complement */ +#define UART_MCR_DTR 0x01 /* DTR complement */ + +/* + * These are the definitions for the Modem Status Register + */ +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ +#define UART_MSR_RI 0x40 /* Ring Indicator */ +#define UART_MSR_DSR 0x20 /* Data Set Ready */ +#define UART_MSR_CTS 0x10 /* Clear to Send */ +#define UART_MSR_DDCD 0x08 /* Delta DCD */ +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /* Delta DSR */ +#define UART_MSR_DCTS 0x01 /* Delta CTS */ +#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ + +/* + * These are the definitions for the Extended Features Register + * (StarTech 16C660 only, when DLAB=1) + */ +#define UART_EFR_CTS 0x80 /* CTS flow control */ +#define UART_EFR_RTS 0x40 /* RTS flow control */ +#define UART_EFR_SCD 0x20 /* Special character detect */ +#define UART_EFR_ECB 0x10 /* Enhanced control bit */ +/* + * the low four bits control software flow control + */ + +/* + * These register definitions are for the 16C950 + */ +#define UART_ASR 0x01 /* Additional Status Register */ +#define UART_RFL 0x03 /* Transmitter FIFO level */ +#define UART_TFL 0x04 /* Receiver FIFO level */ +#define UART_ICR 0x05 /* Index Control Register */ + +/* The 16950 ICR registers */ +#define UART_ACR 0x00 /* Additional Control Register */ +#define UART_CPR 0x01 /* Clock Prescalar Register */ +#define UART_TCR 0x02 /* Times Clock Register */ +#define UART_CKS 0x03 /* Clock Select Register */ +#define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */ +#define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */ +#define UART_FCL 0x06 /* Flow Control Level Lower */ +#define UART_FCH 0x07 /* Flow Control Level Higher */ +#define UART_ID1 0x08 /* ID #1 */ +#define UART_ID2 0x09 /* ID #2 */ +#define UART_ID3 0x0A /* ID #3 */ +#define UART_REV 0x0B /* Revision */ +#define UART_CSR 0x0C /* Channel Software Reset */ +#define UART_NMR 0x0D /* Nine-bit Mode Register */ +#define UART_CTR 0xFF + +/* + * The 16C950 Additional Control Reigster + */ +#define UART_ACR_RXDIS 0x01 /* Receiver disable */ +#define UART_ACR_TXDIS 0x02 /* Receiver disable */ +#define UART_ACR_DSRFC 0x04 /* DSR Flow Control */ +#define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */ +#define UART_ACR_ICRRD 0x40 /* ICR Read enable */ +#define UART_ACR_ASREN 0x80 /* Additional status enable */ + +/* + * These are the definitions for the Feature Control Register + * (XR16C85x only, when LCR=bf; doubles with the Interrupt Enable + * Register, UART register #1) + */ +#define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */ +#define UART_FCTR_RTS_4DELAY 0x01 +#define UART_FCTR_RTS_6DELAY 0x02 +#define UART_FCTR_RTS_8DELAY 0x03 +#define UART_FCTR_IRDA 0x04 /* IrDa data encode select */ +#define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */ +#define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */ +#define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */ +#define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */ +#define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */ +#define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */ +#define UART_FCTR_RX 0x00 /* Programmable trigger mode select */ +#define UART_FCTR_TX 0x80 /* Programmable trigger mode select */ + +/* + * These are the definitions for the Enhanced Mode Select Register + * (XR16C85x only, when LCR=bf and FCTR bit 6=1; doubles with the + * Scratch register, UART register #7) + */ +#define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */ +#define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */ + +/* + * These are the definitions for the Programmable Trigger + * Register (XR16C85x only, when LCR=bf; doubles with the UART RX/TX + * register, UART register #0) + */ +#define UART_TRG_1 0x01 +#define UART_TRG_4 0x04 +#define UART_TRG_8 0x08 +#define UART_TRG_16 0x10 +#define UART_TRG_32 0x20 +#define UART_TRG_64 0x40 +#define UART_TRG_96 0x60 +#define UART_TRG_120 0x78 +#define UART_TRG_128 0x80 + +/* + * These definitions are for the RSA-DV II/S card, from + * + * Kiyokazu SUTO + */ + +#define UART_RSA_BASE (-8) + +#define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */ + +#define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */ +#define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */ +#define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */ +#define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */ + +#define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */ + +#define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */ +#define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */ +#define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */ +#define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */ +#define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */ + +#define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */ + +#define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */ +#define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */ +#define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */ +#define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */ +#define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */ +#define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */ +#define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occured (1) */ +#define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occured */ + +#define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */ + +#define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */ + +#define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */ + +#define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */ + +/* + * The RSA DSV/II board has two fixed clock frequencies. One is the + * standard rate, and the other is 8 times faster. + */ +#define SERIAL_RSA_BAUD_BASE (921600) +#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8) + +#endif /* _LINUX_SERIAL_REG_H */ + diff --git a/embedded/board/arm/lpc17xx-common/libs/bspbase/uart.c b/embedded/board/arm/lpc17xx-common/libs/bspbase/uart.c new file mode 100644 index 0000000..f7c985e --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/bspbase/uart.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * + * $RCSfile$ + * $Revision$ + * + * This module provides interface routines to the LPC ARM UARTs. + * Copyright 2004, R O SoftWare + * No guarantees, warrantees, or promises, implied or otherwise. + * May be used for hobby or commercial purposes provided copyright + * notice remains intact. + * + * reduced to see what has to be done for minimum UART-support by mthomas + *****************************************************************************/ + +// #warning "this is a reduced version of the R O Software code" + +#include +#include "uart.h" +#include "serial_reg.h" + +/* on LPC17xx: UART0 TX-Pin=P0.2, RX-Pin=P0.3 + PINSEL0 has to be set to "UART-Function" = Function "01" + for Pin 0.2 and 0.3 */ + +#define PINSEL_BIT_TXD0 (2*2) +#define PINSEL_BIT_RXD0 (3*2) +#define PINSEL_FIRST_ALT_FUNC 1 +#define PINSEL_SECOND_ALT_FUNC 2 + +// Values of Bits 4-7 in PINSEL to activate UART0 +#define UART0_PINSEL ((PINSEL_FIRST_ALT_FUNC<PINSEL0 = (PINCON->PINSEL0 & ~UART0_PINMASK) | UART0_PINSEL; + + UART0->IER = 0x00; // disable all interrupts + //UART0->IIR = 0x00; // clear interrupt ID register + //UART0->LSR = 0x00; // clear line status register + + baud *= 16; + baud_div = (PCLK + baud / 4) / baud; + + // set the baudrate - DLAB must be set to access DLL/DLM + UART0->LCR = (1<DLL = (uint8_t)baud_div; // set for baud low byte + UART0->DLM = (uint8_t)(baud_div >> 8); // set for baud high byte + + // set the number of characters and other + // user specified operating parameters + // Databits, Parity, Stopbits - Settings in Line Control Register + UART0->LCR = (mode & ~(1<FCR = fmode; + + for(i=0;i<65000;i++); +} + +int uart0Putch(int ch) +{ + while (!(UART0->LSR & UART_LSR_THRE)) // wait for TX buffer to empty + continue; // also either WDOG() or swap() + + UART0->THR = (uint8_t)ch; // put char to Transmit Holding Register + return (uint8_t)ch; // return char ("stdio-compatible"?) +} + +int uart0PutchNW(int ch) +{ + if (!(UART0->LSR & UART_LSR_THRE)) // wait for TX buffer to empty + return -1; // also either WDOG() or swap() + + UART0->THR = (uint8_t)ch; // put char to Transmit Holding Register + return (uint8_t)ch; // return char ("stdio-compatible"?) +} + +const char *uart0Puts(const char *string) +{ + char ch; + + while ((ch = *string)) { + if (uart0Putch(ch)<0) break; + string++; + } + + return string; +} + +int uart0TxEmpty(void) +{ + return (UART0->LSR & (UART_LSR_THRE | UART_LSR_TEMT)) == (UART_LSR_THRE | UART_LSR_TEMT); +} + +void uart0TxFlush(void) +{ + UART0->FCR |= UART_FCR_CLEAR_XMIT; // clear the TX fifo +} + + +/* Returns: character on success, -1 if no character is available */ +int uart0Getch(void) +{ + if (UART0->LSR & UART_LSR_DR) // check if character is available + return UART0->RBR; // return character + + return -1; +} + +/* Returns: character on success, waits */ +int uart0GetchW(void) +{ + while ( !(UART0->LSR & UART_LSR_DR) ); // wait for character + return UART0->RBR; // return character +} + diff --git a/embedded/board/arm/lpc17xx-common/libs/bspbase/uart.h b/embedded/board/arm/lpc17xx-common/libs/bspbase/uart.h new file mode 100644 index 0000000..e569875 --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/bspbase/uart.h @@ -0,0 +1,64 @@ +/****************************************************************************** + * based on software from: + * Copyright 2004, R O SoftWare + * No guarantees, warrantees, or promises, implied or otherwise. + * May be used for hobby or commercial purposes provided copyright + * notice remains intact. + * + * reduced to learn what has to be done to enable and use UART0 + *****************************************************************************/ +#ifndef INC_UART_H +#define INC_UART_H + +#include +#include "serial_reg.h" + + +/////////////////////////////////////////////////////////////////////////////// +// Prehistoric solutions slect baudrates according to some magic constants +// Use SI defined Hz/Baud units for selection of baudrate directly for +// uart0Init() and uart1Init() +#define UART_BAUD(baud) (baud) + +/////////////////////////////////////////////////////////////////////////////// +// Definitions for typical UART 'baud' settings +#define B1200 UART_BAUD(1200) +#define B9600 UART_BAUD(9600) +#define B19200 UART_BAUD(19200) +#define B38400 UART_BAUD(38400) +#define B57600 UART_BAUD(57600) +#define B115200 UART_BAUD(115200) + +/////////////////////////////////////////////////////////////////////////////// +// Definitions for typical UART 'mode' settings +#define UART_8N1 (uint8_t)(UART_LCR_WLEN8 ) +#define UART_7N1 (uint8_t)(UART_LCR_WLEN7 ) +#define UART_8N2 (uint8_t)(UART_LCR_WLEN8 | UART_LCR_STOP) +#define UART_7N2 (uint8_t)(UART_LCR_WLEN7 | UART_LCR_STOP) +#define UART_8E1 (uint8_t)(UART_LCR_WLEN8 | UART_LCR_PARITY | UART_LCR_EPAR) +#define UART_7E1 (uint8_t)(UART_LCR_WLEN7 | UART_LCR_PARITY | UART_LCR_EPAR) +#define UART_8E2 (uint8_t)(UART_LCR_WLEN8 | UART_LCR_PARITY | UART_LCR_EPAR | UART_LCR_STOP) +#define UART_7E2 (uint8_t)(UART_LCR_WLEN7 | UART_LCR_PARITY | UART_LCR_EPAR | UART_LCR_STOP) +#define UART_8O1 (uint8_t)(UART_LCR_WLEN8 | UART_LCR_PARITY ) +#define UART_7O1 (uint8_t)(UART_LCR_WLEN7 | UART_LCR_PARITY ) +#define UART_8O2 (uint8_t)(UART_LCR_WLEN8 | UART_LCR_PARITY | UART_LCR_STOP) +#define UART_7O2 (uint8_t)(UART_LCR_WLEN7 | UART_LCR_PARITY | UART_LCR_STOP) + +/////////////////////////////////////////////////////////////////////////////// +// Definitions for typical UART 'fmode' settings +#define UART_FIFO_OFF (0x00) +#define UART_FIFO_1 (uint8_t)(UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1) +#define UART_FIFO_4 (uint8_t)(UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_4) +#define UART_FIFO_8 (uint8_t)(UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_8) +#define UART_FIFO_14 (uint8_t)(UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_14) + +void uart0Init(uint32_t baud, uint8_t mode, uint8_t fmode); +int uart0Putch(int ch); +uint16_t uart0Space(void); +const char *uart0Puts(const char *string); +int uart0TxEmpty(void); +void uart0TxFlush(void); +int uart0Getch(void); +int uart0GetchW(void); + +#endif diff --git a/embedded/board/arm/lpc17xx-common/libs/ldscripts/Makefile b/embedded/board/arm/lpc17xx-common/libs/ldscripts/Makefile new file mode 100644 index 0000000..76b56fd --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/ldscripts/Makefile @@ -0,0 +1,14 @@ +# Generic directory or leaf node makefile for OCERA make framework + +ifndef MAKERULES_DIR +MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) ) +endif + +ifeq ($(MAKERULES_DIR),) +all : default +.DEFAULT:: + @echo -e "\nThe Makefile.rules has not been found in this or parent directory\n" +else +include $(MAKERULES_DIR)/Makefile.rules +endif + diff --git a/embedded/board/arm/lpc17xx-common/libs/ldscripts/Makefile.omk b/embedded/board/arm/lpc17xx-common/libs/ldscripts/Makefile.omk new file mode 100644 index 0000000..01e6b77 --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/ldscripts/Makefile.omk @@ -0,0 +1,5 @@ +# -*- makefile -*- + +lib_LDSCRIPTS = $(notdir $(wildcard $(SOURCES_DIR)/*.ld*)) + +include_HEADERS = mem_loc.h keyval_loc.h diff --git a/embedded/board/arm/lpc17xx-common/libs/ldscripts/keyval_loc.h b/embedded/board/arm/lpc17xx-common/libs/ldscripts/keyval_loc.h new file mode 100644 index 0000000..2ee23e5 --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/ldscripts/keyval_loc.h @@ -0,0 +1,10 @@ +#ifndef _KEYVAL_LOC_H +#define _KEYVAL_LOC_H + +extern int _keyval_start; +extern int _keyval_page_len; + +#define KEYVAL_START ((unsigned int)&_keyval_start) +#define KEYVAL_PAGE_LEN ((unsigned int)&_keyval_page_len) + +#endif /* _KVPB_LOC */ diff --git a/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1754.ld-app b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1754.ld-app new file mode 100644 index 0000000..b3a1abc --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1754.ld-app @@ -0,0 +1,10 @@ +/***********************************************************************/ +/* */ +/* ROM.ld: Linker Script File */ +/* */ +/***********************************************************************/ + +INCLUDE "lpc1754.ld-cfg" + +INCLUDE "lpc17xx-base.ld-app" + diff --git a/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1754.ld-boot b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1754.ld-boot new file mode 100644 index 0000000..d7dd60f --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1754.ld-boot @@ -0,0 +1,9 @@ +/***********************************************************************/ +/* */ +/* ROM.ld: Linker Script File */ +/* */ +/***********************************************************************/ + +INCLUDE "lpc1754.ld-cfg" + +INCLUDE "lpc17xx-base.ld-boot" diff --git a/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1754.ld-cfg b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1754.ld-cfg new file mode 100644 index 0000000..ac7590a --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1754.ld-cfg @@ -0,0 +1,26 @@ + +KEYVAL_PAGE_LEN = 0x00001000; + +PROVIDE( __bbconf_pt_addr = 0 ); + +MEMORY +{ + /* LPC1754 : 128k ROM + 32k SRAM */ + /*------------------------------ */ + + + /* Main ROM region - 128k for LPC1754 */ + FLASHBOOT (rx) : ORIGIN = 0x00000000, LENGTH = 0x00007000 + KEYVAL (rx) : ORIGIN = 0x00007000, LENGTH = 0x00002000 + FLASHAPP (rx) : ORIGIN = 0x00009000, LENGTH = 0x00017000 + + /* local static RAM - 16k for LPC1754 */ + IRAM0 (rwx) : ORIGIN = 0x10000000, LENGTH = 16k + + /* stack location */ + STACK (rw) : ORIGIN = 0x10000000 + 0x00003FE0 - 4, LENGTH = 4 + + /* AHB SRAM - 16k for LPC1756 - often used for USB */ + IRAM1 (rwx) : ORIGIN = 0x2007C000, LENGTH = 16k +} + diff --git a/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1758.ld-app b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1758.ld-app new file mode 100644 index 0000000..0ee7bea --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1758.ld-app @@ -0,0 +1,10 @@ +/***********************************************************************/ +/* */ +/* ROM.ld: Linker Script File */ +/* */ +/***********************************************************************/ + +INCLUDE "lpc1758.ld-cfg" + +INCLUDE "lpc17xx-base.ld-app" + diff --git a/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1758.ld-boot b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1758.ld-boot new file mode 100644 index 0000000..c61c957 --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1758.ld-boot @@ -0,0 +1,9 @@ +/***********************************************************************/ +/* */ +/* ROM.ld: Linker Script File */ +/* */ +/***********************************************************************/ + +INCLUDE "lpc1758.ld-cfg" + +INCLUDE "lpc17xx-base.ld-boot" diff --git a/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1758.ld-cfg b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1758.ld-cfg new file mode 100644 index 0000000..c4e1e37 --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1758.ld-cfg @@ -0,0 +1,30 @@ + +KEYVAL_PAGE_LEN = 0x00001000; + +PROVIDE( __bbconf_pt_addr = 0 ); + +MEMORY +{ + /* LPC1758 : 512k ROM + 64k SRAM */ + /*------------------------------ */ + + + /* Main ROM region - 512k for LPC1758 */ + FLASHBOOT (rx) : ORIGIN = 0x00000000, LENGTH = 0x00007000 + KEYVAL (rx) : ORIGIN = 0x00007000, LENGTH = 0x00002000 + FLASHAPP (rx) : ORIGIN = 0x00009000, LENGTH = 0x00077000 + + /* local static RAM - 32k for LPC1758 */ + IRAM0 (rwx) : ORIGIN = 0x10000000, LENGTH = 32k + + /* stack location */ + STACK (rw) : ORIGIN = 0x10000000 + 0x00007FE0 - 4, LENGTH = 4 + + /* AHB SRAM - 16k for LPC1758 - often used for USB */ + IRAM1 (rwx) : ORIGIN = 0x2007C000, LENGTH = 16k + + /* AHB SRAM - 16k for LPC1758 */ + IRAM2 (rwx) : ORIGIN = 0x20080000, LENGTH = 16k + +} + diff --git a/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1766.ld-app b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1766.ld-app new file mode 100644 index 0000000..dd8f18c --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1766.ld-app @@ -0,0 +1,10 @@ +/***********************************************************************/ +/* */ +/* ROM.ld: Linker Script File */ +/* */ +/***********************************************************************/ + +INCLUDE "lpc1766.ld-cfg" + +INCLUDE "lpc17xx-base.ld-app" + diff --git a/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1766.ld-boot b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1766.ld-boot new file mode 100644 index 0000000..e5a9a75 --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1766.ld-boot @@ -0,0 +1,9 @@ +/***********************************************************************/ +/* */ +/* ROM.ld: Linker Script File */ +/* */ +/***********************************************************************/ + +INCLUDE "lpc1766.ld-cfg" + +INCLUDE "lpc17xx-base.ld-boot" diff --git a/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1766.ld-cfg b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1766.ld-cfg new file mode 100644 index 0000000..8a7c802 --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1766.ld-cfg @@ -0,0 +1,26 @@ + +KEYVAL_PAGE_LEN = 0x00001000; + +PROVIDE( __bbconf_pt_addr = 0 ); + +MEMORY +{ + /* LPC1768 : 512 ROM + 32k SRAM + 16k SRAM + 16k SRAM */ + /*--------------------------------------------------- */ + + + /* Main ROM region - 256k for LPC1766 */ + FLASHBOOT (rx) : ORIGIN = 0x00000000, LENGTH = 0x00007000 + KEYVAL (rx) : ORIGIN = 0x00007000, LENGTH = 0x00002000 + FLASHAPP (rx) : ORIGIN = 0x00009000, LENGTH = 0x00037000 + + /* local static RAM - 32k for LPC1766 */ + IRAM0 (rwx) : ORIGIN = 0x10000000, LENGTH = 32k + + /* stack location */ + STACK (rw) : ORIGIN = 0x10000000 + 0x00007FE0 - 4, LENGTH = 4 + + /* AHB SRAM - 16k for LPC1768 - often used for USB */ + IRAM1 (rwx) : ORIGIN = 0x2007C000, LENGTH = 32k +} + diff --git a/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1768.ld-app b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1768.ld-app new file mode 100644 index 0000000..b5e87e3 --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1768.ld-app @@ -0,0 +1,10 @@ +/***********************************************************************/ +/* */ +/* ROM.ld: Linker Script File */ +/* */ +/***********************************************************************/ + +INCLUDE "lpc1768.ld-cfg" + +INCLUDE "lpc17xx-base.ld-app" + diff --git a/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1768.ld-boot b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1768.ld-boot new file mode 100644 index 0000000..d2a6b89 --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1768.ld-boot @@ -0,0 +1,9 @@ +/***********************************************************************/ +/* */ +/* ROM.ld: Linker Script File */ +/* */ +/***********************************************************************/ + +INCLUDE "lpc1768.ld-cfg" + +INCLUDE "lpc17xx-base.ld-boot" diff --git a/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1768.ld-cfg b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1768.ld-cfg new file mode 100644 index 0000000..c37ec2d --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc1768.ld-cfg @@ -0,0 +1,26 @@ + +KEYVAL_PAGE_LEN = 0x00001000; + +PROVIDE( __bbconf_pt_addr = 0 ); + +MEMORY +{ + /* LPC1768 : 512 ROM + 32k SRAM + 16k SRAM + 16k SRAM */ + /*--------------------------------------------------- */ + + + /* Main ROM region - 512k for LPC1768 */ + FLASHBOOT (rx) : ORIGIN = 0x00000000, LENGTH = 0x00007000 + KEYVAL (rx) : ORIGIN = 0x00007000, LENGTH = 0x00002000 + FLASHAPP (rx) : ORIGIN = 0x00009000, LENGTH = 0x00077000 + + /* local static RAM - 32k for LPC1768 */ + IRAM0 (rwx) : ORIGIN = 0x10000000, LENGTH = 32k + + /* stack location */ + STACK (rw) : ORIGIN = 0x10000000 + 0x00007FE0 - 4, LENGTH = 4 + + /* AHB SRAM - 16k for LPC1768 - often used for USB */ + IRAM1 (rwx) : ORIGIN = 0x2007C000, LENGTH = 32k +} + diff --git a/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc17xx-base.ld-app b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc17xx-base.ld-app new file mode 100644 index 0000000..d3b7bb4 --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc17xx-base.ld-app @@ -0,0 +1,181 @@ +/***********************************************************************/ +/* */ +/* ROM.ld: Linker Script File */ +/* */ +/***********************************************************************/ + +ENTRY(g_pfnVectors) + +PROVIDE (_setup_board = 0); + +/* SECTION command : Define mapping of input sections */ +/* into output sections. */ + +SECTIONS +{ + /******************************************/ + /* code section */ + + /* "normal" code */ + + .text : + { + KEEP(*(.isr_vector .isr_vector.*)) + *(.text .text.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.gcc_except_table) + *(.rodata .rodata*) + *(.gnu.linkonce.r.*) + } >FLASHAPP + + /******************************************/ + /* .ctors .dtors are used for c++ constructors/destructors */ + .ctors : + { + . = ALIGN(4); + PROVIDE(__ctors_start = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end = .); + } >FLASHAPP + + .dtors : + { + . = ALIGN(4); + PROVIDE(__dtors_start = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end = .); + + . = ALIGN(4); + /* End Of .text section */ + _etext = .; + _sifastcode = .; + } >FLASHAPP + + + .keyval : + { + PROVIDE (_keyval_start = .); + PROVIDE (_keyval_page_len = KEYVAL_PAGE_LEN ); + }> KEYVAL + + .app : + { + PROVIDE (_mem_app_start = . ); + } > FLASHAPP + + .irqarea (NOLOAD): + { + . = ALIGN (256); + *(.irqarea .irqarea.*) + + } >IRAM0 + + /**************************************************/ + /* fastcode - copied at startup & executed in RAM */ + + .fastcode : + { + . = ALIGN (4); + _sfastcode = . ; + + *(.glue_7t) *(.glue_7) + *(.fastcode) + + /* add other modules here ... */ + + . = ALIGN (4); + _efastcode = . ; + _sidata = .; + } >IRAM0 AT>FLASHAPP + + /******************************************/ + /* This used for USB RAM section */ + .usbram (NOLOAD): + { + _usbram = . ; + *(.usbram) + . = ALIGN(4); + _eusbram = . ; + _usbram_end = . ; + } > IRAM1 + + /******************************************/ + /* data section */ + .data : + { + _sidata = LOADADDR (.data); + . = ALIGN(4); + _sdata = .; + + *(vtable vtable.*) + *(.data .data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + _edata = . ; + } >IRAM0 AT>FLASHAPP + + /******************************************/ + /* For no-init variables section */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + + *(.bss .bss.*) + *(.gnu.linkonce.b*) + *(COMMON) + + . = ALIGN(4); + _ebss = . ; + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); + } >IRAM0 + + .stack : + { + _stack = .; + } >STACK + + + /******************************************/ + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + /* .comment 0 : { *(.comment) } */ + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc17xx-base.ld-boot b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc17xx-base.ld-boot new file mode 100644 index 0000000..b2c64fa --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/ldscripts/lpc17xx-base.ld-boot @@ -0,0 +1,181 @@ +/***********************************************************************/ +/* */ +/* ROM.ld: Linker Script File */ +/* */ +/***********************************************************************/ + +ENTRY(g_pfnVectors) + +PROVIDE (_setup_board = 0); + +/* SECTION command : Define mapping of input sections */ +/* into output sections. */ + +SECTIONS +{ + /******************************************/ + /* code section */ + + /* "normal" code */ + + .text : + { + KEEP(*(.isr_vector .isr_vector.*)) + *(.text .text.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.gcc_except_table) + *(.rodata .rodata*) + *(.gnu.linkonce.r.*) + } >FLASHBOOT + + /******************************************/ + /* .ctors .dtors are used for c++ constructors/destructors */ + .ctors : + { + . = ALIGN(4); + PROVIDE(__ctors_start = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end = .); + } >FLASHBOOT + + .dtors : + { + . = ALIGN(4); + PROVIDE(__dtors_start = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end = .); + + . = ALIGN(4); + /* End Of .text section */ + _etext = .; + _sifastcode = .; + } >FLASHBOOT + + + .keyval : + { + PROVIDE (_keyval_start = .); + PROVIDE (_keyval_page_len = KEYVAL_PAGE_LEN ); + }> KEYVAL + + .app : + { + PROVIDE (_mem_app_start = . ); + } > FLASHAPP + + .irqarea (NOLOAD): + { + . = ALIGN (256); + *(.irqarea .irqarea.*) + + } >IRAM0 + + /**************************************************/ + /* fastcode - copied at startup & executed in RAM */ + + .fastcode : + { + . = ALIGN (4); + _sfastcode = . ; + + *(.glue_7t) *(.glue_7) + *(.fastcode) + + /* add other modules here ... */ + + . = ALIGN (4); + _efastcode = . ; + _sidata = .; + } >IRAM0 AT>FLASHBOOT + + /******************************************/ + /* This used for USB RAM section */ + .usbram (NOLOAD): + { + _usbram = . ; + *(.usbram) + . = ALIGN(4); + _eusbram = . ; + _usbram_end = . ; + } > IRAM1 + + /******************************************/ + /* data section */ + .data : + { + _sidata = LOADADDR (.data); + . = ALIGN(4); + _sdata = .; + + *(vtable vtable.*) + *(.data .data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + _edata = . ; + } >IRAM0 AT>FLASHBOOT + + /******************************************/ + /* For no-init variables section */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + + *(.bss .bss.*) + *(.gnu.linkonce.b*) + *(COMMON) + + . = ALIGN(4); + _ebss = . ; + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); + } >IRAM0 + + .stack : + { + _stack = .; + } >STACK + + + /******************************************/ + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + /* .comment 0 : { *(.comment) } */ + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/embedded/board/arm/lpc17xx-common/libs/ldscripts/mem_loc.h b/embedded/board/arm/lpc17xx-common/libs/ldscripts/mem_loc.h new file mode 100644 index 0000000..77b24d1 --- /dev/null +++ b/embedded/board/arm/lpc17xx-common/libs/ldscripts/mem_loc.h @@ -0,0 +1,8 @@ +#ifndef _MEM_LOC_H +#define _MEM_LOC_H + +extern int _mem_app_start; + +#define MEM_APP_START ((unsigned int)&_mem_app_start) + +#endif /* _MEM_LOC */ -- 2.39.2