From: ppisa <ppisa>
Date: Sun, 21 Mar 2004 15:04:41 +0000 (+0000)
Subject: Updated Intel 82527 support and added feeding of MSMCAN secret and hidden watchdog.
X-Git-Tag: CLT_COMM_CAN-lincan-0_2_2~22
X-Git-Url: http://rtime.felk.cvut.cz/gitweb/lincan.git/commitdiff_plain/cfabb1cb554e19976ed4ecd60c3d7eb9de24a43f

Updated Intel 82527 support and added feeding of MSMCAN secret and hidden watchdog.
---

diff --git a/lincan/src/i82527.c b/lincan/src/i82527.c
index 7b9602f..86e340d 100644
--- a/lincan/src/i82527.c
+++ b/lincan/src/i82527.c
@@ -106,7 +106,7 @@ int i82527_chip_config(struct chip_t *chip)
 		CANMSG("Error clearing message objects\n");
 		return -ENODEV;
 	}
-	if (i82527_config_irqs(chip,0x0a)) {
+	if (i82527_config_irqs(chip,iCTL_IE|iCTL_EIE)) { /* has been 0x0a */
 		CANMSG("Error configuring interrupts\n");
 		return -ENODEV;
 	}
@@ -288,6 +288,9 @@ int i82527_pre_read_config(struct chip_t *chip, struct msgobj_t *obj)
 	}
 	canobj_write_reg(chip,obj,(NEWD_RES|MLST_RES|TXRQ_RES|RMPD_RES), iMSGCTL1);
 	canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
+
+	DEBUGMSG("i82527_pre_read_config: configured obj at 0x%08lx\n",obj->obj_base_addr);
+
 	
 	return 0;
 }
@@ -301,8 +304,8 @@ int i82527_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
 	len = msg->length;
 	if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
 
-	canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|CPUU_SET|NEWD_RES),iMSGCTL1);
 	canobj_write_reg(chip,obj,(MVAL_SET|TXIE_SET|RXIE_RES|INTPD_RES),iMSGCTL0);
+	canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|CPUU_SET|NEWD_RES),iMSGCTL1);
 
 	if (extended || (msg->flags&MSG_EXT)) {
 		canobj_write_reg(chip,obj,(len<<4)|(MCFG_DIR|MCFG_XTD),iMSGCFG);
@@ -322,7 +325,7 @@ int i82527_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
 		canobj_write_reg(chip,obj,id1,iMSGID1);
 		canobj_write_reg(chip,obj,id0,iMSGID0);
 	}
-	canobj_write_reg(chip,obj,0xfa,iMSGCTL1);
+	canobj_write_reg(chip,obj,RMPD_UNC|TXRQ_UNC|CPUU_SET|NEWD_SET,iMSGCTL1);
 	for (i=0; i<len; i++) {
 		canobj_write_reg(chip,obj,msg->data[i],iMSGDAT0+i);
 	}
@@ -333,6 +336,8 @@ int i82527_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
 int i82527_send_msg(struct chip_t *chip, struct msgobj_t *obj,
 							struct canmsg_t *msg)
 {
+	canobj_write_reg(chip,obj,(MVAL_SET|TXIE_SET|RXIE_RES|INTPD_RES),iMSGCTL0);
+
 	if (msg->flags & MSG_RTR) {
 		canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|CPUU_RES|NEWD_SET),iMSGCTL1);
 	}
@@ -401,7 +406,7 @@ inline void i82527_irq_write_handler(struct chip_t *chip, struct msgobj_t *obj)
 {
 	int cmd;
 
-	canobj_write_reg(chip,obj,(MVAL_RES|TXIE_RES|RXIE_RES|INTPD_RES),+iMSGCTL0);
+	canobj_write_reg(chip,obj,(MVAL_RES|TXIE_RES|RXIE_RES|INTPD_RES),iMSGCTL0);
 
 	if(obj->tx_slot){
 		/* Do local transmitted message distribution if enabled */
@@ -434,66 +439,149 @@ inline void i82527_irq_write_handler(struct chip_t *chip, struct msgobj_t *obj)
 	} 
 }
 
-inline void i82527_irq_read_handler(struct chip_t *chip, struct msgobj_t *obj,
-				    unsigned long message_id)
+inline void i82527_irq_read_handler(struct chip_t *chip, struct msgobj_t *obj, int objnum)
 {
-	int i=0, tmp=1, len;
+	int i;
+	unsigned long message_id;
+	int msgcfg, msgctl1;
+	
+	msgctl1=canobj_read_reg(chip,obj,iMSGCTL1);
+	if(msgctl1 & NEWD_RES)
+		return;
 	
-	while (tmp) {
-		canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|MLST_RES|NEWD_RES),iMSGCTL1);
-		canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
+	do {
+		if(objnum != 14) {
+			canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|MLST_UNC|NEWD_RES),iMSGCTL1);
+			canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
+		}
+
+		msgcfg = canobj_read_reg(chip,obj,iMSGCFG);
+
+		if (msgcfg&MCFG_XTD) {
+			message_id =canobj_read_reg(chip,obj,iMSGID3);
+			message_id|=canobj_read_reg(chip,obj,iMSGID2)<<8;
+			message_id|=canobj_read_reg(chip,obj,iMSGID1)<<16;
+			message_id|=canobj_read_reg(chip,obj,iMSGID0)<<24;
+			message_id>>=3;
+			obj->rx_msg.flags = MSG_EXT;
+
+		}
+		else {
+			message_id =canobj_read_reg(chip,obj,iMSGID1);
+			message_id|=canobj_read_reg(chip,obj,iMSGID0)<<8;
+			message_id>>=5;
+			obj->rx_msg.flags = 0;
+		}
+
+		obj->rx_msg.length = (msgcfg >> 4) & 0xf;
+		if(obj->rx_msg.length > CAN_MSG_LENGTH) obj->rx_msg.length = CAN_MSG_LENGTH;
 
-		len = (canobj_read_reg(chip,obj,iMSGCFG) >> 4) & 0xf;
-		obj->rx_msg.length = len;
 		obj->rx_msg.id = message_id;
 
-		if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
 		for (i=0; i < obj->rx_msg.length; i++)
 			obj->rx_msg.data[i] = canobj_read_reg(chip,obj,iMSGDAT0+i);
 
-		canque_filter_msg2edges(obj->qends, &obj->rx_msg);
-
-		if (!((tmp=canobj_read_reg(chip,obj,iMSGCTL1)) & NEWD_SET)) {
-			break;
+		
+		if(objnum != 14) {
+			/* if NEWD is set after data read, then read data are likely inconsistent */
+			msgctl1=canobj_read_reg(chip,obj,iMSGCTL1);
+			if(msgctl1 & NEWD_SET) {
+				CANMSG("i82527_irq_read_handler: object %d data overwritten\n",objnum);
+				continue;
+			}
 		}
+		else {
+			/* this object is special and data are queued in the shadow register */
+			canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
+			canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|MLST_UNC|NEWD_RES),iMSGCTL1);
+			msgctl1=canobj_read_reg(chip,obj,iMSGCTL1);
+		}
+		
 
-		if (tmp & MLST_SET)
-			CANMSG("Message lost!\n");
+		canque_filter_msg2edges(obj->qends, &obj->rx_msg);
+		
+		if (msgctl1 & NEWD_SET)
+			continue;
+		
+		if (msgctl1 & MLST_SET) {
+			canobj_write_reg(chip,obj,(RMPD_UNC|TXRQ_UNC|MLST_RES|NEWD_UNC),iMSGCTL1);
+			CANMSG("i82527_irq_read_handler: object %d message lost\n",objnum);
+		}
+		
+		return;
 
-	}
+	} while(1);
 }
 
+/*
+			if (msgcfg&MCFG_XTD) {
+				message_id =canobj_read_reg(chip,obj,iMSGID3);
+				message_id|=canobj_read_reg(chip,obj,iMSGID2)<<8;
+				message_id|=canobj_read_reg(chip,obj,iMSGID1)<<16;
+				message_id|=canobj_read_reg(chip,obj,iMSGID0)<<24;
+				message_id>>=3;
+			}
+			else {
+				message_id =canobj_read_reg(chip,obj,iMSGID1);
+				message_id|=canobj_read_reg(chip,obj,iMSGID0)<<8;
+				message_id>>=5;
+			}
+
+			can_spin_lock(&hardware_p->rtr_lock);
+			rtr_search=hardware_p->rtr_queue;
+			while (rtr_search != NULL) {
+				if (rtr_search->id == message_id)
+					break;
+				rtr_search=rtr_search->next;
+			}
+			can_spin_unlock(&hardware_p->rtr_lock);
+			if ((rtr_search!=NULL) && (rtr_search->id==message_id))
+				i82527_irq_rtr_handler(chip, obj, rtr_search, message_id);
+			else
+				i82527_irq_read_handler(chip, obj, message_id); 
+*/
+
 can_irqreturn_t i82527_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
 {
-	int id0=0, id1=0, id2=0, id3=0;
+	unsigned char msgcfg;
 
 	unsigned irq_register;
 	unsigned object;
 	struct chip_t *chip=(struct chip_t *)dev_id;
 	struct msgobj_t *obj;
-	unsigned long message_id;
-	struct rtr_id *rtr_search;
 
 	/*put_reg=device->hwspecops->write_register;*/
 	/*get_reg=device->hwspecops->read_register;*/
 
 	irq_register = i82527_seg_read_reg(chip, iIRQ);
 
-	while (irq_register) {
+	if(!irq_register) {
+		DEBUGMSG("i82527: spurious IRQ\n");
+		return CAN_IRQ_NONE;
+	}
+
 
+	do {
+
+		DEBUGMSG("i82527: iIRQ 0x%02x\n",irq_register);
+		
 		if (irq_register == 0x01) {
 			DEBUGMSG("Status register: 0x%x\n",can_read_reg(chip, iSTAT));
-			return CAN_IRQ_NONE;
+			continue;
+			/*return CAN_IRQ_NONE;*/
 		}
 		
 		if (irq_register == 0x02)
 			object = 14;
-		else
+		else if(irq_register < 14)
 			object = irq_register-3;
+		else
+			return CAN_IRQ_NONE;
 
 		obj=chip->msgobj[object];
-
-		if (canobj_read_reg(chip,obj,iMSGCFG) & MCFG_DIR) {
+		
+		msgcfg = canobj_read_reg(chip,obj,iMSGCFG);
+		if (msgcfg & MCFG_DIR) {
 			can_msgobj_set_fl(obj,TX_REQUEST);
 			while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
 				can_msgobj_clear_fl(obj,TX_REQUEST);
@@ -507,35 +595,11 @@ can_irqreturn_t i82527_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
 		}
 		else { 
 
-			if (extended) {
-				id0=canobj_read_reg(chip,obj,iMSGID3);
-				id1=canobj_read_reg(chip,obj,iMSGID2)<<8;
-				id2=canobj_read_reg(chip,obj,iMSGID1)<<16;
-				id3=canobj_read_reg(chip,obj,iMSGID0)<<24;
-				message_id=(id0|id1|id2|id3)>>3;
-			}
-			else {
-				id0=canobj_read_reg(chip,obj,iMSGID1);
-				id1=canobj_read_reg(chip,obj,iMSGID0)<<8;
-				message_id=(id0|id1)>>5;
-			}
-
-			can_spin_lock(&hardware_p->rtr_lock);
-			rtr_search=hardware_p->rtr_queue;
-			while (rtr_search != NULL) {
-				if (rtr_search->id == message_id)
-					break;
-				rtr_search=rtr_search->next;
-			}
-			can_spin_unlock(&hardware_p->rtr_lock);
-			if ((rtr_search!=NULL) && (rtr_search->id==message_id))
-				i82527_irq_rtr_handler(chip, obj, rtr_search, message_id);
-			else
-				i82527_irq_read_handler(chip, obj, message_id); 
+			i82527_irq_read_handler(chip, obj, object); 
 		}
 
-		irq_register=i82527_seg_read_reg(chip, iIRQ);
-	}
+	} while((irq_register=i82527_seg_read_reg(chip, iIRQ)) != 0);
+
 	return CAN_IRQ_HANDLED;
 }
 
diff --git a/lincan/src/msmcan.c b/lincan/src/msmcan.c
index e9f68f5..1d6fb51 100644
--- a/lincan/src/msmcan.c
+++ b/lincan/src/msmcan.c
@@ -63,6 +63,27 @@ int msmcan_reset(struct candevice_t *candev)
 	   registers of the card but the third in order to make a hard reset */
 	/* outb (1, msmcan_base + candev->res_addr); */
 
+
+	/* terrible MSMCAN reset design - best to comment out */
+	if(0) {
+		int tic=jiffies;
+		int tac;
+		
+		msmcan_write_register(iCTL_INI, chip->chip_base_addr+iCTL);
+		/*CLKOUT stopped (iCPU_CEN=0) */
+		msmcan_write_register(iCPU_DSC, chip->chip_base_addr+iCPU);
+		while(!(msmcan_read_register(chip->chip_base_addr+iCPU)&iCPU_CEN)){
+			tac=jiffies;
+			if((tac-tic)>HZ*2){
+				CANMSG("Unable to reset board\n");
+				return -EIO;
+			}
+			schedule();
+		}
+		
+	
+	}
+
 	can_disable_irq(chip->chip_irq);
 	msmcan_write_register(iCTL_INI, chip->chip_base_addr+iCTL);
 	can_enable_irq(chip->chip_irq);
@@ -110,7 +131,8 @@ int msmcan_init_chip_data(struct candevice_t *candev, int chipnr)
 	candev->chip[chipnr]->chip_base_addr=
 	    candev->io_addr << 16;
 	candev->chip[chipnr]->clock = 16000000;
-	candev->chip[chipnr]->int_cpu_reg = iCPU_DSC;
+	/* The CLKOUT has to be enabled to reset MSMCAN MAX1232 watchdog */
+	candev->chip[chipnr]->int_cpu_reg = iCPU_DSC | iCPU_CEN;
 	candev->chip[chipnr]->int_clk_reg = iCLK_SL1;
 	candev->chip[chipnr]->int_bus_reg = iBUS_CBY;